osfmk/i386/Diagnostics.c

   1 /*
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   6  * This file contains Original Code and/or Modifications of Original Code
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   8  * Version 2.0 (the 'License'). You may not use this file except in
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  10  * may not be used to create, or enable the creation or redistribution of,
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  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
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  23  * Please see the License for the specific language governing rights and
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  27  */
  28 /*
  29  * @OSF_FREE_COPYRIGHT@
  30  */
  31 /*
  32  * @APPLE_FREE_COPYRIGHT@
  33  */
  34
  35 /*
  36  *      Author: Bill Angell, Apple
  37  *      Date:   10/auht-five
  38  *
  39  *      Random diagnostics, augmented Derek Kumar 2011
  40  *
  41  *
  42  */
  43
  44
  45 #include <kern/machine.h>
  46 #include <kern/processor.h>
  47 #include <mach/machine.h>
  48 #include <mach/processor_info.h>
  49 #include <mach/mach_types.h>
  50 #include <mach/boolean.h>
  51 #include <kern/thread.h>
  52 #include <kern/task.h>
  53 #include <kern/ipc_kobject.h>
  54 #include <mach/vm_param.h>
  55 #include <ipc/port.h>
  56 #include <ipc/ipc_entry.h>
  57 #include <ipc/ipc_space.h>
  58 #include <ipc/ipc_object.h>
  59 #include <ipc/ipc_port.h>
  60 #include <vm/vm_kern.h>
  61 #include <vm/vm_map.h>
  62 #include <vm/vm_page.h>
  63 #include <vm/pmap.h>
  64 #include <pexpert/pexpert.h>
  65 #include <console/video_console.h>
  66 #include <i386/cpu_data.h>
  67 #include <i386/Diagnostics.h>
  68 #include <i386/mp.h>
  69 #include <i386/pmCPU.h>
  70 #include <i386/tsc.h>
  71 #include <mach/i386/syscall_sw.h>
  72 #include <kern/kalloc.h>
  73 #include <sys/kdebug.h>
  74 #include <i386/machine_cpu.h>
  75 #include <i386/misc_protos.h>
  76 #include <i386/cpuid.h>
  77
  78 #if MONOTONIC
  79 #include <kern/monotonic.h>
  80 #endif /* MONOTONIC */
  81
  82 #define PERMIT_PERMCHECK (0)
  83
  84 diagWork        dgWork;
  85 uint64_t        lastRuptClear = 0ULL;
  86 boolean_t       diag_pmc_enabled = FALSE;
  87 void cpu_powerstats(void *);
  88
  89 typedef struct {
  90         uint64_t caperf;
  91         uint64_t cmperf;
  92         uint64_t ccres[6];
  93         uint64_t crtimes[CPU_RTIME_BINS];
  94         uint64_t citimes[CPU_ITIME_BINS];
  95         uint64_t crtime_total;
  96         uint64_t citime_total;
  97         uint64_t cpu_idle_exits;
  98         uint64_t cpu_insns;
  99         uint64_t cpu_ucc;
 100         uint64_t cpu_urc;
 101 #if     DIAG_ALL_PMCS
 102         uint64_t gpmcs[4];
 103 #endif /* DIAG_ALL_PMCS */
 104 } core_energy_stat_t;
 105
 106 typedef struct {
 107         uint64_t pkes_version;
 108         uint64_t pkg_cres[2][7];
 109         uint64_t pkg_power_unit;
 110         uint64_t pkg_energy;
 111         uint64_t pp0_energy;
 112         uint64_t pp1_energy;
 113         uint64_t ddr_energy;
 114         uint64_t llc_flushed_cycles;
 115         uint64_t ring_ratio_instantaneous;
 116         uint64_t IA_frequency_clipping_cause;
 117         uint64_t GT_frequency_clipping_cause;
 118         uint64_t pkg_idle_exits;
 119         uint64_t pkg_rtimes[CPU_RTIME_BINS];
 120         uint64_t pkg_itimes[CPU_ITIME_BINS];
 121         uint64_t mbus_delay_time;
 122         uint64_t mint_delay_time;
 123         uint32_t ncpus;
 124         core_energy_stat_t cest[];
 125 } pkg_energy_statistics_t;
 126
 127
 128 int
 129 diagCall64(x86_saved_state_t * state)
 130 {
 131         uint64_t        curpos, i, j;
 132         uint64_t        selector, data;
 133         uint64_t        currNap, durNap;
 134         x86_saved_state64_t     *regs;
 135         boolean_t       diagflag;
 136         uint32_t        rval = 0;
 137
 138         assert(is_saved_state64(state));
 139         regs = saved_state64(state);
 140
 141         diagflag = ((dgWork.dgFlags & enaDiagSCs) != 0);
 142         selector = regs->rdi;
 143
 144         switch (selector) {     /* Select the routine */
 145         case dgRuptStat:        /* Suck Interruption statistics */
 146                 (void) ml_set_interrupts_enabled(TRUE);
 147                 data = regs->rsi; /* Get the number of processors */
 148
 149                 if (data == 0) { /* If no location is specified for data, clear all
 150                                   * counts
 151                                   */
 152                         for (i = 0; i < real_ncpus; i++) {      /* Cycle through
 153                                                                  * processors */
 154                                 for (j = 0; j < 256; j++) {
 155                                         cpu_data_ptr[i]->cpu_hwIntCnt[j] = 0;
 156                                 }
 157                         }
 158
 159                         lastRuptClear = mach_absolute_time();   /* Get the time of clear */
 160                         rval = 1;       /* Normal return */
 161                         (void) ml_set_interrupts_enabled(FALSE);
 162                         break;
 163                 }
 164
 165                 (void) copyout((char *) &real_ncpus, data, sizeof(real_ncpus)); /* Copy out number of
 166                                                                                  * processors */
 167                 currNap = mach_absolute_time(); /* Get the time now */
 168                 durNap = currNap - lastRuptClear;       /* Get the last interval
 169                                                          * duration */
 170                 if (durNap == 0) {
 171                         durNap = 1;     /* This is a very short time, make it
 172                                          * bigger */
 173                 }
 174                 curpos = data + sizeof(real_ncpus);     /* Point to the next
 175                                                          * available spot */
 176
 177                 for (i = 0; i < real_ncpus; i++) {      /* Move 'em all out */
 178                         (void) copyout((char *) &durNap, curpos, 8);    /* Copy out the time
 179                                                                          * since last clear */
 180                         (void) copyout((char *) &cpu_data_ptr[i]->cpu_hwIntCnt, curpos + 8, 256 * sizeof(uint32_t));    /* Copy out interrupt
 181                                                                                                                          * data for this
 182                                                                                                                          * processor */
 183                         curpos = curpos + (256 * sizeof(uint32_t) + 8); /* Point to next out put
 184                                                                          * slot */
 185                 }
 186                 rval = 1;
 187                 (void) ml_set_interrupts_enabled(FALSE);
 188                 break;
 189
 190         case dgPowerStat:
 191         {
 192                 uint32_t c2l = 0, c2h = 0, c3l = 0, c3h = 0, c6l = 0, c6h = 0, c7l = 0, c7h = 0;
 193                 uint32_t pkg_unit_l = 0, pkg_unit_h = 0, pkg_ecl = 0, pkg_ech = 0;
 194
 195                 pkg_energy_statistics_t pkes;
 196                 core_energy_stat_t cest;
 197
 198                 bzero(&pkes, sizeof(pkes));
 199                 bzero(&cest, sizeof(cest));
 200
 201                 pkes.pkes_version = 1ULL;
 202                 rdmsr_carefully(MSR_IA32_PKG_C2_RESIDENCY, &c2l, &c2h);
 203                 rdmsr_carefully(MSR_IA32_PKG_C3_RESIDENCY, &c3l, &c3h);
 204                 rdmsr_carefully(MSR_IA32_PKG_C6_RESIDENCY, &c6l, &c6h);
 205                 rdmsr_carefully(MSR_IA32_PKG_C7_RESIDENCY, &c7l, &c7h);
 206
 207                 pkes.pkg_cres[0][0] = ((uint64_t)c2h << 32) | c2l;
 208                 pkes.pkg_cres[0][1] = ((uint64_t)c3h << 32) | c3l;
 209                 pkes.pkg_cres[0][2] = ((uint64_t)c6h << 32) | c6l;
 210                 pkes.pkg_cres[0][3] = ((uint64_t)c7h << 32) | c7l;
 211
 212                 uint64_t c8r = ~0ULL, c9r = ~0ULL, c10r = ~0ULL;
 213
 214                 rdmsr64_carefully(MSR_IA32_PKG_C8_RESIDENCY, &c8r);
 215                 rdmsr64_carefully(MSR_IA32_PKG_C9_RESIDENCY, &c9r);
 216                 rdmsr64_carefully(MSR_IA32_PKG_C10_RESIDENCY, &c10r);
 217
 218                 pkes.pkg_cres[0][4] = c8r;
 219                 pkes.pkg_cres[0][5] = c9r;
 220                 pkes.pkg_cres[0][6] = c10r;
 221
 222                 pkes.ddr_energy = ~0ULL;
 223                 rdmsr64_carefully(MSR_IA32_DDR_ENERGY_STATUS, &pkes.ddr_energy);
 224                 pkes.llc_flushed_cycles = ~0ULL;
 225                 rdmsr64_carefully(MSR_IA32_LLC_FLUSHED_RESIDENCY_TIMER, &pkes.llc_flushed_cycles);
 226
 227                 pkes.ring_ratio_instantaneous = ~0ULL;
 228                 rdmsr64_carefully(MSR_IA32_RING_PERF_STATUS, &pkes.ring_ratio_instantaneous);
 229
 230                 pkes.IA_frequency_clipping_cause = ~0ULL;
 231
 232                 uint32_t ia_perf_limits = MSR_IA32_IA_PERF_LIMIT_REASONS;
 233                 /* Should perhaps be a generic register map module for these
 234                  * registers with identical functionality that were renumbered.
 235                  */
 236                 switch (cpuid_cpufamily()) {
 237                 case CPUFAMILY_INTEL_SKYLAKE:
 238                 case CPUFAMILY_INTEL_KABYLAKE:
 239                 case CPUFAMILY_INTEL_ICELAKE:
 240                         ia_perf_limits = MSR_IA32_IA_PERF_LIMIT_REASONS_SKL;
 241                         break;
 242                 default:
 243                         break;
 244                 }
 245
 246                 rdmsr64_carefully(ia_perf_limits, &pkes.IA_frequency_clipping_cause);
 247
 248                 pkes.GT_frequency_clipping_cause = ~0ULL;
 249                 rdmsr64_carefully(MSR_IA32_GT_PERF_LIMIT_REASONS, &pkes.GT_frequency_clipping_cause);
 250
 251                 rdmsr_carefully(MSR_IA32_PKG_POWER_SKU_UNIT, &pkg_unit_l, &pkg_unit_h);
 252                 rdmsr_carefully(MSR_IA32_PKG_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
 253                 pkes.pkg_power_unit = ((uint64_t)pkg_unit_h << 32) | pkg_unit_l;
 254                 pkes.pkg_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;
 255
 256                 rdmsr_carefully(MSR_IA32_PP0_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
 257                 pkes.pp0_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;
 258
 259                 rdmsr_carefully(MSR_IA32_PP1_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
 260                 pkes.pp1_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;
 261
 262                 pkes.pkg_idle_exits = current_cpu_datap()->lcpu.package->package_idle_exits;
 263                 pkes.ncpus = real_ncpus;
 264
 265                 (void) ml_set_interrupts_enabled(TRUE);
 266
 267                 copyout(&pkes, regs->rsi, sizeof(pkes));
 268                 curpos = regs->rsi + sizeof(pkes);
 269
 270                 mp_cpus_call(CPUMASK_ALL, ASYNC, cpu_powerstats, NULL);
 271
 272                 for (i = 0; i < real_ncpus; i++) {
 273                         (void) ml_set_interrupts_enabled(FALSE);
 274
 275                         cest.caperf = cpu_data_ptr[i]->cpu_aperf;
 276                         cest.cmperf = cpu_data_ptr[i]->cpu_mperf;
 277                         cest.ccres[0] = cpu_data_ptr[i]->cpu_c3res;
 278                         cest.ccres[1] = cpu_data_ptr[i]->cpu_c6res;
 279                         cest.ccres[2] = cpu_data_ptr[i]->cpu_c7res;
 280
 281                         bcopy(&cpu_data_ptr[i]->cpu_rtimes[0], &cest.crtimes[0], sizeof(cest.crtimes));
 282                         bcopy(&cpu_data_ptr[i]->cpu_itimes[0], &cest.citimes[0], sizeof(cest.citimes));
 283
 284                         cest.citime_total = cpu_data_ptr[i]->cpu_itime_total;
 285                         cest.crtime_total = cpu_data_ptr[i]->cpu_rtime_total;
 286                         cest.cpu_idle_exits = cpu_data_ptr[i]->cpu_idle_exits;
 287 #if MONOTONIC
 288                         cest.cpu_insns = cpu_data_ptr[i]->cpu_monotonic.mtc_counts[MT_CORE_INSTRS];
 289                         cest.cpu_ucc = cpu_data_ptr[i]->cpu_monotonic.mtc_counts[MT_CORE_CYCLES];
 290                         cest.cpu_urc = cpu_data_ptr[i]->cpu_monotonic.mtc_counts[MT_CORE_REFCYCLES];
 291 #endif /* MONOTONIC */
 292 #if DIAG_ALL_PMCS
 293                         bcopy(&cpu_data_ptr[i]->cpu_gpmcs[0], &cest.gpmcs[0], sizeof(cest.gpmcs));
 294 #endif /* DIAG_ALL_PMCS */
 295                         (void) ml_set_interrupts_enabled(TRUE);
 296
 297                         copyout(&cest, curpos, sizeof(cest));
 298                         curpos += sizeof(cest);
 299                 }
 300                 rval = 1;
 301                 (void) ml_set_interrupts_enabled(FALSE);
 302         }
 303         break;
 304         case dgEnaPMC:
 305         {
 306                 boolean_t enable = TRUE;
 307                 uint32_t cpuinfo[4];
 308                 /* Require architectural PMC v2 or higher, corresponding to
 309                  * Merom+, or equivalent virtualised facility.
 310                  */
 311                 do_cpuid(0xA, &cpuinfo[0]);
 312                 if ((cpuinfo[0] & 0xFF) >= 2) {
 313                         mp_cpus_call(CPUMASK_ALL, ASYNC, cpu_pmc_control, &enable);
 314                         diag_pmc_enabled = TRUE;
 315                 }
 316                 rval = 1;
 317         }
 318         break;
 319 #if     DEVELOPMENT || DEBUG
 320         case dgGzallocTest:
 321         {
 322                 (void) ml_set_interrupts_enabled(TRUE);
 323                 if (diagflag) {
 324                         unsigned *ptr = (unsigned *)kalloc(1024);
 325                         kfree(ptr, 1024);
 326                         *ptr = 0x42;
 327                 }
 328                 (void) ml_set_interrupts_enabled(FALSE);
 329         }
 330         break;
 331 #endif
 332
 333 #if DEVELOPMENT || DEBUG
 334         case    dgPermCheck:
 335         {
 336                 (void) ml_set_interrupts_enabled(TRUE);
 337                 if (diagflag) {
 338                         rval = pmap_permissions_verify(kernel_pmap, kernel_map, 0, ~0ULL);
 339                 }
 340                 (void) ml_set_interrupts_enabled(FALSE);
 341         }
 342         break;
 343 #endif /* DEVELOPMENT || DEBUG */
 344         default:                /* Handle invalid ones */
 345                 rval = 0;       /* Return an exception */
 346         }
 347
 348         regs->rax = rval;
 349
 350         assert(ml_get_interrupts_enabled() == FALSE);
 351         return rval;
 352 }
 353
 354 void
 355 cpu_powerstats(__unused void *arg)
 356 {
 357         cpu_data_t *cdp = current_cpu_datap();
 358         __unused int cnum = cdp->cpu_number;
 359         uint32_t cl = 0, ch = 0, mpl = 0, mph = 0, apl = 0, aph = 0;
 360
 361         rdmsr_carefully(MSR_IA32_MPERF, &mpl, &mph);
 362         rdmsr_carefully(MSR_IA32_APERF, &apl, &aph);
 363
 364         cdp->cpu_mperf = ((uint64_t)mph << 32) | mpl;
 365         cdp->cpu_aperf = ((uint64_t)aph << 32) | apl;
 366
 367         uint64_t ctime = mach_absolute_time();
 368         cdp->cpu_rtime_total += ctime - cdp->cpu_ixtime;
 369         cdp->cpu_ixtime = ctime;
 370
 371         rdmsr_carefully(MSR_IA32_CORE_C3_RESIDENCY, &cl, &ch);
 372         cdp->cpu_c3res = ((uint64_t)ch << 32) | cl;
 373
 374         rdmsr_carefully(MSR_IA32_CORE_C6_RESIDENCY, &cl, &ch);
 375         cdp->cpu_c6res = ((uint64_t)ch << 32) | cl;
 376
 377         rdmsr_carefully(MSR_IA32_CORE_C7_RESIDENCY, &cl, &ch);
 378         cdp->cpu_c7res = ((uint64_t)ch << 32) | cl;
 379
 380         if (diag_pmc_enabled) {
 381 #if MONOTONIC
 382                 mt_update_fixed_counts();
 383 #else /* MONOTONIC */
 384                 uint64_t insns = read_pmc(FIXED_PMC0);
 385                 uint64_t ucc = read_pmc(FIXED_PMC1);
 386                 uint64_t urc = read_pmc(FIXED_PMC2);
 387 #endif /* !MONOTONIC */
 388 #if DIAG_ALL_PMCS
 389                 int i;
 390
 391                 for (i = 0; i < 4; i++) {
 392                         cdp->cpu_gpmcs[i] = read_pmc(i);
 393                 }
 394 #endif /* DIAG_ALL_PMCS */
 395 #if !MONOTONIC
 396                 cdp->cpu_cur_insns = insns;
 397                 cdp->cpu_cur_ucc = ucc;
 398                 cdp->cpu_cur_urc = urc;
 399 #endif /* !MONOTONIC */
 400         }
 401 }
 402
 403 void
 404 cpu_pmc_control(void *enablep)
 405 {
 406 #if !MONOTONIC
 407         boolean_t enable = *(boolean_t *)enablep;
 408         cpu_data_t      *cdp = current_cpu_datap();
 409
 410         if (enable) {
 411                 wrmsr64(0x38F, 0x70000000FULL);
 412                 wrmsr64(0x38D, 0x333);
 413                 set_cr4(get_cr4() | CR4_PCE);
 414         } else {
 415                 wrmsr64(0x38F, 0);
 416                 wrmsr64(0x38D, 0);
 417                 set_cr4((get_cr4() & ~CR4_PCE));
 418         }
 419         cdp->cpu_fixed_pmcs_enabled = enable;
 420 #else /* !MONOTONIC */
 421 #pragma unused(enablep)
 422 #endif /* MONOTONIC */
 423 }