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1 /*
2 * Copyright (c) 2007-2018 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 /* CMU_ENDHIST */
32 /*
33 * Mach Operating System
34 * Copyright (c) 1991,1990 Carnegie Mellon University
35 * All Rights Reserved.
36 *
37 * Permission to use, copy, modify and distribute this software and its
38 * documentation is hereby granted, provided that both the copyright
39 * notice and this permission notice appear in all copies of the
40 * software, derivative works or modified versions, and any portions
41 * thereof, and that both notices appear in supporting documentation.
42 *
43 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
44 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
45 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
46 *
47 * Carnegie Mellon requests users of this software to return to
48 *
49 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
50 * School of Computer Science
51 * Carnegie Mellon University
52 * Pittsburgh PA 15213-3890
53 *
54 * any improvements or extensions that they make and grant Carnegie Mellon
55 * the rights to redistribute these changes.
56 */
57
58 /*
59 */
60
61 /*
62 * Processor registers for ARM
63 */
64 #ifndef _ARM_PROC_REG_H_
65 #define _ARM_PROC_REG_H_
66
67 #if defined (__arm64__)
68 #include <pexpert/arm64/board_config.h>
69 #elif defined (__arm__)
70 #include <pexpert/arm/board_config.h>
71 #endif
72
73 #if defined (ARMA7)
74 #define __ARM_ARCH__ 7
75 #define __ARM_SUB_ARCH__ CPU_ARCH_ARMv7k
76 #define __ARM_VMSA__ 7
77 #define __ARM_VFP__ 3
78 #if defined(__XNU_UP__)
79 #define __ARM_SMP__ 0
80 #else
81 #define __ARM_SMP__ 1
82 /* For SMP kernels, force physical aperture to be mapped at PTE level so that its mappings
83 * can be updated to reflect cache attribute changes on alias mappings. This prevents
84 * prefetched physical aperture cachelines from becoming dirty in L1 due to a write to
85 * an uncached alias mapping on the same core. Subsequent uncached writes from another
86 * core may not snoop this line, and the dirty line may end up being evicted later to
87 * effectively overwrite the uncached writes from other cores. */
88 #define __ARM_PTE_PHYSMAP__ 1
89 #endif
90 /* __ARMA7_SMP__ controls whether we are consistent with the A7 MP_CORE spec; needed because entities other than
91 * the xnu-managed processors may need to snoop our cache operations.
92 */
93 #define __ARMA7_SMP__ 1
94 #define __ARM_COHERENT_CACHE__ 1
95 #define __ARM_DEBUG__ 7
96 #define __ARM_USER_PROTECT__ 1
97 #define __ARM_TIME_TIMEBASE_ONLY__ 1
98
99 #elif defined (APPLETYPHOON)
100 #define __ARM_ARCH__ 8
101 #define __ARM_VMSA__ 8
102 #define __ARM_SMP__ 1
103 #define __ARM_VFP__ 4
104 #define __ARM_COHERENT_CACHE__ 1
105 #define __ARM_COHERENT_IO__ 1
106 #define __ARM_IC_NOALIAS_ICACHE__ 1
107 #define __ARM_DEBUG__ 7
108 #define __ARM_ENABLE_SWAP__ 1
109 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
110 #define __ARM64_PMAP_SUBPAGE_L1__ 1
111 #define __ARM_KERNEL_PROTECT__ 1
112
113 #elif defined (APPLETWISTER)
114 #define __ARM_ARCH__ 8
115 #define __ARM_VMSA__ 8
116 #define __ARM_SMP__ 1
117 #define __ARM_VFP__ 4
118 #define __ARM_COHERENT_CACHE__ 1
119 #define __ARM_COHERENT_IO__ 1
120 #define __ARM_IC_NOALIAS_ICACHE__ 1
121 #define __ARM_DEBUG__ 7
122 #define __ARM_ENABLE_SWAP__ 1
123 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
124 #define __ARM_16K_PG__ 1
125 #define __ARM64_PMAP_SUBPAGE_L1__ 1
126 #define __ARM_KERNEL_PROTECT__ 1
127
128 #elif defined (APPLEHURRICANE)
129 #define __ARM_ARCH__ 8
130 #define __ARM_VMSA__ 8
131 #define __ARM_SMP__ 1
132 #define __ARM_VFP__ 4
133 #define __ARM_COHERENT_CACHE__ 1
134 #define __ARM_COHERENT_IO__ 1
135 #define __ARM_IC_NOALIAS_ICACHE__ 1
136 #define __ARM_DEBUG__ 7
137 #define __ARM_ENABLE_SWAP__ 1
138 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
139 #define __ARM_16K_PG__ 1
140 #define __ARM64_PMAP_SUBPAGE_L1__ 1
141 #define __ARM_KERNEL_PROTECT__ 1
142 #define __ARM_GLOBAL_SLEEP_BIT__ 1
143 #define __ARM_PAN_AVAILABLE__ 1
144
145 #elif defined (APPLEMONSOON)
146 #define __ARM_ARCH__ 8
147 #define __ARM_VMSA__ 8
148 #define __ARM_SMP__ 1
149 #define __ARM_AMP__ 1
150 #define __ARM_VFP__ 4
151 #define __ARM_COHERENT_CACHE__ 1
152 #define __ARM_COHERENT_IO__ 1
153 #define __ARM_IC_NOALIAS_ICACHE__ 1
154 #define __ARM_DEBUG__ 7
155 #define __ARM_ENABLE_SWAP__ 1
156 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
157 #define __ARM_16K_PG__ 1
158 #define __ARM64_PMAP_SUBPAGE_L1__ 1
159 #define __ARM_KERNEL_PROTECT__ 1
160 #define __ARM_GLOBAL_SLEEP_BIT__ 1
161 #define __ARM_PAN_AVAILABLE__ 1
162 #define __ARM_WKDM_ISA_AVAILABLE__ 1
163 #define __PLATFORM_WKDM_ALIGNMENT_MASK__ (0x3FULL)
164 #define __PLATFORM_WKDM_ALIGNMENT_BOUNDARY__ (64)
165 #define __ARM_CLUSTER_COUNT__ 2
166
167 #elif defined (BCM2837)
168 #define __ARM_ARCH__ 8
169 #define __ARM_VMSA__ 8
170 #define __ARM_SMP__ 1
171 #define __ARM_VFP__ 4
172 #define __ARM_COHERENT_CACHE__ 1
173 #define __ARM_DEBUG__ 7
174 #define __ARM64_PMAP_SUBPAGE_L1__ 1
175 #else
176 #error processor not supported
177 #endif
178
179 #if __ARM_42BIT_PA_SPACE__
180 /* For now, force the issue! */
181 #undef __ARM64_PMAP_SUBPAGE_L1__
182 #endif /* __ARM_42BIT_PA_SPACE__ */
183
184 #if __ARM_KERNEL_PROTECT__
185 /*
186 * This feature is not currently implemented for 32-bit ARM CPU architectures.
187 * A discussion of this feature for 64-bit ARM CPU architectures can be found
188 * in the ARM64 version of this file.
189 */
190 #if __arm__
191 #error __ARM_KERNEL_PROTECT__ is not supported on ARM32
192 #endif /* __arm__ */
193 #endif /* __ARM_KERNEL_PROTECT__ */
194
195 #if defined(ARM_BOARD_WFE_TIMEOUT_NS)
196 #define __ARM_ENABLE_WFE_ 1
197 #else /* defined(ARM_BOARD_WFE_TIMEOUT_NS) */
198 #define __ARM_ENABLE_WFE_ 0
199 #endif /* defined(ARM_BOARD_WFE_TIMEOUT_NS) */
200
201 /*
202 * The clutch scheduler is enabled only on non-AMP platforms for now.
203 */
204 #if !__ARM_AMP__ && CONFIG_CLUTCH
205 #define CONFIG_SCHED_CLUTCH 1
206 #else /* !__ARM_AMP__ && CONFIG_CLUTCH */
207 #define CONFIG_SCHED_CLUTCH 0
208 #endif /* !__ARM_AMP__ && CONFIG_CLUTCH */
209
210 #if __ARM_AMP__ || CONFIG_SCHED_CLUTCH
211 #define CONFIG_THREAD_GROUPS 1
212 #else /* __ARM_AMP__ || CONFIG_SCHED_CLUTCH */
213 #define CONFIG_THREAD_GROUPS 0
214 #endif
215
216 #ifdef XNU_KERNEL_PRIVATE
217
218 #if __ARM_VFP__
219 #define ARM_VFP_DEBUG 0
220 #endif /* __ARM_VFP__ */
221
222 #endif /* XNU_KERNEL_PRIVATE */
223
224
225
226 /*
227 * FSR registers
228 *
229 * CPSR: Current Program Status Register
230 * SPSR: Saved Program Status Registers
231 *
232 * 31 30 29 28 27 24 19 16 9 8 7 6 5 4 0
233 * +-----------------------------------------------------------+
234 * | N| Z| C| V| Q|...| J|...|GE[3:0]|...| E| A| I| F| T| MODE |
235 * +-----------------------------------------------------------+
236 */
237
238 /*
239 * Flags
240 */
241 #define PSR_NF 0x80000000 /* Negative/Less than */
242 #define PSR_ZF 0x40000000 /* Zero */
243 #define PSR_CF 0x20000000 /* Carry/Borrow/Extend */
244 #define PSR_VF 0x10000000 /* Overflow */
245 #define PSR_QF 0x08000000 /* saturation flag (QADD ARMv5) */
246
247 /*
248 * Modified execution mode flags
249 */
250 #define PSR_JF 0x01000000 /* Jazelle flag (BXJ ARMv5) */
251 #define PSR_EF 0x00000200 /* mixed-endian flag (SETEND ARMv6) */
252 #define PSR_AF 0x00000100 /* precise abort flag (ARMv6) */
253 #define PSR_TF 0x00000020 /* thumb flag (BX ARMv4T) */
254 #define PSR_TFb 5 /* thumb flag (BX ARMv4T) */
255
256 /*
257 * Interrupts
258 */
259 #define PSR_IRQFb 7 /* IRQ : 0 = IRQ enable */
260 #define PSR_IRQF 0x00000080 /* IRQ : 0 = IRQ enable */
261 #define PSR_FIQF 0x00000040 /* FIQ : 0 = FIQ enable */
262
263 /*
264 * CPU mode
265 */
266 #define PSR_USER_MODE 0x00000010 /* User mode */
267 #define PSR_FIQ_MODE 0x00000011 /* FIQ mode */
268 #define PSR_IRQ_MODE 0x00000012 /* IRQ mode */
269 #define PSR_SVC_MODE 0x00000013 /* Supervisor mode */
270 #define PSR_ABT_MODE 0x00000017 /* Abort mode */
271 #define PSR_UND_MODE 0x0000001B /* Undefined mode */
272
273 #define PSR_MODE_MASK 0x0000001F
274 #define PSR_IS_KERNEL(psr) (((psr) & PSR_MODE_MASK) != PSR_USER_MODE)
275 #define PSR_IS_USER(psr) (((psr) & PSR_MODE_MASK) == PSR_USER_MODE)
276
277 #define PSR_USERDFLT PSR_USER_MODE
278 #define PSR_USER_MASK (PSR_AF | PSR_IRQF | PSR_FIQF | PSR_MODE_MASK)
279 #define PSR_USER_SET PSR_USER_MODE
280
281 #define PSR_INTMASK PSR_IRQF /* Interrupt disable */
282
283 /*
284 * FPEXC: Floating-Point Exception Register
285 */
286
287 #define FPEXC_EX 0x80000000 /* Exception status */
288 #define FPEXC_EX_BIT 31
289 #define FPEXC_EN 0x40000000 /* VFP : 1 = EN enable */
290 #define FPEXC_EN_BIT 30
291
292
293 /*
294 * FPSCR: Floating-point Status and Control Register
295 */
296
297 #define FPSCR_DN 0x02000000 /* Default NaN */
298 #define FPSCR_FZ 0x01000000 /* Flush to zero */
299
300 #define FPSCR_DEFAULT FPSCR_DN | FPSCR_FZ
301
302
303 /*
304 * FSR registers
305 *
306 * IFSR: Instruction Fault Status Register
307 * DFSR: Data Fault Status Register
308 */
309 #define FSR_ALIGN 0x00000001 /* Alignment */
310 #define FSR_DEBUG 0x00000002 /* Debug (watch/break) */
311 #define FSR_ICFAULT 0x00000004 /* Fault on instruction cache maintenance */
312 #define FSR_SFAULT 0x00000005 /* Translation Section */
313 #define FSR_PFAULT 0x00000007 /* Translation Page */
314 #define FSR_SACCESS 0x00000003 /* Section access */
315 #define FSR_PACCESS 0x00000006 /* Page Access */
316 #define FSR_SDOM 0x00000009 /* Domain Section */
317 #define FSR_PDOM 0x0000000B /* Domain Page */
318 #define FSR_SPERM 0x0000000D /* Permission Section */
319 #define FSR_PPERM 0x0000000F /* Permission Page */
320 #define FSR_EXT 0x00001000 /* External (Implementation Defined Classification) */
321
322 #define FSR_MASK 0x0000040F /* Valid bits */
323 #define FSR_ALIGN_MASK 0x0000040D /* Valid bits to check align */
324
325 #define DFSR_WRITE 0x00000800 /* write data abort fault */
326
327 #if defined (ARMA7) || defined (APPLE_ARM64_ARCH_FAMILY) || defined (BCM2837)
328
329 #define TEST_FSR_VMFAULT(status) \
330 (((status) == FSR_PFAULT) \
331 || ((status) == FSR_PPERM) \
332 || ((status) == FSR_SFAULT) \
333 || ((status) == FSR_SPERM) \
334 || ((status) == FSR_ICFAULT) \
335 || ((status) == FSR_SACCESS) \
336 || ((status) == FSR_PACCESS))
337
338 #define TEST_FSR_TRANSLATION_FAULT(status) \
339 (((status) == FSR_SFAULT) \
340 || ((status) == FSR_PFAULT))
341
342 #else
343
344 #error Incompatible CPU type configured
345
346 #endif
347
348 /*
349 * Cache configuration
350 */
351
352 #if defined (ARMA7)
353
354 /* I-Cache */
355 #define MMU_I_CLINE 5 /* cache line size as 1<<MMU_I_CLINE (32) */
356
357 /* D-Cache */
358 #define MMU_CSIZE 15 /* cache size as 1<<MMU_CSIZE (32K) */
359 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
360 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */
361 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
362 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
363
364 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
365 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
366
367 #define __ARM_L2CACHE__ 1
368
369 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<MMU_CSIZE */
370 #define L2_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
371 #define L2_NWAY 3 /* set associativity 1<<MMU_NWAY (8) */
372 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
373 #define L2_I7WAY 29 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
374 #define L2_I9WAY 29 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
375
376 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<MMU_SWAY */
377 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<MMU_NSET */
378
379 #elif defined (APPLETYPHOON)
380
381 /* I-Cache */
382 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
383
384 /* D-Cache */
385 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
386 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
387 #define MMU_NWAY 1 /* set associativity 1<<MMU_NWAY (2) */
388 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
389 #define MMU_I7WAY 31 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
390 #define MMU_I9WAY 31 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
391
392 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
393 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
394
395 #define __ARM_L2CACHE__ 1
396
397 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
398 #define L2_CLINE 6 /* cache line size as 1<<L2_CLINE (64) */
399 #define L2_NWAY 3 /* set associativity 1<<L2_NWAY (8) */
400 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
401 #define L2_I7WAY 29 /* cp15 c7 way incrementer 1<<L2_I7WAY */
402 #define L2_I9WAY 29 /* cp15 c9 way incrementer 1<<L2_I9WAY */
403
404 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
405 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
406
407 #elif defined (APPLETWISTER)
408
409 /* I-Cache */
410 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
411
412 /* D-Cache */
413 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
414 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
415 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */
416 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
417 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
418 #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
419
420 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
421 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
422
423 /* L2-Cache */
424 #define __ARM_L2CACHE__ 1
425
426 /*
427 * For reasons discussed in the platform expert code, we round the reported
428 * L2 size to 4MB, and adjust the other parameters accordingly.
429 */
430 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
431 #define L2_CLINE 6 /* cache line size as 1<<L2_CSIZE (64) */
432 #define L2_NWAY 4 /* set associativity as 1<<L2_CLINE (16, is actually 12) */
433 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
434 #define L2_I7WAY 28 /* cp15 c7 way incrementer 1<<L2_I7WAY */
435 #define L2_I9WAY 28 /* cp15 c9 way incremenber 1<<L2_I9WAY */
436
437 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
438 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
439
440 #elif defined (APPLEHURRICANE)
441
442 /* I-Cache */
443 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
444
445 /* D-Cache */
446 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
447 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
448 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */
449 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
450 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
451 #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
452
453 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
454 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
455
456 /* L2-Cache */
457 #define __ARM_L2CACHE__ 1
458
459 /*
460 * For reasons discussed in the platform expert code, we round the reported
461 * L2 size to 4MB, and adjust the other parameters accordingly.
462 */
463 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
464 #define L2_CLINE 6 /* cache line size as 1<<L2_CSIZE (64) */
465 #define L2_NWAY 4 /* set associativity as 1<<L2_CLINE (16, is actually 12) */
466 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
467 #define L2_I7WAY 28 /* cp15 c7 way incrementer 1<<L2_I7WAY */
468 #define L2_I9WAY 28 /* cp15 c9 way incremenber 1<<L2_I9WAY */
469
470 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
471 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
472
473 #elif defined (APPLEMONSOON)
474
475 /* I-Cache, 96KB for Monsoon, 48KB for Mistral, 6-way. */
476 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
477
478 /* D-Cache, 64KB for Monsoon, 32KB for Mistral, 4-way. */
479 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
480 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
481 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */
482 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
483 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
484 #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
485
486 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
487 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
488
489 /* L2-Cache */
490 #define __ARM_L2CACHE__ 1
491
492 /*
493 * LLC (Monsoon L2, Mistral L3): 8MB, 128-byte lines, 16-way.
494 * L2E (Mistral L2): 1MB, 64-byte lines, 8-way.
495 *
496 * TODO: Our L2 cahes have different line sizes. I begin to suspect
497 * this may be a problem.
498 */
499 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
500 #define L2_CLINE 7 /* cache line size as 1<<L2_CLINE (128) */
501 #define L2_NWAY 4 /* set associativity as 1<<L2_NWAY (16) */
502 #define L2_I7SET 6 /* TODO: cp15 c7 set incrementer 1<<L2_I7SET */
503 #define L2_I7WAY 28 /* TODO: cp15 c7 way incrementer 1<<L2_I7WAY */
504 #define L2_I9WAY 28 /* TODO: cp15 c9 way incremenber 1<<L2_I9WAY */
505
506 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
507 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
508
509 #elif defined (BCM2837) /* Raspberry Pi 3 */
510
511 /* I-Cache. We don't have detailed spec so we just follow the ARM technical reference. */
512 #define MMU_I_CLINE 6
513
514 /* D-Cache. */
515 #define MMU_CSIZE 15
516 #define MMU_CLINE 6
517 #define MMU_NWAY 2
518
519 #define MMU_I7SET 6
520 #define MMU_I7WAY 30
521 #define MMU_I9WAY 30
522
523 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY)
524 #define MMU_NSET (MMU_SWAY - MMU_CLINE)
525
526 #define __ARM_L2CACHE__ 1
527
528 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__
529 #define L2_CLINE 6
530 #define L2_NWAY 4
531 #define L2_I7SET 6
532 #define L2_I7WAY 28
533 #define L2_I9WAY 28
534 #define L2_SWAY (L2_CSIZE - L2_NWAY)
535 #define L2_NSET (L2_SWAY - L2_CLINE)
536
537 #else
538 #error processor not supported
539 #endif
540
541
542 #if (__ARM_VMSA__ <= 7)
543
544 /*
545 * SCTLR: System Control Register
546 */
547 /*
548 * System Control Register (SCTLR)
549 *
550 * 31 30 29 28 27 25 24 22 21 20 19 17 15 14 13 12 11 10 5 2 1 0
551 * +-+--+---+---+----+-+--+--+--+--+----+---+-+--+-+-+--+--+--+--+--+---+-+------+--+-+-+-+
552 * |0|TE|AFE|TRE|NMFI|0|EE|VE|11|FI|UWXN|WXN|1|HA|1|0|RR| V| I| Z|SW|000|1|C15BEN|11|C|A|M|
553 * +-+--+---+---+----+-+--+--+--+--+----+---+-+--+-+-+--+--+--+--+--+---+-+------+--+-+-+-+
554 *
555 * Where:
556 * TE: Thumb Exception enable
557 * AFE: Access flag enable
558 * TRE: TEX remap enable
559 * NMFI: Non-maskable FIQ (NMFI) support
560 * EE: Exception Endianness
561 * VE: Interrupt Vectors Enable
562 * FI: Fast interrupts configuration enable
563 * ITD: IT Disable
564 * UWXN: Unprivileged write permission implies PL1 XN
565 * WXN: Write permission implies XN
566 * HA: Hardware Access flag enable
567 * RR: Round Robin select
568 * V: High exception vectors
569 * I: Instruction cache enable
570 * Z: Branch prediction enable
571 * SW: SWP/SWPB enable
572 * C15BEN: CP15 barrier enable
573 * C: Cache enable
574 * A: Alignment check enable
575 * M: MMU enable
576 */
577
578 #define SCTLR_RESERVED 0x82DD8394
579
580 #define SCTLR_ENABLE 0x00000001 /* MMU enable */
581 #define SCTLR_ALIGN 0x00000002 /* Alignment check enable */
582 #define SCTLR_DCACHE 0x00000004 /* Data or Unified Cache enable */
583 #define SCTLR_BEN 0x00000040 /* CP15 barrier enable */
584 #define SCTLR_SW 0x00000400 /* SWP/SWPB Enable */
585 #define SCTLR_PREDIC 0x00000800 /* Branch prediction enable */
586 #define SCTLR_ICACHE 0x00001000 /* Instruction cache enabled. */
587 #define SCTLR_HIGHVEC 0x00002000 /* Vector table at 0xffff0000 */
588 #define SCTLR_RROBIN 0x00004000 /* Round Robin replacement */
589 #define SCTLR_HA 0x00020000 /* Hardware Access flag enable */
590 #define SCTLR_NMFI 0x08000000 /* Non-maskable FIQ */
591 #define SCTLR_TRE 0x10000000 /* TEX remap enable */
592 #define SCTLR_AFE 0x20000000 /* Access flag enable */
593 #define SCTLR_TE 0x40000000 /* Thumb Exception enable */
594
595 #define SCTLR_DEFAULT \
596 (SCTLR_AFE|SCTLR_TRE|SCTLR_HIGHVEC|SCTLR_ICACHE|SCTLR_PREDIC|SCTLR_DCACHE|SCTLR_ENABLE)
597
598
599 /*
600 * PRRR: Primary Region Remap Register
601 *
602 * 31 24 20 19 18 17 16 0
603 * +---------------------------------------------------------------+
604 * | NOSn | Res |NS1|NS0|DS1|DS0| TRn |
605 * +---------------------------------------------------------------+
606 */
607
608 #define PRRR_NS1 0x00080000
609 #define PRRR_NS0 0x00040000
610 #define PRRR_DS1 0x00020000
611 #define PRRR_DS0 0x00010000
612
613 #define PRRR_NOSn_ISH(region) (0x1<<((region)+24))
614
615 #if defined (ARMA7)
616 #define PRRR_SETUP (0x1F08022A)
617 #else
618 #error processor not supported
619 #endif
620
621 /*
622 * NMRR, Normal Memory Remap Register
623 *
624 * 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0
625 * +---------------------------------------------------------------+
626 * |OR7|OR6|OR5|OR4|OR3|OR2|OR1|OR0|IR7|IR6|IR5|IR4|IR3|IR2|IR1|IR0|
627 * +---------------------------------------------------------------+
628 */
629
630 #define NMRR_DISABLED 0x0 /* Non-cacheable */
631 #define NMRR_WRITEBACK 0x1 /* Write-Back, Write-Allocate */
632 #define NMRR_WRITETHRU 0x2 /* Write-Through, no Write-Allocate */
633 #define NMRR_WRITEBACKNO 0x3 /* Write-Back, no Write-Allocate */
634
635 #if defined (ARMA7)
636 #define NMRR_SETUP (0x01210121)
637 #else
638 #error processor not supported
639 #endif
640
641 /*
642 * TTBR: Translation Table Base Register
643 *
644 */
645
646 #define TTBR_IRGN_DISBALED 0x00000000 /* inner non-cacheable */
647 #define TTBR_IRGN_WRITEBACK 0x00000040 /* inner write back and allocate */
648 #define TTBR_IRGN_WRITETHRU 0x00000001 /* inner write thru */
649 #define TTBR_IRGN_WRITEBACKNO 0x00000041 /* inner write back no allocate */
650
651 #define TTBR_RGN_DISBALED 0x00000000 /* outer non-cacheable */
652 #define TTBR_RGN_WRITEBACK 0x00000008 /* outer write back and allocate */
653 #define TTBR_RGN_WRITETHRU 0x00000010 /* outer write thru outer cache */
654 #define TTBR_RGN_WRITEBACKNO 0x00000018 /* outer write back no allocate */
655
656 #define TTBR_SHARED 0x00000002 /* Shareable memory atribute */
657 #define TTBR_SHARED_NOTOUTER 0x00000020 /* Outer not shareable memory atribute */
658
659 #if defined (ARMA7)
660 #define TTBR_SETUP (TTBR_RGN_WRITEBACK|TTBR_IRGN_WRITEBACK|TTBR_SHARED)
661 #else
662 #error processor not supported
663 #endif
664
665 /*
666 * TTBCR: Translation Table Base Control register
667 *
668 * 31 3 2 0
669 * +----------+
670 * | zero | N |
671 * +----------+
672 *
673 * If N=0, always use translation table base register 0. Otherwise, if
674 * bits [31:32-N] of the address are all zero use base register 0. Otherwise,
675 * use base register 1.
676 *
677 * Reading from this register also returns the page table boundary for TTB0.
678 * Writing to it updates the boundary for TTB0. (0=16KB, 1=8KB, 2=4KB, etc...)
679 */
680
681 #define TTBCR_N_1GB_TTB0 0x2 /* 1 GB TTB0, 3GB TTB1 */
682 #define TTBCR_N_2GB_TTB0 0x1 /* 2 GB TTB0, 2GB TTB1 */
683 #define TTBCR_N_4GB_TTB0 0x0 /* 4 GB TTB0 */
684 #define TTBCR_N_MASK 0x3
685
686
687
688 /*
689 * ARM Page Granule
690 */
691 #define ARM_PGSHIFT 12
692 #define ARM_PGBYTES (1 << ARM_PGSHIFT)
693 #define ARM_PGMASK (ARM_PGBYTES-1)
694
695 /*
696 * DACR: Domain Access Control register
697 */
698
699 #define DAC_FAULT 0x0 /* invalid domain - everyone loses */
700 #define DAC_CLIENT 0x1 /* client domain - use AP bits */
701 #define DAC_RESERVE 0x2 /* reserved domain - undefined */
702 #define DAC_MANAGER 0x3 /* manager domain - all access */
703
704 #define DACR_SET(dom, x) ((x)<<((dom)<<1))
705
706
707 #define ARM_DOM_DEFAULT 0 /* domain that forces AP use */
708 #define ARM_DAC_SETUP 0x1
709
710 /*
711 * ARM 2-level Page Table support
712 */
713
714 /*
715 * Memory Attribute Index
716 */
717 #define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled */
718 #define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes */
719 #define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled */
720 #define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer */
721 #define CACHE_ATTRINDX_INNERWRITEBACK 0x4 /* inner cache enabled, buffer enabled, write allocate */
722 #define CACHE_ATTRINDX_POSTED CACHE_ATTRINDX_DISABLE
723 #define CACHE_ATTRINDX_POSTED_REORDERED CACHE_ATTRINDX_DISABLE
724 #define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED CACHE_ATTRINDX_DISABLE
725 #define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK
726
727
728 /*
729 * Access protection bit values
730 */
731 #define AP_RWNA 0x0 /* priv=read-write, user=no-access */
732 #define AP_RWRW 0x1 /* priv=read-write, user=read-write */
733 #define AP_RONA 0x2 /* priv=read-only , user=no-access */
734 #define AP_RORO 0x3 /* priv=read-only , user=read-only */
735
736 /*
737 * L1 Translation table
738 *
739 * Each translation table is up to 16KB
740 * 4096 32-bit entries of 1MB of address space.
741 */
742
743 #define ARM_TT_L1_SIZE 0x00100000 /* size of area covered by a tte */
744 #define ARM_TT_L1_OFFMASK 0x000FFFFF /* offset within an L1 entry */
745 #define ARM_TT_L1_TABLE_OFFMASK 0x000FFFFF /* offset within an L1 entry */
746 #define ARM_TT_L1_BLOCK_OFFMASK 0x000FFFFF /* offset within an L1 entry */
747 #define ARM_TT_L1_SUPER_OFFMASK 0x00FFFFFF /* offset within an L1 entry */
748 #define ARM_TT_L1_SHIFT 20 /* page descriptor shift */
749 #define ARM_TT_L1_INDEX_MASK 0xfff00000 /* mask for getting index in L1 table from virtual address */
750
751 #define ARM_TT_L1_PT_SIZE (4 * ARM_TT_L1_SIZE) /* 4 L1 table entries required to consume 1 L2 pagetable page */
752 #define ARM_TT_L1_PT_OFFMASK (ARM_TT_L1_PT_SIZE - 1)
753
754 /*
755 * L2 Translation table
756 *
757 * Each translation table is up to 1KB
758 * 4096 32-bit entries of 1MB (2^30) of address space.
759 */
760
761 #define ARM_TT_L2_SIZE 0x00001000 /* size of area covered by a tte */
762 #define ARM_TT_L2_OFFMASK 0x00000FFF /* offset within an L2 entry */
763 #define ARM_TT_L2_SHIFT 12 /* page descriptor shift */
764 #define ARM_TT_L2_INDEX_MASK 0x000ff000 /* mask for getting index in L2 table from virtual address */
765
766 /*
767 * Convenience definitions for:
768 * ARM_TT_LEAF: The last level of the configured page table format.
769 * ARM_TT_TWIG: The second to last level of the configured page table format.
770 * ARM_TT_ROOT: The first level of the configured page table format.
771 *
772 * My apologies to any botanists who may be reading this.
773 */
774 #define ARM_TT_LEAF_SIZE ARM_TT_L2_SIZE
775 #define ARM_TT_LEAF_OFFMASK ARM_TT_L2_OFFMASK
776 #define ARM_TT_LEAF_SHIFT ARM_TT_L2_SHIFT
777 #define ARM_TT_LEAF_INDEX_MASK ARM_TT_L2_INDEX_MASK
778
779 #define ARM_TT_TWIG_SIZE ARM_TT_L1_SIZE
780 #define ARM_TT_TWIG_OFFMASK ARM_TT_L1_OFFMASK
781 #define ARM_TT_TWIG_SHIFT ARM_TT_L1_SHIFT
782 #define ARM_TT_TWIG_INDEX_MASK ARM_TT_L1_INDEX_MASK
783
784 #define ARM_TT_ROOT_SIZE ARM_TT_L1_SIZE
785 #define ARM_TT_ROOT_OFFMASK ARM_TT_L1_OFFMASK
786 #define ARM_TT_ROOT_SHIFT ARM_TT_L1_SHIFT
787 #define ARM_TT_ROOT_INDEX_MASK ARM_TT_L1_INDEX_MASK
788
789 /*
790 * Level 1 Translation Table Entry
791 *
792 * page table entry
793 *
794 * 31 10 9 8 5 4 2 0
795 * +----------------------+-+----+--+--+--+
796 * | page table base addr | |dom |XN|00|01|
797 * +----------------------+-+----+--+--+--+
798 *
799 * direct (1MB) section entry
800 *
801 * 31 20 18 15 12 10 9 8 5 4 2 0
802 * +------------+--+-+-+-+---+--+-+----+--+--+--+
803 * | base addr |00|G|S|A|TEX|AP| |dom |XN|CB|10|
804 * +------------+--+-+-+-+---+--+-+----+--+--+--+
805 *
806 * super (16MB) section entry
807 *
808 * 31 24 23 18 15 12 10 9 8 5 4 2 0
809 * +---------+------+-+-+-+---+--+-+----+--+--+--+
810 * |base addr|000001|G|S|A|TEX|AP| |dom |XN|CB|10|
811 * +---------+------+-+-+-+---+--+-+----+--+--+--+
812 *
813 * where:
814 * 'G' is the notGlobal bit
815 * 'S' is the shared bit
816 * 'A' in the access permission extension (APX) bit
817 * 'TEX' remap register control bits
818 * 'AP' is the access protection
819 * 'dom' is the domain for the translation
820 * 'XN' is the eXecute Never bit
821 * 'CB' is the cache/buffer attribute
822 */
823
824 #define ARM_TTE_EMPTY 0x00000000 /* unasigned entry */
825
826 #define ARM_TTE_TYPE_FAULT 0x00000000 /* fault entry type */
827 #define ARM_TTE_TYPE_TABLE 0x00000001 /* page table type */
828 #define ARM_TTE_TYPE_BLOCK 0x00000002 /* section entry type */
829 #define ARM_TTE_TYPE_MASK 0x00000003 /* mask for extracting the type */
830
831 #define ARM_TTE_BLOCK_NGSHIFT 17
832 #define ARM_TTE_BLOCK_NG_MASK 0x00020000 /* mask to determine notGlobal bit */
833 #define ARM_TTE_BLOCK_NG 0x00020000 /* value for a per-process mapping */
834
835 #define ARM_TTE_BLOCK_SHSHIFT 16
836 #define ARM_TTE_BLOCK_SH_MASK 0x00010000 /* shared (SMP) mapping mask */
837 #define ARM_TTE_BLOCK_SH 0x00010000 /* shared (SMP) mapping */
838
839 #define ARM_TTE_BLOCK_CBSHIFT 2
840 #define ARM_TTE_BLOCK_CB(x) ((x) << ARM_TTE_BLOCK_CBSHIFT)
841 #define ARM_TTE_BLOCK_CB_MASK (3<< ARM_TTE_BLOCK_CBSHIFT)
842
843 #define ARM_TTE_BLOCK_AP0SHIFT 10
844 #define ARM_TTE_BLOCK_AP0 (1<<ARM_TTE_BLOCK_AP0SHIFT)
845 #define ARM_TTE_BLOCK_AP0_MASK (1<<ARM_TTE_BLOCK_AP0SHIFT)
846
847 #define ARM_TTE_BLOCK_AP1SHIFT 11
848 #define ARM_TTE_BLOCK_AP1 (1<<ARM_TTE_BLOCK_AP1SHIFT)
849 #define ARM_TTE_BLOCK_AP1_MASK (1<<ARM_TTE_BLOCK_AP1SHIFT)
850
851 #define ARM_TTE_BLOCK_AP2SHIFT 15
852 #define ARM_TTE_BLOCK_AP2 (1<<ARM_TTE_BLOCK_AP2SHIFT)
853 #define ARM_TTE_BLOCK_AP2_MASK (1<<ARM_TTE_BLOCK_AP2SHIFT)
854
855 /* access protections */
856 #define ARM_TTE_BLOCK_AP(ap) \
857 ((((ap)&0x1)<<ARM_TTE_BLOCK_AP1SHIFT) | \
858 ((((ap)>>1)&0x1)<<ARM_TTE_BLOCK_AP2SHIFT))
859
860 /* mask access protections */
861 #define ARM_TTE_BLOCK_APMASK \
862 (ARM_TTE_BLOCK_AP1_MASK | ARM_TTE_BLOCK_AP2_MASK)
863
864 #define ARM_TTE_BLOCK_AF ARM_TTE_BLOCK_AP0 /* value for access */
865 #define ARM_TTE_BLOCK_AFMASK ARM_TTE_BLOCK_AP0_MASK /* access mask */
866
867 #define ARM_TTE_TABLE_MASK 0xFFFFFC00 /* mask for a L2 page table entry */
868 #define ARM_TTE_TABLE_SHIFT 10 /* shift for L2 page table phys address */
869
870 #define ARM_TTE_BLOCK_L1_MASK 0xFFF00000 /* mask to extract phys address from L1 section entry */
871 #define ARM_TTE_BLOCK_L1_SHIFT 20 /* shift for 1MB section phys address */
872
873 #define ARM_TTE_SUPER_L1_MASK 0xFF000000 /* mask to extract phys address from L1 super entry */
874 #define ARM_TTE_SUPER_L1_SHIFT 24 /* shift for 16MB section phys address */
875
876 #define ARM_TTE_BLOCK_SUPER 0x00040000 /* make section a 16MB section */
877 #define ARM_TTE_BLOCK_SUPER_MASK 0x00F40000 /* make section a 16MB section */
878
879 #define ARM_TTE_BLOCK_NXSHIFT 4
880 #define ARM_TTE_BLOCK_NX 0x00000010 /* section is no execute */
881 #define ARM_TTE_BLOCK_NX_MASK 0x00000010 /* mask for extracting no execute bit */
882 #define ARM_TTE_BLOCK_PNX ARM_TTE_BLOCK_NX
883
884 #define ARM_TTE_BLOCK_TEX0SHIFT 12
885 #define ARM_TTE_BLOCK_TEX0 (1<<ARM_TTE_BLOCK_TEX0SHIFT)
886 #define ARM_TTE_BLOCK_TEX0_MASK (1<<ARM_TTE_BLOCK_TEX0SHIFT)
887
888 #define ARM_TTE_BLOCK_TEX1SHIFT 13
889 #define ARM_TTE_BLOCK_TEX1 (1<<ARM_TTE_BLOCK_TEX1SHIFT)
890 #define ARM_TTE_BLOCK_TEX1_MASK (1<<ARM_TTE_BLOCK_TEX1SHIFT)
891
892 #define ARM_TTE_BLOCK_TEX2SHIFT 14
893 #define ARM_TTE_BLOCK_TEX2 (1<<ARM_TTE_BLOCK_TEX2SHIFT)
894 #define ARM_TTE_BLOCK_TEX2_MASK (1<<ARM_TTE_BLOCK_TEX2SHIFT)
895
896
897 /* mask memory attributes index */
898 #define ARM_TTE_BLOCK_ATTRINDX(i) \
899 ((((i)&0x3)<<ARM_TTE_BLOCK_CBSHIFT) | \
900 ((((i)>>2)&0x1)<<ARM_TTE_BLOCK_TEX0SHIFT))
901
902 /* mask memory attributes index */
903 #define ARM_TTE_BLOCK_ATTRINDXMASK \
904 (ARM_TTE_BLOCK_CB_MASK | ARM_TTE_BLOCK_TEX0_MASK)
905
906
907 /*
908 * Level 2 Page table entries
909 *
910 * The following page table entry types are possible:
911 *
912 * fault page entry
913 * 31 2 0
914 * +----------------------------------------+--+
915 * | ignored |00|
916 * +----------------------------------------+--+
917 *
918 * large (64KB) page entry
919 * 31 16 15 12 9 6 4 3 2 0
920 * +----------------+--+---+-+-+-+---+--+-+-+--+
921 * | base phys addr |XN|TEX|G|S|A|000|AP|C|B|01|
922 * +----------------+--+---+-+-+-+---+--+-+-+--+
923 *
924 * small (4KB) page entry
925 * 31 12 9 6 4 3 2 1 0
926 * +-----------------------+-+-+-+---+--+-+-+-+--+
927 * | base phys addr |G|S|A|TEX|AP|C|B|1|XN|
928 * +-----------------------+-+-+-+---+--+-+-+-+--+
929 *
930 * also where:
931 * 'XN' is the eXecute Never bit
932 * 'G' is the notGlobal (process-specific) bit
933 * 'S' is the shared bit
934 * 'A' in the access permission extension (ATX) bit
935 * 'TEX' remap register control bits
936 * 'AP' is the access protection
937 * 'dom' is the domain for the translation
938 * 'C' is the cache attribute
939 * 'B' is the write buffer attribute
940 */
941
942 /* markers for (invalid) PTE for a page sent to compressor */
943 #define ARM_PTE_COMPRESSED ARM_PTE_TEX1 /* compressed... */
944 #define ARM_PTE_COMPRESSED_ALT ARM_PTE_TEX2 /* ... and was "alt_acct" */
945 #define ARM_PTE_COMPRESSED_MASK (ARM_PTE_COMPRESSED | ARM_PTE_COMPRESSED_ALT)
946 #define ARM_PTE_IS_COMPRESSED(x, p) \
947 ((((x) & 0x3) == 0) && /* PTE is not valid... */ \
948 ((x) & ARM_PTE_COMPRESSED) && /* ...has "compressed" marker" */ \
949 ((!((x) & ~ARM_PTE_COMPRESSED_MASK)) || /* ...no other bits */ \
950 (panic("compressed PTE %p 0x%x has extra bits 0x%x: corrupted?", \
951 (p), (x), (x) & ~ARM_PTE_COMPRESSED_MASK), FALSE)))
952
953 #define PTE_SHIFT 2 /* shift width of a pte (sizeof(pte) == (1 << PTE_SHIFT)) */
954 #define PTE_PGENTRIES (1024 >> PTE_SHIFT) /* number of ptes per page */
955
956 #define ARM_PTE_EMPTY 0x00000000 /* unasigned - invalid entry */
957
958 #define ARM_PTE_TYPE_FAULT 0x00000000 /* fault entry type */
959 #define ARM_PTE_TYPE_VALID 0x00000002 /* valid L2 entry */
960 #define ARM_PTE_TYPE 0x00000002 /* small page entry type */
961 #define ARM_PTE_TYPE_MASK 0x00000002 /* mask to get pte type */
962
963 #define ARM_PTE_NG_MASK 0x00000800 /* mask to determine notGlobal bit */
964 #define ARM_PTE_NG 0x00000800 /* value for a per-process mapping */
965
966 #define ARM_PTE_SHSHIFT 10
967 #define ARM_PTE_SHMASK 0x00000400 /* shared (SMP) mapping mask */
968 #define ARM_PTE_SH 0x00000400 /* shared (SMP) mapping */
969
970 #define ARM_PTE_CBSHIFT 2
971 #define ARM_PTE_CB(x) ((x)<<ARM_PTE_CBSHIFT)
972 #define ARM_PTE_CB_MASK (0x3<<ARM_PTE_CBSHIFT)
973
974 #define ARM_PTE_AP0SHIFT 4
975 #define ARM_PTE_AP0 (1<<ARM_PTE_AP0SHIFT)
976 #define ARM_PTE_AP0_MASK (1<<ARM_PTE_AP0SHIFT)
977
978 #define ARM_PTE_AP1SHIFT 5
979 #define ARM_PTE_AP1 (1<<ARM_PTE_AP1SHIFT)
980 #define ARM_PTE_AP1_MASK (1<<ARM_PTE_AP1SHIFT)
981
982 #define ARM_PTE_AP2SHIFT 9
983 #define ARM_PTE_AP2 (1<<ARM_PTE_AP2SHIFT)
984 #define ARM_PTE_AP2_MASK (1<<ARM_PTE_AP2SHIFT)
985
986 /* access protections */
987 #define ARM_PTE_AP(ap) \
988 ((((ap)&0x1)<<ARM_PTE_AP1SHIFT) | \
989 ((((ap)>>1)&0x1)<<ARM_PTE_AP2SHIFT))
990
991 /* mask access protections */
992 #define ARM_PTE_APMASK \
993 (ARM_PTE_AP1_MASK | ARM_PTE_AP2_MASK)
994
995 #define ARM_PTE_AF ARM_PTE_AP0 /* value for access */
996 #define ARM_PTE_AFMASK ARM_PTE_AP0_MASK /* access mask */
997
998 #define ARM_PTE_PAGE_MASK 0xFFFFF000 /* mask for a small page */
999 #define ARM_PTE_PAGE_SHIFT 12 /* page shift for 4KB page */
1000
1001 #define ARM_PTE_NXSHIFT 0
1002 #define ARM_PTE_NX 0x00000001 /* small page no execute */
1003 #define ARM_PTE_NX_MASK (1<<ARM_PTE_NXSHIFT)
1004
1005 #define ARM_PTE_PNXSHIFT 0
1006 #define ARM_PTE_PNX 0x00000000 /* no privilege execute. not impl */
1007 #define ARM_PTE_PNX_MASK (0<<ARM_PTE_NXSHIFT)
1008
1009 #define ARM_PTE_TEX0SHIFT 6
1010 #define ARM_PTE_TEX0 (1<<ARM_PTE_TEX0SHIFT)
1011 #define ARM_PTE_TEX0_MASK (1<<ARM_PTE_TEX0SHIFT)
1012
1013 #define ARM_PTE_TEX1SHIFT 7
1014 #define ARM_PTE_TEX1 (1<<ARM_PTE_TEX1SHIFT)
1015 #define ARM_PTE_TEX1_MASK (1<<ARM_PTE_TEX1SHIFT)
1016
1017 #define ARM_PTE_WRITEABLESHIFT ARM_PTE_TEX1SHIFT
1018 #define ARM_PTE_WRITEABLE ARM_PTE_TEX1
1019 #define ARM_PTE_WRITEABLE_MASK ARM_PTE_TEX1_MASK
1020
1021 #define ARM_PTE_TEX2SHIFT 8
1022 #define ARM_PTE_TEX2 (1<<ARM_PTE_TEX2SHIFT)
1023 #define ARM_PTE_TEX2_MASK (1<<ARM_PTE_TEX2SHIFT)
1024
1025 #define ARM_PTE_WIREDSHIFT ARM_PTE_TEX2SHIFT
1026 #define ARM_PTE_WIRED ARM_PTE_TEX2
1027 #define ARM_PTE_WIRED_MASK ARM_PTE_TEX2_MASK
1028
1029 /* mask memory attributes index */
1030 #define ARM_PTE_ATTRINDX(indx) \
1031 ((((indx)&0x3)<<ARM_PTE_CBSHIFT) | \
1032 ((((indx)>>2)&0x1)<<ARM_PTE_TEX0SHIFT))
1033
1034 /* mask memory attributes index */
1035 #define ARM_PTE_ATTRINDXMASK \
1036 (ARM_PTE_CB_MASK | ARM_PTE_TEX0_MASK)
1037
1038 #define ARM_SMALL_PAGE_SIZE (4096) /* 4KB */
1039 #define ARM_LARGE_PAGE_SIZE (64*1024) /* 64KB */
1040 #define ARM_SECTION_SIZE (1024*1024) /* 1MB */
1041 #define ARM_SUPERSECTION_SIZE (16*1024*1024) /* 16MB */
1042
1043 #define TLBI_ADDR_SHIFT (12)
1044 #define TLBI_ADDR_SIZE (20)
1045 #define TLBI_ADDR_MASK (((1ULL << TLBI_ADDR_SIZE) - 1))
1046 #define TLBI_ASID_SHIFT (0)
1047 #define TLBI_ASID_SIZE (8)
1048 #define TLBI_ASID_MASK (((1ULL << TLBI_ASID_SIZE) - 1))
1049 #endif
1050
1051 /*
1052 * Format of the Debug Status and Control Register (DBGDSCR)
1053 */
1054 #define ARM_DBGDSCR_RXFULL (1 << 30)
1055 #define ARM_DBGDSCR_TXFULL (1 << 29)
1056 #define ARM_DBGDSCR_RXFULL_1 (1 << 27)
1057 #define ARM_DBGDSCR_TXFULL_1 (1 << 26)
1058 #define ARM_DBGDSCR_PIPEADV (1 << 25)
1059 #define ARM_DBGDSCR_INSTRCOMPL_1 (1 << 24)
1060 #define ARM_DBGDSCR_EXTDCCMODE_MASK (3 << 20)
1061 #define ARM_DBGDSCR_EXTDCCMODE_NONBLOCKING (0 << 20)
1062 #define ARM_DBGDSCR_EXTDCCMODE_STALL (1 << 20)
1063 #define ARM_DBGDSCR_EXTDCCMODE_FAST (1 << 20)
1064 #define ARM_DBGDSCR_ADADISCARD (1 << 19)
1065 #define ARM_DBGDSCR_NS (1 << 18)
1066 #define ARM_DBGDSCR_SPNIDDIS (1 << 17)
1067 #define ARM_DBGDSCR_SPIDDIS (1 << 16)
1068 #define ARM_DBGDSCR_MDBGEN (1 << 15)
1069 #define ARM_DBGDSCR_HDBGEN (1 << 14)
1070 #define ARM_DBGDSCR_ITREN (1 << 13)
1071 #define ARM_DBGDSCR_UDCCDIS (1 << 12)
1072 #define ARM_DBGDSCR_INTDIS (1 << 11)
1073 #define ARM_DBGDSCR_DBGACK (1 << 10)
1074 #define ARM_DBGDSCR_DBGNOPWRDWN (1 << 9)
1075 #define ARM_DBGDSCR_UND_1 (1 << 8)
1076 #define ARM_DBGDSCR_ADABORT_1 (1 << 7)
1077 #define ARM_DBGDSCR_SDABORT_1 (1 << 6)
1078 #define ARM_DBGDSCR_MOE_MASK (15 << 2)
1079 #define ARM_DBGDSCR_MOE_HALT_REQUEST (0 << 2)
1080 #define ARM_DBGDSCR_MOE_BREAKPOINT (1 << 2)
1081 #define ARM_DBGDSCR_MOE_ASYNC_WATCHPOINT (2 << 2)
1082 #define ARM_DBGDSCR_MOE_BKPT_INSTRUCTION (3 << 2)
1083 #define ARM_DBGDSCR_MOE_EXT_DEBUG_REQ (4 << 2)
1084 #define ARM_DBGDSCR_MOE_VECTOR_CATCH (5 << 2)
1085 #define ARM_DBGDSCR_MOE_DSIDE_ABORT (6 << 2)
1086 #define ARM_DBGDSCR_MOE_ISIDE_ABORT (7 << 2)
1087 #define ARM_DBGDSCR_MOE_OS_UNLOCK_CATCH (8 << 2)
1088 #define ARM_DBGDSCR_MOE_SYNC_WATCHPOINT (10 << 2)
1089
1090 #define ARM_DBGDSCR_RESTARTED (1 << 1)
1091 #define ARM_DBGDSCR_HALTED (1 << 0)
1092
1093 /*
1094 * Format of the Debug & Watchpoint Breakpoint Value and Control Registers
1095 * Using ARMv7 names; ARMv6 and ARMv6.1 are bit-compatible
1096 */
1097 #define ARM_DBG_VR_ADDRESS_MASK 0xFFFFFFFC /* BVR & WVR */
1098 #define ARM_DBGBVR_CONTEXTID_MASK 0xFFFFFFFF /* BVR only */
1099
1100 #define ARM_DBG_CR_ADDRESS_MASK_MASK 0x1F000000 /* BCR & WCR */
1101 #define ARM_DBGBCR_MATCH_MASK (1 << 22) /* BCR only */
1102 #define ARM_DBGBCR_MATCH_MATCH (0 << 22)
1103 #define ARM_DBGBCR_MATCH_MISMATCH (1 << 22)
1104 #define ARM_DBGBCR_TYPE_MASK (1 << 21) /* BCR only */
1105 #define ARM_DBGBCR_TYPE_IVA (0 << 21)
1106 #define ARM_DBGBCR_TYPE_CONTEXTID (1 << 21)
1107 #define ARM_DBG_CR_LINKED_MASK (1 << 20) /* BCR & WCR */
1108 #define ARM_DBG_CR_LINKED_LINKED (1 << 20)
1109 #define ARM_DBG_CR_LINKED_UNLINKED (0 << 20)
1110 #define ARM_DBG_CR_LINKED_BRP_MASK 0x000F0000 /* BCR & WCR */
1111 #define ARM_DBG_CR_SECURITY_STATE_MASK (3 << 14) /* BCR & WCR */
1112 #define ARM_DBG_CR_SECURITY_STATE_BOTH (0 << 14)
1113 #define ARM_DBG_CR_SECURITY_STATE_NONSECURE (1 << 14)
1114 #define ARM_DBG_CR_SECURITY_STATE_SECURE (2 << 14)
1115 #define ARM_DBG_CR_HIGHER_MODE_MASK (1 << 13) /* BCR & WCR */
1116 #define ARM_DBG_CR_HIGHER_MODE_ENABLE (1 << 13)
1117 #define ARM_DBG_CR_HIGHER_MODE_DISABLE (0 << 13)
1118 #define ARM_DBGWCR_BYTE_ADDRESS_SELECT_MASK 0x00001FE0 /* WCR only */
1119 #define ARM_DBG_CR_BYTE_ADDRESS_SELECT_MASK 0x000001E0 /* BCR & WCR */
1120 #define ARM_DBGWCR_ACCESS_CONTROL_MASK (3 << 3) /* WCR only */
1121 #define ARM_DBCWCR_ACCESS_CONTROL_LOAD (1 << 3)
1122 #define ARM_DBCWCR_ACCESS_CONTROL_STORE (2 << 3)
1123 #define ARM_DBCWCR_ACCESS_CONTROL_ANY (3 << 3)
1124 #define ARM_DBG_CR_MODE_CONTROL_MASK (3 << 1) /* BCR & WCR */
1125 #define ARM_DBG_CR_MODE_CONTROL_U_S_S (0 << 1) /* BCR only */
1126 #define ARM_DBG_CR_MODE_CONTROL_PRIVILEGED (1 << 1) /* BCR & WCR */
1127 #define ARM_DBG_CR_MODE_CONTROL_USER (2 << 1) /* BCR & WCR */
1128 #define ARM_DBG_CR_MODE_CONTROL_ANY (3 << 1) /* BCR & WCR */
1129 #define ARM_DBG_CR_ENABLE_MASK (1 << 0) /* BCR & WCR */
1130 #define ARM_DBG_CR_ENABLE_ENABLE (1 << 0)
1131 #define ARM_DBG_CR_ENABLE_DISABLE (0 << 0)
1132
1133 /*
1134 * Format of the Device Power-down and Reset Status Register (DBGPRSR)
1135 */
1136 #define ARM_DBGPRSR_STICKY_RESET_STATUS (1 << 3)
1137 #define ARM_DBGPRSR_RESET_STATUS (1 << 2)
1138 #define ARM_DBGPRSR_STICKY_POWERDOWN_STATUS (1 << 1)
1139 #define ARM_DBGPRSR_POWERUP_STATUS (1 << 0)
1140
1141 /*
1142 * Format of the OS Lock Access (DBGOSLAR) and Lock Access Registers (DBGLAR)
1143 */
1144 #define ARM_DBG_LOCK_ACCESS_KEY 0xC5ACCE55
1145
1146 /* ARMv7 Debug register map */
1147 #define ARM_DEBUG_OFFSET_DBGDIDR (0x000)
1148 #define ARM_DEBUG_OFFSET_DBGWFAR (0x018)
1149 #define ARM_DEBUG_OFFSET_DBGVCR (0x01C)
1150 #define ARM_DEBUG_OFFSET_DBGECR (0x024)
1151 #define ARM_DEBUG_OFFSET_DBGDSCCR (0x028)
1152 #define ARM_DEBUG_OFFSET_DBGDSMCR (0x02C)
1153 #define ARM_DEBUG_OFFSET_DBGDTRRX (0x080)
1154 #define ARM_DEBUG_OFFSET_DBGITR (0x084) /* Write-only */
1155 #define ARM_DEBUG_OFFSET_DBGPCSR (0x084) /* Read-only */
1156 #define ARM_DEBUG_OFFSET_DBGDSCR (0x088)
1157 #define ARM_DEBUG_OFFSET_DBGDTRTX (0x08C)
1158 #define ARM_DEBUG_OFFSET_DBGDRCR (0x090)
1159 #define ARM_DEBUG_OFFSET_DBGBVR (0x100) /* 0x100 - 0x13C */
1160 #define ARM_DEBUG_OFFSET_DBGBCR (0x140) /* 0x140 - 0x17C */
1161 #define ARM_DEBUG_OFFSET_DBGWVR (0x180) /* 0x180 - 0x1BC */
1162 #define ARM_DEBUG_OFFSET_DBGWCR (0x1C0) /* 0x1C0 - 0x1FC */
1163 #define ARM_DEBUG_OFFSET_DBGOSLAR (0x300)
1164 #define ARM_DEBUG_OFFSET_DBGOSLSR (0x304)
1165 #define ARM_DEBUG_OFFSET_DBGOSSRR (0x308)
1166 #define ARM_DEBUG_OFFSET_DBGPRCR (0x310)
1167 #define ARM_DEBUG_OFFSET_DBGPRSR (0x314)
1168 #define ARM_DEBUG_OFFSET_DBGITCTRL (0xF00)
1169 #define ARM_DEBUG_OFFSET_DBGCLAIMSET (0xFA0)
1170 #define ARM_DEBUG_OFFSET_DBGCLAIMCLR (0xFA4)
1171 #define ARM_DEBUG_OFFSET_DBGLAR (0xFB0)
1172 #define ARM_DEBUG_OFFSET_DBGLSR (0xFB4)
1173 #define ARM_DEBUG_OFFSET_DBGAUTHSTATUS (0xFB8)
1174 #define ARM_DEBUG_OFFSET_DBGDEVID (0xFC8)
1175 #define ARM_DEBUG_OFFSET_DBGDEVTYPE (0xFCC)
1176 #define ARM_DEBUG_OFFSET_DBGPID0 (0xFD0)
1177 #define ARM_DEBUG_OFFSET_DBGPID1 (0xFD4)
1178 #define ARM_DEBUG_OFFSET_DBGPID2 (0xFD8)
1179 #define ARM_DEBUG_OFFSET_DBGPID3 (0xFDA)
1180 #define ARM_DEBUG_OFFSET_DBGPID4 (0xFDC)
1181 #define ARM_DEBUG_OFFSET_DBGCID0 (0xFF0)
1182 #define ARM_DEBUG_OFFSET_DBGCID1 (0xFF4)
1183 #define ARM_DEBUG_OFFSET_DBGCID2 (0xFF8)
1184 #define ARM_DEBUG_OFFSET_DBGCID3 (0xFFA)
1185 #define ARM_DEBUG_OFFSET_DBGCID4 (0xFFC)
1186
1187 /*
1188 * Media and VFP Feature Register 1 (MVFR1)
1189 */
1190 #define MVFR_ASIMD_HPFP 0x00100000UL
1191
1192 /*
1193 * Main ID Register (MIDR)
1194 *
1195 * 31 24 23 20 19 16 15 4 3 0
1196 * +-----+-----+------+------+-----+
1197 * | IMP | VAR | ARCH | PNUM | REV |
1198 * +-----+-----+------+------+-----+
1199 *
1200 * where:
1201 * IMP: Implementor code
1202 * VAR: Variant number
1203 * ARCH: Architecture code
1204 * PNUM: Primary part number
1205 * REV: Minor revision number
1206 */
1207 #define MIDR_REV_SHIFT 0
1208 #define MIDR_REV_MASK (0xf << MIDR_REV_SHIFT)
1209 #define MIDR_PNUM_SHIFT 4
1210 #define MIDR_PNUM_MASK (0xfff << MIDR_PNUM_SHIFT)
1211 #define MIDR_ARCH_SHIFT 16
1212 #define MIDR_ARCH_MASK (0xf << MIDR_ARCH_SHIFT)
1213 #define MIDR_VAR_SHIFT 20
1214 #define MIDR_VAR_MASK (0xf << MIDR_VAR_SHIFT)
1215 #define MIDR_IMP_SHIFT 24
1216 #define MIDR_IMP_MASK (0xff << MIDR_IMP_SHIFT)
1217
1218 #ifdef __arm__
1219
1220 /* Macros meant to make __builtin_arm_* functions easier to use. */
1221 #define MRC_SCTLR 15,0,1,0,0
1222 #define MCR_SCTLR(x) 15,0,(x),1,0,0
1223
1224 #define MRC_ACTLR 15,0,1,0,1
1225 #define MCR_ACTLR(x) 15,0,(x),1,0,1
1226
1227 #endif /* __arm__ */
1228
1229 #endif /* _ARM_PROC_REG_H_ */
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