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1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22 /*
23 * @OSF_COPYRIGHT@
24 */
25 /*
26 * Mach Operating System
27 * Copyright (c) 1991 Carnegie Mellon University
28 * All Rights Reserved.
29 *
30 * Permission to use, copy, modify and distribute this software and its
31 * documentation is hereby granted, provided that both the copyright
32 * notice and this permission notice appear in all copies of the
33 * software, derivative works or modified versions, and any portions
34 * thereof, and that both notices appear in supporting documentation.
35 *
36 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
37 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
38 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
39 *
40 * Carnegie Mellon requests users of this software to return to
41 *
42 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
43 * School of Computer Science
44 * Carnegie Mellon University
45 * Pittsburgh PA 15213-3890
46 *
47 * any improvements or extensions that they make and grant Carnegie Mellon
48 * the rights to redistribute these changes.
49 */
50
51 /*
52 */
53
54 #ifndef _I386_FPU_H_
55 #define _I386_FPU_H_
56
57 /*
58 * Macro definitions for routines to manipulate the
59 * floating-point processor.
60 */
61
62 #include <i386/proc_reg.h>
63 #include <i386/thread.h>
64 #include <kern/kern_types.h>
65 #include <mach/i386/kern_return.h>
66 #include <mach/i386/thread_status.h>
67
68 /*
69 * FPU instructions.
70 */
71 #define fninit() \
72 __asm__ volatile("fninit")
73
74 #define fnstcw(control) \
75 __asm__("fnstcw %0" : "=m" (*(unsigned short *)(control)))
76
77 #define fldcw(control) \
78 __asm__ volatile("fldcw %0" : : "m" (*(unsigned short *) &(control)) )
79
80 extern unsigned short fnstsw(void);
81
82 extern __inline__ unsigned short fnstsw(void)
83 {
84 unsigned short status;
85 __asm__ volatile("fnstsw %0" : "=ma" (status));
86 return(status);
87 }
88
89 #define fnclex() \
90 __asm__ volatile("fnclex")
91
92 #define fnsave(state) \
93 __asm__ volatile("fnsave %0" : "=m" (*state))
94
95 #define frstor(state) \
96 __asm__ volatile("frstor %0" : : "m" (state))
97
98 #define fwait() \
99 __asm__("fwait");
100
101 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
102 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
103
104 #define FXSAFE() (fp_kind == FP_FXSR)
105
106 #define fpu_load_context(pcb)
107
108 /*
109 * Save thread`s FPU context.
110 * If only one CPU, we just set the task-switched bit,
111 * to keep the new thread from using the coprocessor.
112 * If multiple CPUs, we save the entire state.
113 * NOTE: in order to provide backwards compatible support in the kernel. When saving SSE2 state, we also save the
114 * FP state in it's old location. Otherwise fpu_get_state() and fpu_set_state() will stop working
115 */
116 #define fpu_save_context(thread) \
117 { \
118 register struct i386_fpsave_state *ifps; \
119 ifps = (thread)->machine.pcb->ims.ifps; \
120 if (ifps != 0 && !ifps->fp_valid) { \
121 /* registers are in FPU - save to memory */ \
122 ifps->fp_valid = TRUE; \
123 ifps->fp_save_flavor = FP_387; \
124 if (FXSAFE()) { \
125 fxsave(&ifps->fx_save_state); \
126 ifps->fp_save_flavor = FP_FXSR; \
127 } \
128 fnsave(&ifps->fp_save_state); \
129 } \
130 set_ts(); \
131 }
132
133
134
135 extern int fp_kind;
136
137 extern void init_fpu(void);
138 extern void fpu_module_init(void);
139 extern void fpu_free(
140 struct i386_fpsave_state * fps);
141 extern kern_return_t fpu_set_state(
142 thread_t thr_act,
143 struct i386_float_state * st);
144 extern kern_return_t fpu_get_state(
145 thread_t thr_act,
146 struct i386_float_state * st);
147 extern kern_return_t fpu_set_fxstate(
148 thread_t thr_act,
149 struct i386_float_state * st);
150 extern kern_return_t fpu_get_fxstate(
151 thread_t thr_act,
152 struct i386_float_state * st);
153 extern void fpnoextflt(void);
154 extern void fpextovrflt(void);
155 extern void fpexterrflt(void);
156 extern void fp_state_alloc(void);
157 extern void fpintr(void);
158 extern void fpflush(thread_t);
159
160 #endif /* _I386_FPU_H_ */