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1 /*
2 * Copyright (c) 2000-2004 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31
32 #define __APPLE_API_PRIVATE
33
34 #include <mach_kdb.h>
35 #include <mach_kdp.h>
36 #include <mach_kgdb.h>
37 #include <ppc/asm.h>
38 #include <ppc/proc_reg.h>
39 #include <ppc/spec_reg.h>
40 #include <machine/cpu_capabilities.h>
41 #include <mach/ppc/vm_param.h>
42 #include <assym.s>
43
44
45 ; Definitions of the processor type table format, which drives this code.
46 ; The table ("processor_types") is assembled in at the end of this file.
47
48 #define ptFilter 0
49 #define ptVersion 4
50 #define ptRevision 6
51 #define ptFeatures 8
52 #define ptCPUCap 12
53 #define ptPwrModes 16
54 #define ptPatch 20
55 #define ptInitRout 24
56 #define ptRptdProc 28
57 #define ptLineSize 32
58 #define ptl1iSize 36
59 #define ptl1dSize 40
60 #define ptPTEG 44
61 #define ptMaxVAddr 48
62 #define ptMaxPAddr 52
63 #define ptSize 56
64
65
66 ; We use cr2 for flags:
67
68 #define bootCPU 10
69 #define firstInit 9
70 #define firstBoot 8
71
72 /*
73 * Interrupt and bootup stack for initial processor
74 */
75
76 .file "start.s"
77
78 /*
79 * All CPUs start here.
80 *
81 * This code is called from SecondaryLoader
82 *
83 * Various arguments are passed via a table:
84 * R3 = pointer to other startup parameters
85 */
86 .text
87
88 ENTRY(resetPOR,TAG_NO_FRAME_USED)
89
90 li r12,0 ; Get a 0
91 stw r12,0xF0(0) ; Make sure the special flag is clear
92 mtmsrd r12 ; Make sure we are in 32-bit mode
93 isync ; Really make sure
94 lwz r3,0xF4(0) ; Get the boot_args pointer
95 b startJoin ; Join up...
96
97
98 ENTRY(_start_cpu,TAG_NO_FRAME_USED)
99 crclr bootCPU ; Set non-boot processor
100 crclr firstInit ; Set not first time init
101 lwz r30,ppe_paddr(r3) ; Set current per_proc
102 lwz r28,ppe_paddr+4(r3) ; Set current per_proc
103 rlwinm r30,r30,0,1,0 ; Copy low 32 bits to top 32
104 rlwimi r30,r28,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
105 subi r29,r3,(ACT_PER_PROC-ppe_vaddr) ; Substract mact.PerProc offset
106 mr r3,r30 ; Set current per_proc
107
108 ;
109 ; Note that we are just trying to get close. The real TB sync will take
110 ; place later. The value we are loading is set in two places. For the
111 ; main processor, it will be the TB at the last interrupt before we went
112 ; to sleep. For the others, it will be the time just before the main
113 ; processor woke us up.
114 ;
115
116 lwz r15,ruptStamp(r3) ; Get the timebase from the other processor
117 li r17,0 ; Clear this out
118 lwz r16,ruptStamp+4(r3) ; Get the timebase from the other processor
119 mtspr tbl,r17 ; Clear bottom so we do not tick
120 mtspr tbu,r15 ; Set top
121 mtspr tbl,r16 ; Then bottom again
122 b allstart
123
124 ENTRY(_start,TAG_NO_FRAME_USED)
125
126 startJoin:
127 mflr r2 ; Save the return address
128 lis r28,hi16(EXT(PerProcTable)) ; Set PerProcTable
129 lis r30,hi16(EXT(BootProcInfo)) ; Set current per_proc
130 ori r28,r28,lo16(EXT(PerProcTable)) ; Set PerProcTable
131 ori r30,r30,lo16(EXT(BootProcInfo)) ; Set current per_proc
132 stw r30,ppe_paddr+4(r28) ; Set per_proc_entry
133 stw r30,ppe_vaddr(r28) ; Set per_proc_entry
134 subi r29,r28,(ACT_PER_PROC-ppe_vaddr) ; Substract mact.PerProc offset
135 crset bootCPU ; Set boot processor
136
137 lwz r17,pfAvailable(r30) ; Get the available bits
138 rlwinm. r0,r17,0,pfValidb,pfValidb ; Have we initialized the feature flags yet?
139 crmove firstInit,cr0_eq ; Set if we are doing first time init
140 bne allstart ; Yeah, we must be waking up from sleep...
141
142 ;
143 ; Here is where we do any one time general low-level initialization
144
145 lis r20,HIGH_ADDR(fwdisplock) ; Get address of the firmware display lock
146 li r19,0 ; Zorch a register
147 ori r20,r20,LOW_ADDR(fwdisplock) ; Get address of the firmware display lock
148 stw r19,0(r20) ; Make sure the lock is free
149
150 allstart:
151 mr r31,r3 ; Save away arguments
152
153 crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
154
155 mtsprg 0,r30 ; Set per_proc paddr
156 mtsprg 1,r29 ; Set spr1
157
158 li r9,0 ; Clear out a register
159 mtsprg 2,r9
160 mtsprg 3,r9
161
162 li r7,MSR_VM_OFF ; Get real mode MSR
163 mtmsr r7 ; Set the real mode SRR
164 isync
165
166 lis r26,hi16(processor_types) ; Point to processor table
167 ori r26,r26,lo16(processor_types) ; Other half
168 mfpvr r10 ; Get the PVR
169
170 nextPVR: lwz r28,ptFilter(r26) ; Get the filter
171 lwz r27,ptVersion(r26) ; Get the version and revision codes
172 and r28,r10,r28 ; Throw away dont care bits
173 cmplw r27,r28 ; Is this the right set?
174 beq donePVR ; We have the right one...
175 addi r26,r26,ptSize ; Point to the next type
176 b nextPVR ; Check it out...
177
178 donePVR: lwz r20,ptInitRout(r26) ; Grab the special init routine
179 mtlr r20 ; Setup to call the init
180
181 bf firstBoot,notFirst ; Not first boot, go...
182
183 ;
184 ; The following code just does a general initialization of the features just
185 ; after the initial first-time boot. This is not done after waking up or on
186 ; any "secondary" processor. Just after the boot-processor init, we copy the
187 ; features to any possible per_proc.
188 ;
189 ; We are just setting defaults. The specific initialization code will modify these
190 ; if necessary.
191 ;
192 lis r18,hi16(EXT(_cpu_capabilities)) ; Get the address of _cpu_capabilities
193 ori r18,r18,lo16(EXT(_cpu_capabilities))
194 lwz r17,ptCPUCap(r26) ; Get the default cpu capabilities
195 stw r17, 0(r18) ; Save the default value in _cpu_capabilities
196
197 lwz r17,ptFeatures(r26) ; Pick up the features
198
199 lwz r18,ptRptdProc(r26) ; Get the reported processor
200 sth r18,pfrptdProc(r30) ; Set the reported processor
201
202 lwz r13,ptPwrModes(r26) ; Get the supported power modes
203 stw r13,pfPowerModes(r30) ; Set the supported power modes
204
205 lwz r13,ptLineSize(r26) ; Get the cache line size
206 sth r13,pflineSize(r30) ; Save it
207 lwz r13,ptl1iSize(r26) ; Get icache size
208 stw r13,pfl1iSize(r30) ; Save it
209 lwz r13,ptl1dSize(r26) ; Get dcache size
210 stw r13,pfl1dSize(r30) ; Save it
211 lwz r13,ptPTEG(r26) ; Get PTEG size address
212 stw r13,pfPTEG(r30) ; Save it
213 lwz r13,ptMaxVAddr(r26) ; Get max virtual address
214 stw r13,pfMaxVAddr(r30) ; Save it
215 lwz r13,ptMaxPAddr(r26) ; Get max physical address
216 stw r13,pfMaxPAddr(r30) ; Save it
217
218
219 ; Go through the patch table, changing performance sensitive kernel routines based on the
220 ; processor type or other things.
221
222 lis r11,hi16(EXT(patch_table))
223 ori r11,r11,lo16(EXT(patch_table))
224 lwz r19,ptPatch(r26) ; Get ptPatch field
225 patch_loop:
226 lwz r16,patchType(r11) ; Load the patch type
227 lwz r15,patchValue(r11) ; Load the patch value
228 cmplwi cr1,r16,PATCH_FEATURE ; Is it a patch feature entry
229 cmplwi cr7,r16,PATCH_END_OF_TABLE ; end of table?
230 and. r14,r15,r19 ; Is it set in the patch feature
231 crandc cr0_eq,cr1_eq,cr0_eq ; Do we have a match
232 beq cr7,doOurInit ; end of table, Go do processor specific initialization
233 beq patch_apply ; proc feature matches, so patch memory
234 cmplwi cr1,r16,PATCH_PROCESSOR ; Is it a patch processor entry
235 cmplw cr0,r15,r18 ; Check matching processor
236 crand cr0_eq,cr1_eq,cr0_eq ; Do we have a match
237 bne patch_skip ; No, skip patch memory
238 patch_apply:
239 lwz r13,patchAddr(r11) ; Load the address to patch
240 lwz r14,patchData(r11) ; Load the patch data
241 stw r14,0(r13) ; Patch the location
242 dcbf 0,r13 ; Flush the old one
243 sync ; Make sure we see it all
244 icbi 0,r13 ; Flush the i-cache
245 isync ; Hang out
246 sync ; Hang out some more...
247 patch_skip:
248 addi r11,r11,peSize ; Point to the next patch entry
249 b patch_loop ; handle next
250
251
252 ; Additional processors join here after skipping above code.
253
254 notFirst: lwz r17,pfAvailable(r30) ; Get our features
255
256 doOurInit: mr. r20,r20 ; See if initialization routine
257 crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
258 bnelrl ; Do the initialization
259
260 ori r17,r17,lo16(pfValid) ; Set the valid bit
261 stw r17,pfAvailable(r30) ; Set the available features
262
263 rlwinm. r0,r17,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
264 mtsprg 2,r17 ; Remember the feature flags
265
266 bne++ start64 ; Skip following if 64-bit...
267
268 mfspr r6,hid0 ; Get the HID0
269 rlwinm r6,r6,0,sleep+1,doze-1 ; Remove any vestiges of sleep
270 mtspr hid0,r6 ; Set the insominac HID0
271 isync
272
273 ; Clear the BAT registers
274
275 li r9,0 ; Clear out a register
276 sync
277 isync
278 mtdbatu 0,r9 ; Invalidate maps
279 mtdbatl 0,r9 ; Invalidate maps
280 mtdbatu 1,r9 ; Invalidate maps
281 mtdbatl 1,r9 ; Invalidate maps
282 mtdbatu 2,r9 ; Invalidate maps
283 mtdbatl 2,r9 ; Invalidate maps
284 mtdbatu 3,r9 ; Invalidate maps
285 mtdbatl 3,r9 ; Invalidate maps
286 sync
287 isync
288 mtibatu 0,r9 ; Invalidate maps
289 mtibatl 0,r9 ; Invalidate maps
290 mtibatu 1,r9 ; Invalidate maps
291 mtibatl 1,r9 ; Invalidate maps
292 mtibatu 2,r9 ; Invalidate maps
293 mtibatl 2,r9 ; Invalidate maps
294 mtibatu 3,r9 ; Invalidate maps
295 mtibatl 3,r9 ; Invalidate maps
296 sync
297 isync
298 b startcommon ; Go join up the common start routine
299
300 start64: lis r5,hi16(startcommon) ; Get top of address of continue point
301 mfspr r6,hid0 ; Get the HID0
302 ori r5,r5,lo16(startcommon) ; Get low of address of continue point
303 lis r9,hi16(MASK(MSR_HV)|MASK(MSR_SF)) ; ?
304 lis r20,hi16(dozem|napm|sleepm) ; Get mask of power saving features
305 li r7,MSR_VM_OFF ; Get real mode MSR
306 sldi r9,r9,32 ; Slide into position
307 sldi r20,r20,32 ; Slide power stuff into position
308 or r9,r9,r7 ; Form initial MSR
309 andc r6,r6,r20 ; Remove any vestiges of sleep
310 isync
311 mtspr hid0,r6 ; Set the insominac HID0
312 mfspr r6,hid0 ; Get it
313 mfspr r6,hid0 ; Get it
314 mfspr r6,hid0 ; Get it
315 mfspr r6,hid0 ; Get it
316 mfspr r6,hid0 ; Get it
317 mfspr r6,hid0 ; Get it
318 isync
319 mtsrr0 r5 ; Set the continue point
320 mtsrr1 r9 ; Set our normal disabled MSR
321 rfid ; Tally ho...
322
323 .align 5
324
325 startcommon:
326 rlwinm. r0,r17,0,pfFloatb,pfFloatb ; See if there is floating point
327 beq- noFloat ; Nope, this is a really stupid machine...
328
329 li r0,MSR_VM_OFF|MASK(MSR_FP) ; Enable for floating point
330 mtmsr r0 /* Set the standard MSR values */
331 isync
332
333 lis r5,HIGH_ADDR(EXT(FloatInit)) /* Get top of floating point init value */
334 ori r5,r5,LOW_ADDR(EXT(FloatInit)) /* Slam bottom */
335 lfd f0,0(r5) /* Initialize FP0 */
336 fmr f1,f0 /* Ours in not */
337 fmr f2,f0 /* to wonder why, */
338 fmr f3,f0 /* ours is but to */
339 fmr f4,f0 /* do or die! */
340 fmr f5,f0
341 fmr f6,f0
342 fmr f7,f0
343 fmr f8,f0
344 fmr f9,f0
345 fmr f10,f0
346 fmr f11,f0
347 fmr f12,f0
348 fmr f13,f0
349 fmr f14,f0
350 fmr f15,f0
351 fmr f16,f0
352 fmr f17,f0
353 fmr f18,f0
354 fmr f19,f0
355 fmr f20,f0
356 fmr f21,f0
357 fmr f22,f0
358 fmr f23,f0
359 fmr f24,f0
360 fmr f25,f0
361 fmr f26,f0
362 fmr f27,f0
363 fmr f28,f0
364 fmr f29,f0
365 fmr f30,f0
366 fmr f31,f0
367
368 li r0, MSR_VM_OFF ; Turn off floating point
369 mtmsr r0
370 isync
371
372 noFloat: rlwinm. r0,r17,0,pfAltivecb,pfAltivecb ; See if there is Altivec
373 beq- noVector ; Nope...
374
375 li r0,0 ; Clear out a register
376
377 lis r7,hi16(MSR_VEC_ON) ; Get real mode MSR + Altivec
378 ori r7,r7,lo16(MSR_VM_OFF) ; Get real mode MSR + Altivec
379 mtmsr r7 ; Set the real mode SRR */
380 isync ; Make sure it has happened
381
382 lis r5,hi16(EXT(QNaNbarbarian)) ; Altivec initializer
383 ori r5,r5,lo16(EXT(QNaNbarbarian)) ; Altivec initializer
384
385 mtspr vrsave,r0 ; Set that no VRs are used yet */
386
387 vspltish v1,1 ; Turn on the non-Java bit and saturate
388 vspltisw v0,1 ; Turn on the saturate bit
389 vxor v1,v1,v0 ; Turn off saturate and leave non-Java set
390 lvx v0,br0,r5 ; Initialize VR0
391 mtvscr v1 ; Clear the vector status register
392 vor v2,v0,v0 ; Copy into the next register
393 vor v1,v0,v0 ; Copy into the next register
394 vor v3,v0,v0 ; Copy into the next register
395 vor v4,v0,v0 ; Copy into the next register
396 vor v5,v0,v0 ; Copy into the next register
397 vor v6,v0,v0 ; Copy into the next register
398 vor v7,v0,v0 ; Copy into the next register
399 vor v8,v0,v0 ; Copy into the next register
400 vor v9,v0,v0 ; Copy into the next register
401 vor v10,v0,v0 ; Copy into the next register
402 vor v11,v0,v0 ; Copy into the next register
403 vor v12,v0,v0 ; Copy into the next register
404 vor v13,v0,v0 ; Copy into the next register
405 vor v14,v0,v0 ; Copy into the next register
406 vor v15,v0,v0 ; Copy into the next register
407 vor v16,v0,v0 ; Copy into the next register
408 vor v17,v0,v0 ; Copy into the next register
409 vor v18,v0,v0 ; Copy into the next register
410 vor v19,v0,v0 ; Copy into the next register
411 vor v20,v0,v0 ; Copy into the next register
412 vor v21,v0,v0 ; Copy into the next register
413 vor v22,v0,v0 ; Copy into the next register
414 vor v23,v0,v0 ; Copy into the next register
415 vor v24,v0,v0 ; Copy into the next register
416 vor v25,v0,v0 ; Copy into the next register
417 vor v26,v0,v0 ; Copy into the next register
418 vor v27,v0,v0 ; Copy into the next register
419 vor v28,v0,v0 ; Copy into the next register
420 vor v29,v0,v0 ; Copy into the next register
421 vor v30,v0,v0 ; Copy into the next register
422 vor v31,v0,v0 ; Copy into the next register
423
424 li r0, MSR_VM_OFF ; Turn off vectors
425 mtmsr r0
426 isync
427
428 noVector:
429 bl EXT(cacheInit) ; Initializes all caches (including the TLB)
430
431 bt bootCPU,run32
432
433 mfsprg r30,0 ; Phys per proc
434 lwz r29,PP_HIBERNATE(r30)
435 andi. r29, r29, 1
436 beq noHashTableInit ; Skip following if not waking from from hibernate
437 bl EXT(hw_clear_maps) ; Mark all maps as absent from hash table
438 bl EXT(hw_hash_init) ; Clear hash table
439 bl EXT(save_snapshot_restore) ; Reset save area chains
440 noHashTableInit:
441 bl EXT(hw_setup_trans) ; Set up hardware needed for translation
442 bl EXT(hw_start_trans) ; Start translating
443
444 run32:
445 rlwinm. r0,r17,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
446 beq++ isnot64 ; Skip following if not 64-bit...
447
448 mfmsr r29 ; Get the MSR
449 rldicl r29,r29,0,MSR_SF_BIT+1 ; turn 64-bit mode off
450 mtmsrd r29 ; Set it
451 isync ; Make sure
452
453 isnot64: bf bootCPU,callcpu
454
455 lis r29,HIGH_ADDR(EXT(intstack)) ; move onto interrupt stack
456 ori r29,r29,LOW_ADDR(EXT(intstack))
457 addi r29,r29,INTSTACK_SIZE-FM_SIZE
458
459 li r28,0
460 stw r28,FM_BACKPTR(r29) ; store a null frame backpointer
461
462 mr r1,r29
463 mr r3,r31 ; Restore any arguments we may have trashed
464
465 ; Note that we exit from here with translation still off
466
467 bl EXT(ppc_init) ; Jump into boot init code
468 BREAKPOINT_TRAP
469
470 callcpu:
471 mfsprg r31,1 ; Fake activation pointer
472 lwz r31,ACT_PER_PROC(r31) ; Load per_proc
473 lwz r29,PP_INTSTACK_TOP_SS(r31) ; move onto interrupt stack
474
475 li r28,0
476 stw r28,FM_BACKPTR(r29) ; store a null frame backpointer
477
478 mr r1,r29 ; move onto new stack
479 mr r3,r31 ; Restore any arguments we may have trashed
480
481 ; Note that we exit from here with translation on
482
483 bl EXT(ppc_init_cpu) ; Jump into cpu init code
484 BREAKPOINT_TRAP ; Should never return
485
486 ;
487 ; Specific processor initialization routines
488 ;
489
490 ; 750
491
492 init750:
493 bf firstBoot, init750nb ; No init for wakeup....
494
495 mfspr r13,l2cr ; Get the L2CR
496 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
497 bne+ i750hl2 ; Yes...
498 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
499
500 i750hl2:
501 lis r14,hi16(256*1024) ; Base L2 size
502 addis r15,r13,0x3000 ; Hah... Figure this one out...
503 rlwinm r15,r15,4,30,31 ; Isolate
504 rlwinm. r8,r13,0,l2siz,l2sizf ; Was size valid?
505 slw r14,r14,r15 ; Set 256KB, 512KB, or 1MB
506 beq- init750l2none ; Not a valid setting...
507
508 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
509 stw r13,pfl2cr(r30) ; Shadow the L2CR
510 stw r14,pfl2Size(r30) ; Set the L2 size
511 b init750l2done ; Done with L2
512
513 init750l2none:
514 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No level 2 cache
515
516 init750l2done:
517 mfspr r11,hid0 ; Get the current HID0
518 stw r11,pfHID0(r30) ; Save the HID0 value
519 blr ; Return...
520
521 init750nb:
522 lwz r11,pfHID0(r30) ; Get HID0
523 sync
524 mtspr hid0,r11 ; Set the HID
525 isync
526 sync
527 blr
528
529 ; 750CX
530
531 init750CX:
532 bf firstBoot, init750 ; No init for wakeup....
533 mfspr r13,hid1 ; Get HID1
534 li r14,lo16(0xFD5F) ; Get valid
535 rlwinm r13,r13,4,28,31 ; Isolate
536 slw r14,r14,r13 ; Position
537 rlwimi r17,r14,15-pfCanNapb,pfCanNapb,pfCanNapb ; Set it
538 b init750 ; Join common...
539
540
541 ; 750FX
542
543 init750FX:
544 bf firstBoot, init750FXnb
545 mfspr r11, hid1
546 stw r11, pfHID1(r30) ; Save the HID1 value
547 b init750
548
549 init750FXnb:
550 lwz r13, pfHID0(r30) ; Get HID0
551 lwz r11, pfHID1(r30) ; Get HID1
552
553 rlwinm. r0, r11, 0, hid1ps, hid1ps ; Isolate the hid1ps bit
554 beq init750FXnb2 ; Clear BTIC if hid1ps set
555 rlwinm r13, r13, 0, btic+1, btic-1 ; Clear the BTIC bit
556
557 init750FXnb2:
558 sync
559 mtspr hid0, r13 ; Set the HID
560 isync
561 sync
562
563 rlwinm r12, r11, 0, hid1ps+1, hid1ps-1 ; Select PLL0
564 mtspr hid1, r12 ; Restore PLL config
565 mftb r13 ; Wait 5000 ticks (> 200 us)
566
567 init750FXnbloop:
568 mftb r14
569 sub r14, r14, r13
570 cmpli cr0, r14, 5000
571 ble init750FXnbloop
572 mtspr hid1, r11 ; Select the desired PLL
573 blr
574
575 ; 750FX vers 2.0 or later
576 init750FXV2:
577 bf firstBoot, init750FXV2nb ; Wake from sleep
578
579 mfspr r11, hid2
580 stw r11, pfHID2(r30) ; Save the HID2 value
581 b init750FX ; Continue with 750FX init
582
583 init750FXV2nb:
584 lwz r13, pfHID2(r30) ; Get HID2
585 rlwinm r13, r13, 0, hid2vmin+1, hid2vmin-1 ; Clear the vmin bit
586 mtspr hid2, r13 ; Restore HID2 value
587 sync ; Wait for it to be done
588 b init750FX
589
590 ; 7400
591
592 init7400: bf firstBoot,i7400nb ; Do different if not initial boot...
593 mfspr r13,l2cr ; Get the L2CR
594 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
595 bne+ i7400hl2 ; Yes...
596 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
597
598 i7400hl2: lis r14,hi16(256*1024) ; Base L2 size
599 addis r15,r13,0x3000 ; Hah... Figure this one out...
600 rlwinm r15,r15,4,30,31
601 slw r14,r14,r15 ; Set 256KB, 512KB, 1MB, or 2MB
602
603 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
604 stw r13,pfl2cr(r30) ; Shadow the L2CR
605 stw r14,pfl2Size(r30) ; Set the L2 size
606
607 mfspr r11,hid0 ; Get the current HID0
608 oris r11,r11,hi16(emcpm|eiecm) ; ?
609 mtspr hid0,r11 ; ?
610 isync
611 stw r11,pfHID0(r30) ; Save the HID0 value
612
613 mfspr r11,msscr0 ; Get the msscr0 register
614 stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
615 mfspr r11,msscr1 ; Get the msscr1 register
616 stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
617 blr ; Return...
618
619 i7400nb:
620 li r11,0
621 mtspr l2cr,r11 ; Make sure L2CR is zero
622 lwz r11,pfHID0(r30) ; Get HID0
623 sync
624 mtspr hid0,r11 ; Set the HID
625 isync
626 sync
627 lwz r11,pfMSSCR0(r30) ; Get MSSCR0
628 isync
629 sync
630 mtspr msscr0,r11 ; Set the MSSCR0
631 lwz r11,pfMSSCR1(r30) ; Get msscr1
632 isync
633 sync
634 mtspr msscr1,r11 ; Set the msscr1
635 isync
636 sync
637 blr
638
639 ; 7400 (ver 2.0 - ver 2.7)
640
641 init7400v2_7:
642 bf firstBoot, init7400
643 mfspr r13, hid0 ; Get the HID0
644 ori r13, r13, nopdstm ; ?
645 mtspr hid0, r13 ; Set the HID0
646 isync
647 sync
648 b init7400
649
650 ; 7410
651 ; Note that this is the same as 7400 except we initialize the l2cr2 register
652
653 init7410: li r13,0 ; Clear
654 mtspr 1016,r13 ; Turn off direct cache
655 b init7400 ; Join up with common....
656
657
658 ; 745X - Any 7450 family processor
659
660 init745X:
661 bf firstBoot,init745Xnb ; Do different if not initial boot...
662
663 mfspr r13,l2cr ; Get the L2CR
664 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
665 bne+ init745Xhl2 ; Yes...
666 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
667
668 init745Xhl2:
669 mfpvr r14 ; Get processor version
670 rlwinm r14,r14,16,16,31 ; Isolate processor version
671 cmpli cr0, r14, PROCESSOR_VERSION_7457 ; Test for 7457 or
672 cmpli cr1, r14, PROCESSOR_VERSION_7447A ; 7447A
673 cror cr0_eq, cr1_eq, cr0_eq
674 lis r14,hi16(512*1024) ; 512KB L2
675 beq init745Xhl2_2
676
677 lis r14,hi16(256*1024) ; Base L2 size
678 rlwinm r15,r13,22,12,13 ; Convert to 256k, 512k, or 768k
679 add r14,r14,r15 ; Add in minimum
680
681 init745Xhl2_2:
682 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
683 stw r13,pfl2cr(r30) ; Shadow the L2CR
684 stw r14,pfl2Size(r30) ; Set the L2 size
685
686 ; Take care of level 3 cache
687
688 mfspr r13,l3cr ; Get the L3CR
689 rlwinm. r0,r13,0,l3e,l3e ; Any L3?
690 bne+ init745Xhl3 ; Yes...
691 rlwinm r17,r17,0,pfL3b+1,pfL3b-1 ; No L3, turn off feature
692
693 init745Xhl3: cmplwi cr0,r13,0 ; No L3 if L3CR is zero
694 beq- init745Xnone ; Go turn off the features...
695 lis r14,hi16(1024*1024) ; Base L3 size
696 rlwinm r15,r13,4,31,31 ; Get size multiplier
697 slw r14,r14,r15 ; Set 1 or 2MB
698
699 stw r13,pfl3crOriginal(r30) ; Shadow the L3CR
700 stw r13,pfl3cr(r30) ; Shadow the L3CR
701 stw r14,pfl3Size(r30) ; Set the L3 size
702 b init745Xfin ; Return....
703
704 init745Xnone:
705 rlwinm r17,r17,0,pfL3fab+1,pfL3b-1 ; No 3rd level cache or assist
706 rlwinm r11,r17,pfWillNapb-pfCanNapb,pfCanNapb,pfCanNapb ; Set pfCanNap if pfWillNap is set
707 or r17,r17,r11
708
709 init745Xfin:
710 rlwinm r17,r17,0,pfWillNapb+1,pfWillNapb-1 ; Make sure pfWillNap is not set
711
712 mfspr r11,hid0 ; Get the current HID0
713 stw r11,pfHID0(r30) ; Save the HID0 value
714 mfspr r11,hid1 ; Get the current HID1
715 stw r11,pfHID1(r30) ; Save the HID1 value
716 mfspr r11,msscr0 ; Get the msscr0 register
717 stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
718 mfspr r11,msscr1 ; Get the msscr1 register
719 stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
720 mfspr r11,ictrl ; Get the ictrl register
721 stw r11,pfICTRL(r30) ; Save the ICTRL value
722 mfspr r11,ldstcr ; Get the ldstcr register
723 stw r11,pfLDSTCR(r30) ; Save the LDSTCR value
724 mfspr r11,ldstdb ; Get the ldstdb register
725 stw r11,pfLDSTDB(r30) ; Save the LDSTDB value
726 mfspr r11,pir ; Get the pir register
727 stw r11,pfBootConfig(r30) ; Save the BootConfig value
728 blr ; Return....
729
730
731 init745Xnb: lwz r11,pfHID0(r30) ; Get HID0
732 sync
733 mtspr hid0,r11 ; Set the HID
734 isync
735 lwz r11,pfHID1(r30) ; Get HID1
736 sync
737 mtspr hid1,r11 ; Set the HID
738 isync
739 lwz r11,pfMSSCR0(r30) ; Get MSSCR0
740 sync
741 mtspr msscr0,r11 ; Set the MSSCR0
742 isync
743 sync
744 lwz r11,pfICTRL(r30) ; Get ICTRL
745 sync
746 mtspr ictrl,r11 ; Set the ICTRL
747 isync
748 sync
749 lwz r11,pfLDSTCR(r30) ; Get LDSTCR
750 sync
751 mtspr ldstcr,r11 ; Set the LDSTCR
752 isync
753 sync
754 lwz r11,pfLDSTDB(r30) ; Get LDSTDB
755 sync
756 mtspr ldstdb,r11 ; Set the LDSTDB
757 isync
758 sync
759 blr
760
761 ; 7450 - Specific
762
763 init7450:
764 bf firstBoot, init745X ; Not boot, use standard init
765
766 mfspr r13, pir ; Get BootConfig from PIR
767 rlwinm. r14, r13, 0, 20, 23 ; Is the pdet value zero
768 bne init7450done ; No, done for now
769
770 ori r13, r13, 0x0400 ; Force pdet value to 4
771 mtspr pir, r13 ; Write back the BootConfig
772
773 init7450done:
774 b init745X ; Continue with standard init
775
776
777 init970:
778 lis r20,8 ; Set up for 512K L2
779 init970x:
780 li r0,0 ; Clear this
781 mtspr hior,r0 ; Make sure that 0 is interrupt prefix
782 bf firstBoot,init970nb ; No init for wakeup or second processor....
783
784
785 ;
786 ; We can not query or change the L2 size. We will just
787 ; phoney up a L2CR to make sysctl "happy" and set the
788 ; L2 size to 512K.
789 ;
790
791 lis r0,0x8000 ; Synthesize a "valid" but non-existant L2CR
792 stw r0,pfl2crOriginal(r30) ; Set a dummy L2CR
793 stw r0,pfl2cr(r30) ; Set a dummy L2CR
794 stw r20,pfl2Size(r30) ; Set the L2 size
795
796 mfspr r11,hid0 ; Get original hid0
797 std r11,pfHID0(r30) ; Save original
798 mfspr r11,hid1 ; Get original hid1
799 std r11,pfHID1(r30) ; Save original
800 mfspr r11,hid4 ; Get original hid4
801 std r11,pfHID4(r30) ; Save original
802 mfspr r11,hid5 ; Get original hid5
803 std r11,pfHID5(r30) ; Save original
804
805 lis r0, hi16(dnapm) ; Create a mask for the dnap bit
806 sldi r0, r0, 32 ; Shift to the top half
807 ld r11,pfHID0(r30) ; Load the hid0 value
808 andc r11, r11, r0 ; Clear the dnap bit
809 isync
810 mtspr hid0,r11 ; Stuff it
811 mfspr r11,hid0 ; Get it
812 mfspr r11,hid0 ; Get it
813 mfspr r11,hid0 ; Get it
814 mfspr r11,hid0 ; Get it
815 mfspr r11,hid0 ; Get it
816 mfspr r11,hid0 ; Get it
817 isync
818
819 lis r0,(pcfValid|pcfLarge|pcfDedSeg)<<8 ; Set the valid bit, dedicated segment, and large page flags
820 ori r0,r0,(24<<8)|24 ; Add in the 16M page size
821 stw r0,lgpPcfg+(pcfSize*pcfLargePcfg)(0) ; Set the 16M primary large page configuration entry
822
823 blr
824
825 ;
826 ; Start up code for second processor or wake up from sleep
827 ;
828
829 init970nb:
830 lis r0, hi16(dnapm) ; Create a mask for the dnap bit
831 sldi r0, r0, 32 ; Shift to the top half
832 ld r11,pfHID0(r30) ; Load the hid0 value
833 andc r11, r11, r0 ; Clear the dnap bit
834 isync
835 mtspr hid0,r11 ; Stuff it
836 mfspr r11,hid0 ; Get it
837 mfspr r11,hid0 ; Get it
838 mfspr r11,hid0 ; Get it
839 mfspr r11,hid0 ; Get it
840 mfspr r11,hid0 ; Get it
841 mfspr r11,hid0 ; Get it
842 isync
843
844 ld r20,pfHID1(r30) ; Get it
845 isync
846 mtspr hid1,r20 ; Stick it
847 mtspr hid1,r20 ; Stick it again
848 isync
849
850 ld r11,pfHID4(r30) ; Get it
851 sync
852 mtspr hid4,r11 ; Stick it
853 isync
854
855 lis r11,0xE000 ; Get the unlikeliest ESID possible
856 srdi r11,r11,1 ; Make 0x7FFFFFFFF0000000
857 slbie r11 ; Make sure the ERAT is cleared
858
859 ld r11,pfHID5(r30) ; Get it
860 mtspr hid5,r11 ; Set it
861 isync
862 ;
863 ; May have changed dcbz mode so kill icache
864 ;
865
866 eqv r13,r13,r13 ; Get a constant -1
867 mr r14,r20 ; Save HID1
868 rldimi r14,r13,54,9 ; Set force icbi match mode
869
870 li r11,0 ; Set start if ICBI range
871 isync
872 mtspr hid1,r14 ; Stick it
873 mtspr hid1,r14 ; Stick it again
874 isync
875
876 inin970ki: icbi 0,r11 ; Kill I$
877 addi r11,r11,128 ; Next line
878 andis. r0,r11,1 ; Have we done them all?
879 beq++ inin970ki ; Not yet...
880
881 isync
882 mtspr hid1,r20 ; Stick it
883 mtspr hid1,r20 ; Stick it again
884 isync
885
886 blr ; Leave...
887
888
889
890 ; Unsupported Processors
891 initUnsupported:
892 mtlr r2 ; Restore the return address
893 blr ; Return to the booter
894
895
896 ;
897 ; Processor to feature table
898
899 ; .align 2 - Always on word boundary
900 ; .long ptFilter - Mask of significant bits in the Version/Revision code
901 ; - NOTE: Always order from most restrictive to least restrictive matching
902 ; .short ptVersion - Version code from PVR. Always start with 0 which is default
903 ; .short ptRevision - Revision code from PVR. A zero value denotes the generic attributes if not specific
904 ; .long ptFeatures - Available features
905 ; .long ptCPUCap - Default value for _cpu_capabilities
906 ; .long ptPwrModes - Available power management features
907 ; .long ptPatch - Patch features
908 ; .long ptInitRout - Initilization routine. Can modify any of the other attributes.
909 ; .long ptRptdProc - Processor type reported
910 ; .long ptLineSize - Level 1 cache line size
911 ; .long ptl1iSize - Level 1 instruction cache size
912 ; .long ptl1dSize - Level 1 data cache size
913 ; .long ptPTEG - Size of PTEG
914 ; .long ptMaxVAddr - Maximum effective address
915 ; .long ptMaxPAddr - Maximum physical address
916 ;
917
918 .align 2
919 processor_types:
920
921 ; 750CX (ver 2.x)
922
923 .align 2
924 .long 0xFFFF0F00 ; 2.x vers
925 .short PROCESSOR_VERSION_750
926 .short 0x0200
927 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2
928 .long kCache32 | kHasGraphicsOps | kHasStfiwx
929 .long 0
930 .long PatchExt32
931 .long init750CX
932 .long CPU_SUBTYPE_POWERPC_750
933 .long 32
934 .long 32*1024
935 .long 32*1024
936 .long 64
937 .long 52
938 .long 32
939
940 ; 750 (generic)
941
942 .align 2
943 .long 0xFFFF0000 ; All revisions
944 .short PROCESSOR_VERSION_750
945 .short 0
946 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2
947 .long kCache32 | kHasGraphicsOps | kHasStfiwx
948 .long 0
949 .long PatchExt32
950 .long init750
951 .long CPU_SUBTYPE_POWERPC_750
952 .long 32
953 .long 32*1024
954 .long 32*1024
955 .long 64
956 .long 52
957 .long 32
958
959 ; 750FX (ver 1.x)
960
961 .align 2
962 .long 0xFFFF0F00 ; 1.x vers
963 .short PROCESSOR_VERSION_750FX
964 .short 0x0100
965 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pf32Byte | pfL2
966 .long kCache32 | kHasGraphicsOps | kHasStfiwx
967 .long pmDualPLL
968 .long PatchExt32
969 .long init750FX
970 .long CPU_SUBTYPE_POWERPC_750
971 .long 32
972 .long 32*1024
973 .long 32*1024
974 .long 64
975 .long 52
976 .long 32
977
978 ; 750FX (generic)
979
980 .align 2
981 .long 0xFFFF0000 ; All revisions
982 .short PROCESSOR_VERSION_750FX
983 .short 0
984 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pf32Byte | pfL2
985 .long kCache32 | kHasGraphicsOps | kHasStfiwx
986 .long pmDualPLL | pmDPLLVmin
987 .long PatchExt32
988 .long init750FXV2
989 .long CPU_SUBTYPE_POWERPC_750
990 .long 32
991 .long 32*1024
992 .long 32*1024
993 .long 64
994 .long 52
995 .long 32
996
997 ; 7400 (ver 2.0 - ver 2.7)
998
999 .align 2
1000 .long 0xFFFFFFF8 ; ver 2.0 - 2.7
1001 .short PROCESSOR_VERSION_7400
1002 .short 0x0200
1003 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1004 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1005 .long 0
1006 .long PatchExt32
1007 .long init7400v2_7
1008 .long CPU_SUBTYPE_POWERPC_7400
1009 .long 32
1010 .long 32*1024
1011 .long 32*1024
1012 .long 64
1013 .long 52
1014 .long 32
1015
1016 ; 7400 (generic)
1017
1018 .align 2
1019 .long 0xFFFF0000 ; All revisions
1020 .short PROCESSOR_VERSION_7400
1021 .short 0
1022 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1023 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1024 .long 0
1025 .long PatchExt32
1026 .long init7400
1027 .long CPU_SUBTYPE_POWERPC_7400
1028 .long 32
1029 .long 32*1024
1030 .long 32*1024
1031 .long 64
1032 .long 52
1033 .long 36
1034
1035 ; 7410 (ver 1.1)
1036
1037 .align 2
1038 .long 0xFFFFFFFF ; Exact match
1039 .short PROCESSOR_VERSION_7400
1040 .short 0x1101
1041 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1042 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1043 .long 0
1044 .long PatchExt32
1045 .long init7410
1046 .long CPU_SUBTYPE_POWERPC_7400
1047 .long 32
1048 .long 32*1024
1049 .long 32*1024
1050 .long 64
1051 .long 52
1052 .long 36
1053
1054 ; 7410 (generic)
1055
1056 .align 2
1057 .long 0xFFFF0000 ; All other revisions
1058 .short PROCESSOR_VERSION_7410
1059 .short 0
1060 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1061 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1062 .long 0
1063 .long PatchExt32
1064 .long init7410
1065 .long CPU_SUBTYPE_POWERPC_7400
1066 .long 32
1067 .long 32*1024
1068 .long 32*1024
1069 .long 64
1070 .long 52
1071 .long 36
1072
1073 ; 7450 (ver 1.xx)
1074
1075 .align 2
1076 .long 0xFFFFFF00 ; Just revisions 1.xx
1077 .short PROCESSOR_VERSION_7450
1078 .short 0x0100
1079 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1080 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1081 .long 0
1082 .long PatchExt32
1083 .long init7450
1084 .long CPU_SUBTYPE_POWERPC_7450
1085 .long 32
1086 .long 32*1024
1087 .long 32*1024
1088 .long 64
1089 .long 52
1090 .long 36
1091
1092 ; 7450 (2.0)
1093
1094 .align 2
1095 .long 0xFFFFFFFF ; Just revision 2.0
1096 .short PROCESSOR_VERSION_7450
1097 .short 0x0200
1098 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1099 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1100 .long 0
1101 .long PatchExt32
1102 .long init7450
1103 .long CPU_SUBTYPE_POWERPC_7450
1104 .long 32
1105 .long 32*1024
1106 .long 32*1024
1107 .long 64
1108 .long 52
1109 .long 36
1110
1111 ; 7450 (2.1)
1112
1113 .align 2
1114 .long 0xFFFF0000 ; All other revisions
1115 .short PROCESSOR_VERSION_7450
1116 .short 0
1117 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1118 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1119 .long 0
1120 .long PatchExt32
1121 .long init7450
1122 .long CPU_SUBTYPE_POWERPC_7450
1123 .long 32
1124 .long 32*1024
1125 .long 32*1024
1126 .long 64
1127 .long 52
1128 .long 36
1129
1130 ; 7455 (1.xx) Just like 7450 2.0
1131
1132 .align 2
1133 .long 0xFFFFFF00 ; Just revisions 1.xx
1134 .short PROCESSOR_VERSION_7455
1135 .short 0x0100
1136 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1137 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1138 .long 0
1139 .long PatchExt32
1140 .long init745X
1141 .long CPU_SUBTYPE_POWERPC_7450
1142 .long 32
1143 .long 32*1024
1144 .long 32*1024
1145 .long 64
1146 .long 52
1147 .long 36
1148
1149 ; 7455 (2.0)
1150
1151 .align 2
1152 .long 0xFFFFFFFF ; Just revision 2.0
1153 .short PROCESSOR_VERSION_7455
1154 .short 0x0200
1155 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1156 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1157 .long 0
1158 .long PatchExt32
1159 .long init745X
1160 .long CPU_SUBTYPE_POWERPC_7450
1161 .long 32
1162 .long 32*1024
1163 .long 32*1024
1164 .long 64
1165 .long 52
1166 .long 36
1167
1168 ; 7455 (2.1)
1169
1170 .align 2
1171 .long 0xFFFF0000 ; All other revisions
1172 .short PROCESSOR_VERSION_7455
1173 .short 0
1174 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1175 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1176 .long 0
1177 .long PatchExt32
1178 .long init745X
1179 .long CPU_SUBTYPE_POWERPC_7450
1180 .long 32
1181 .long 32*1024
1182 .long 32*1024
1183 .long 64
1184 .long 52
1185 .long 36
1186
1187 ; 7457
1188
1189 .align 2
1190 .long 0xFFFF0000 ; All revisions
1191 .short PROCESSOR_VERSION_7457
1192 .short 0
1193 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1194 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1195 .long 0
1196 .long PatchExt32
1197 .long init745X
1198 .long CPU_SUBTYPE_POWERPC_7450
1199 .long 32
1200 .long 32*1024
1201 .long 32*1024
1202 .long 64
1203 .long 52
1204 .long 36
1205
1206 ; 7447A
1207
1208 .align 2
1209 .long 0xFFFF0000 ; All revisions
1210 .short PROCESSOR_VERSION_7447A
1211 .short 0
1212 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1213 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1214 .long pmDFS
1215 .long PatchExt32
1216 .long init745X
1217 .long CPU_SUBTYPE_POWERPC_7450
1218 .long 32
1219 .long 32*1024
1220 .long 32*1024
1221 .long 64
1222 .long 52
1223 .long 36
1224
1225 ; 970
1226
1227 .align 2
1228 .long 0xFFFF0000 ; All versions so far
1229 .short PROCESSOR_VERSION_970
1230 .short 0
1231 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pf128Byte | pf64Bit | pfL2 | pfSCOMFixUp
1232 .long kHasAltivec | k64Bit | kCache128 | kDataStreamsAvailable | kDcbtStreamsRecommended | kDcbtStreamsAvailable | kHasGraphicsOps | kHasStfiwx | kHasFsqrt
1233 .long 0
1234 .long PatchLwsync
1235 .long init970
1236 .long CPU_SUBTYPE_POWERPC_970
1237 .long 128
1238 .long 64*1024
1239 .long 32*1024
1240 .long 128
1241 .long 65
1242 .long 42
1243
1244 ; 970FX
1245
1246 .align 2
1247 .long 0xFFFF0000 ; All versions so far
1248 .short PROCESSOR_VERSION_970FX
1249 .short 0
1250 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pf128Byte | pf64Bit | pfL2
1251 .long kHasAltivec | k64Bit | kCache128 | kDataStreamsAvailable | kDcbtStreamsRecommended | kDcbtStreamsAvailable | kHasGraphicsOps | kHasStfiwx | kHasFsqrt
1252 .long pmPowerTune
1253 .long PatchLwsync
1254 .long init970
1255 .long CPU_SUBTYPE_POWERPC_970
1256 .long 128
1257 .long 64*1024
1258 .long 32*1024
1259 .long 128
1260 .long 65
1261 .long 42
1262
1263
1264 ; All other processors are not supported
1265
1266 .align 2
1267 .long 0x00000000 ; Matches everything
1268 .short 0
1269 .short 0
1270 .long pfFloat | pf32Byte
1271 .long kCache32 | kHasGraphicsOps | kHasStfiwx
1272 .long 0
1273 .long PatchExt32
1274 .long initUnsupported
1275 .long CPU_SUBTYPE_POWERPC_ALL
1276 .long 32
1277 .long 32*1024
1278 .long 32*1024
1279 .long 64
1280 .long 52
1281 .long 32
1282
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