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[apple/xnu.git] / osfmk / ppc / chud / chud_cpu.c
1 /*
2 * Copyright (c) 2003-2004 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_OSREFERENCE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the
10 * License may not be used to create, or enable the creation or
11 * redistribution of, unlawful or unlicensed copies of an Apple operating
12 * system, or to circumvent, violate, or enable the circumvention or
13 * violation of, any terms of an Apple operating system software license
14 * agreement.
15 *
16 * Please obtain a copy of the License at
17 * http://www.opensource.apple.com/apsl/ and read it before using this
18 * file.
19 *
20 * The Original Code and all software distributed under the License are
21 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
22 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
23 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
25 * Please see the License for the specific language governing rights and
26 * limitations under the License.
27 *
28 * @APPLE_LICENSE_OSREFERENCE_HEADER_END@
29 */
30 #include <mach/mach_types.h>
31 #include <mach/mach_host.h>
32
33 #include <kern/host.h>
34 #include <kern/processor.h>
35
36 #include <ppc/chud/chud_spr.h>
37 #include <ppc/chud/chud_xnu.h>
38 #include <ppc/chud/chud_cpu_asm.h>
39 #include <ppc/machine_routines.h>
40 #include <ppc/exception.h>
41 #include <ppc/hw_perfmon.h>
42 #include <ppc/Diagnostics.h>
43
44 // the macros in proc_reg.h fail with "expression must be absolute"
45
46 #undef mtsprg
47 #undef mfsprg
48 #define mtsprg(n, reg) __asm__ volatile("mtsprg " # n ", %0" : : "r" (reg))
49 #define mfsprg(reg, n) __asm__ volatile("mfsprg %0, " # n : "=r" (reg))
50
51 #undef mtspr
52 #undef mfspr
53 #define mtspr(spr, reg) __asm__ volatile ("mtspr %0, %1" : : "n" (spr), "r" (reg))
54 #define mfspr(reg, spr) __asm__ volatile("mfspr %0, %1" : "=r" (reg) : "n" (spr));
55
56 #undef mtsr
57 #undef mfsr
58 #define mtsr(sr, reg) __asm__ volatile("sync" "@" "mtsr sr%0, %1 " "@" "isync" : : "i" (sr), "r" (reg));
59 #define mfsr(reg, sr) __asm__ volatile("mfsr %0, sr%1" : "=r" (reg) : "i" (sr));
60
61 #pragma mark **** cpu count ****
62
63 __private_extern__
64 int chudxnu_avail_cpu_count(void)
65 {
66 host_basic_info_data_t hinfo;
67 kern_return_t kr;
68 mach_msg_type_number_t count = HOST_BASIC_INFO_COUNT;
69
70 kr = host_info(host_self(), HOST_BASIC_INFO, (integer_t *)&hinfo, &count);
71 if(kr == KERN_SUCCESS) {
72 return hinfo.avail_cpus;
73 } else {
74 return 0;
75 }
76 }
77
78 __private_extern__
79 int chudxnu_phys_cpu_count(void)
80 {
81 host_basic_info_data_t hinfo;
82 kern_return_t kr;
83 mach_msg_type_number_t count = HOST_BASIC_INFO_COUNT;
84
85 kr = host_info(host_self(), HOST_BASIC_INFO, (integer_t *)&hinfo, &count);
86 if(kr == KERN_SUCCESS) {
87 return hinfo.max_cpus;
88 } else {
89 return 0;
90 }
91 }
92
93 __private_extern__
94 int chudxnu_cpu_number(void)
95 {
96 return cpu_number();
97 }
98
99 #pragma mark **** cpu enable/disable ****
100
101 extern kern_return_t processor_start(processor_t processor); // osfmk/kern/processor.c
102 extern kern_return_t processor_exit(processor_t processor); // osfmk/kern/processor.c
103
104 __private_extern__
105 kern_return_t chudxnu_enable_cpu(int cpu, boolean_t enable)
106 {
107 chudxnu_unbind_thread(current_thread());
108
109 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
110 return KERN_FAILURE;
111 }
112
113 if((PerProcTable[cpu].ppe_vaddr != (struct per_proc_info *)NULL)
114 && cpu != master_cpu) {
115 processor_t processor = cpu_to_processor(cpu);
116
117 if(enable) {
118 return processor_start(processor);
119 } else {
120 return processor_exit(processor);
121 }
122 }
123 return KERN_FAILURE;
124 }
125
126 #pragma mark **** nap ****
127
128 __private_extern__
129 kern_return_t chudxnu_enable_cpu_nap(int cpu, boolean_t enable)
130 {
131 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
132 return KERN_FAILURE;
133 }
134
135 if(PerProcTable[cpu].ppe_vaddr != (struct per_proc_info *)NULL) {
136 ml_enable_nap(cpu, enable);
137 return KERN_SUCCESS;
138 }
139
140 return KERN_FAILURE;
141 }
142
143 __private_extern__
144 boolean_t chudxnu_cpu_nap_enabled(int cpu)
145 {
146 boolean_t prev;
147
148 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
149 cpu = 0;
150 }
151
152 prev = ml_enable_nap(cpu, TRUE);
153 ml_enable_nap(cpu, prev);
154
155 return prev;
156 }
157
158 #pragma mark **** shadowed spr ****
159
160 __private_extern__
161 kern_return_t chudxnu_set_shadowed_spr(int cpu, int spr, uint32_t val)
162 {
163 cpu_subtype_t target_cpu_subtype;
164 uint32_t available;
165 kern_return_t retval = KERN_FAILURE;
166 struct per_proc_info *per_proc;
167 boolean_t didBind = FALSE;
168
169 if(cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
170 return KERN_FAILURE;
171 }
172
173 if(cpu<0) { // cpu<0 means don't bind (current cpu)
174 cpu = chudxnu_cpu_number();
175 didBind = FALSE;
176 } else {
177 chudxnu_bind_thread(current_thread(), cpu);
178 didBind = TRUE;
179 }
180
181 per_proc = PerProcTable[cpu].ppe_vaddr;
182 available = per_proc->pf.Available;
183 target_cpu_subtype = per_proc->cpu_subtype;
184
185 if(spr==chud_750_l2cr) {
186 switch(target_cpu_subtype) {
187 case CPU_SUBTYPE_POWERPC_750:
188 case CPU_SUBTYPE_POWERPC_7400:
189 case CPU_SUBTYPE_POWERPC_7450:
190 if(available & pfL2) {
191 // int enable = (val & 0x80000000) ? TRUE : FALSE;
192 // if(enable) {
193 // per_proc->pf.l2cr = val;
194 // } else {
195 // per_proc->pf.l2cr = 0;
196 // }
197 per_proc->pf.l2cr = val;
198 cacheInit();
199 // mtspr(l2cr, per_proc->pf.l2cr); // XXXXXXX why is this necessary? XXXXXXX
200 retval = KERN_SUCCESS;
201 } else {
202 retval = KERN_FAILURE;
203 }
204 break;
205 default:
206 retval = KERN_INVALID_ARGUMENT;
207 break;
208 }
209 }
210 else if(spr==chud_7450_l3cr) {
211 switch(target_cpu_subtype) {
212 case CPU_SUBTYPE_POWERPC_7450:
213 if(available & pfL3) {
214 int enable = (val & 0x80000000) ? TRUE : FALSE;
215 if(enable) {
216 per_proc->pf.l3cr = val;
217 } else {
218 per_proc->pf.l3cr = 0;
219 }
220 cacheInit();
221 retval = KERN_SUCCESS;
222 } else {
223 retval = KERN_FAILURE;
224 }
225 break;
226 default:
227 retval = KERN_INVALID_ARGUMENT;
228 break;
229 }
230 }
231 else if(spr==chud_750_hid0) {
232 switch(target_cpu_subtype) {
233 case CPU_SUBTYPE_POWERPC_750:
234 cacheInit();
235 cacheDisable(); /* disable caches */
236 mtspr(chud_750_hid0, val);
237 per_proc->pf.pfHID0 = val;
238 cacheInit(); /* reenable caches */
239 retval = KERN_SUCCESS;
240 break;
241 case CPU_SUBTYPE_POWERPC_7400:
242 case CPU_SUBTYPE_POWERPC_7450:
243 mtspr(chud_750_hid0, val);
244 per_proc->pf.pfHID0 = val;
245 retval = KERN_SUCCESS;
246 break;
247 default:
248 retval = KERN_INVALID_ARGUMENT;
249 break;
250 }
251 }
252 else if(spr==chud_750_hid1) {
253 switch(target_cpu_subtype) {
254 case CPU_SUBTYPE_POWERPC_750:
255 case CPU_SUBTYPE_POWERPC_7400:
256 case CPU_SUBTYPE_POWERPC_7450:
257 mtspr(chud_750_hid1, val);
258 per_proc->pf.pfHID1 = val;
259 retval = KERN_SUCCESS;
260 break;
261 default:
262 retval = KERN_INVALID_ARGUMENT;
263 break;
264 }
265 }
266 else if(spr==chud_750fx_hid2 && target_cpu_subtype==CPU_SUBTYPE_POWERPC_750) {
267 mtspr(chud_750fx_hid2, val);
268 per_proc->pf.pfHID2 = val;
269 retval = KERN_SUCCESS;
270 }
271 else if(spr==chud_7400_msscr0 && (target_cpu_subtype==CPU_SUBTYPE_POWERPC_7400 || target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450)) {
272 mtspr(chud_7400_msscr0, val);
273 per_proc->pf.pfMSSCR0 = val;
274 retval = KERN_SUCCESS;
275 }
276 else if(spr==chud_7400_msscr1 && (target_cpu_subtype==CPU_SUBTYPE_POWERPC_7400 || target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450)) { // called msssr0 on 7450
277 mtspr(chud_7400_msscr1, val);
278 per_proc->pf.pfMSSCR1 = val;
279 retval = KERN_SUCCESS;
280 }
281 else if(spr==chud_7450_ldstcr && target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450) {
282 mtspr(chud_7450_ldstcr, val);
283 per_proc->pf.pfLDSTCR = val;
284 retval = KERN_SUCCESS;
285 }
286 else if(spr==chud_7450_ictrl && target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450) {
287 mtspr(chud_7450_ictrl, val);
288 per_proc->pf.pfICTRL = val;
289 retval = KERN_SUCCESS;
290 } else {
291 retval = KERN_INVALID_ARGUMENT;
292 }
293
294 if(didBind) {
295 chudxnu_unbind_thread(current_thread());
296 }
297
298 return retval;
299 }
300
301 __private_extern__
302 kern_return_t chudxnu_set_shadowed_spr64(int cpu, int spr, uint64_t val)
303 {
304 cpu_subtype_t target_cpu_subtype;
305 kern_return_t retval = KERN_FAILURE;
306 struct per_proc_info *per_proc;
307 boolean_t didBind = FALSE;
308
309 if(cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
310 return KERN_FAILURE;
311 }
312
313 if(cpu<0) { // cpu<0 means don't bind (current cpu)
314 cpu = chudxnu_cpu_number();
315 didBind = FALSE;
316 } else {
317 chudxnu_bind_thread(current_thread(), cpu);
318 didBind = TRUE;
319 }
320
321 per_proc = PerProcTable[cpu].ppe_vaddr;
322 target_cpu_subtype = per_proc->cpu_subtype;
323
324 if(spr==chud_970_hid0) {
325 switch(target_cpu_subtype) {
326 case CPU_SUBTYPE_POWERPC_970:
327 mtspr64(chud_970_hid0, &val);
328 per_proc->pf.pfHID0 = val;
329 retval = KERN_SUCCESS;
330 break;
331 default:
332 retval = KERN_INVALID_ARGUMENT;
333 break;
334 }
335 }
336 else if(spr==chud_970_hid1) {
337 switch(target_cpu_subtype) {
338 case CPU_SUBTYPE_POWERPC_970:
339 mtspr64(chud_970_hid1, &val);
340 per_proc->pf.pfHID1 = val;
341 retval = KERN_SUCCESS;
342 break;
343 default:
344 retval = KERN_INVALID_ARGUMENT;
345 break;
346 }
347 }
348 else if(spr==chud_970_hid4) {
349 switch(target_cpu_subtype) {
350 case CPU_SUBTYPE_POWERPC_970:
351 mtspr64(chud_970_hid4, &val);
352 per_proc->pf.pfHID4 = val;
353 retval = KERN_SUCCESS;
354 break;
355 default:
356 retval = KERN_INVALID_ARGUMENT;
357 break;
358 }
359 }
360 else if(spr==chud_970_hid5) {
361 switch(target_cpu_subtype) {
362 case CPU_SUBTYPE_POWERPC_970:
363 mtspr64(chud_970_hid5, &val);
364 per_proc->pf.pfHID5 = val;
365 retval = KERN_SUCCESS;
366 break;
367 default:
368 retval = KERN_INVALID_ARGUMENT;
369 break;
370 }
371 } else {
372 retval = KERN_INVALID_ARGUMENT;
373 }
374
375 if(didBind) {
376 chudxnu_unbind_thread(current_thread());
377 }
378
379 return retval;
380 }
381
382 __private_extern__
383 uint32_t chudxnu_get_orig_cpu_l2cr(int cpu)
384 {
385 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
386 cpu = 0;
387 }
388 return PerProcTable[cpu].ppe_vaddr->pf.l2crOriginal;
389 }
390
391 __private_extern__
392 uint32_t chudxnu_get_orig_cpu_l3cr(int cpu)
393 {
394 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
395 cpu = 0;
396 }
397 return PerProcTable[cpu].ppe_vaddr->pf.l3crOriginal;
398 }
399
400 #pragma mark **** spr ****
401
402 __private_extern__
403 kern_return_t chudxnu_read_spr(int cpu, int spr, uint32_t *val_p)
404 {
405 kern_return_t retval = KERN_SUCCESS;
406 boolean_t oldlevel;
407 uint32_t val = 0xFFFFFFFF;
408
409 /* bind to requested CPU */
410 if(cpu>=0) { // cpu<0 means don't bind
411 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
412 return KERN_INVALID_ARGUMENT;
413 }
414 }
415
416 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
417
418 do {
419 /* PPC SPRs - 32-bit and 64-bit implementations */
420 if(spr==chud_ppc_srr0) { mfspr(val, chud_ppc_srr0); break; }
421 if(spr==chud_ppc_srr1) { mfspr(val, chud_ppc_srr1); break; }
422 if(spr==chud_ppc_dsisr) { mfspr(val, chud_ppc_dsisr); break; }
423 if(spr==chud_ppc_dar) { mfspr(val, chud_ppc_dar); break; }
424 if(spr==chud_ppc_dec) { mfspr(val, chud_ppc_dec); break; }
425 if(spr==chud_ppc_sdr1) { mfspr(val, chud_ppc_sdr1); break; }
426 if(spr==chud_ppc_sprg0) { mfspr(val, chud_ppc_sprg0); break; }
427 if(spr==chud_ppc_sprg1) { mfspr(val, chud_ppc_sprg1); break; }
428 if(spr==chud_ppc_sprg2) { mfspr(val, chud_ppc_sprg2); break; }
429 if(spr==chud_ppc_sprg3) { mfspr(val, chud_ppc_sprg3); break; }
430 if(spr==chud_ppc_ear) { mfspr(val, chud_ppc_ear); break; }
431 if(spr==chud_ppc_tbl) { mfspr(val, 268); break; } /* timebase consists of read registers and write registers */
432 if(spr==chud_ppc_tbu) { mfspr(val, 269); break; }
433 if(spr==chud_ppc_pvr) { mfspr(val, chud_ppc_pvr); break; }
434 if(spr==chud_ppc_ibat0u) { mfspr(val, chud_ppc_ibat0u); break; }
435 if(spr==chud_ppc_ibat0l) { mfspr(val, chud_ppc_ibat0l); break; }
436 if(spr==chud_ppc_ibat1u) { mfspr(val, chud_ppc_ibat1u); break; }
437 if(spr==chud_ppc_ibat1l) { mfspr(val, chud_ppc_ibat1l); break; }
438 if(spr==chud_ppc_ibat2u) { mfspr(val, chud_ppc_ibat2u); break; }
439 if(spr==chud_ppc_ibat2l) { mfspr(val, chud_ppc_ibat2l); break; }
440 if(spr==chud_ppc_ibat3u) { mfspr(val, chud_ppc_ibat3u); break; }
441 if(spr==chud_ppc_ibat3l) { mfspr(val, chud_ppc_ibat3l); break; }
442 if(spr==chud_ppc_dbat0u) { mfspr(val, chud_ppc_dbat0u); break; }
443 if(spr==chud_ppc_dbat0l) { mfspr(val, chud_ppc_dbat0l); break; }
444 if(spr==chud_ppc_dbat1u) { mfspr(val, chud_ppc_dbat1u); break; }
445 if(spr==chud_ppc_dbat1l) { mfspr(val, chud_ppc_dbat1l); break; }
446 if(spr==chud_ppc_dbat2u) { mfspr(val, chud_ppc_dbat2u); break; }
447 if(spr==chud_ppc_dbat2l) { mfspr(val, chud_ppc_dbat2l); break; }
448 if(spr==chud_ppc_dbat3u) { mfspr(val, chud_ppc_dbat3u); break; }
449 if(spr==chud_ppc_dbat3l) { mfspr(val, chud_ppc_dbat3l); break; }
450 if(spr==chud_ppc_dabr) { mfspr(val, chud_ppc_dabr); break; }
451 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
452 struct ppc_thread_state64 state;
453 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
454 kern_return_t kr;
455 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
456 if(KERN_SUCCESS==kr) {
457 val = state.srr1;
458 } else {
459 retval = KERN_FAILURE;
460 }
461 break;
462 }
463
464 /* PPC SPRs - 32-bit implementations */
465 if(spr==chud_ppc32_sr0) { mfsr(val, 0); break; }
466 if(spr==chud_ppc32_sr1) { mfsr(val, 1); break; }
467 if(spr==chud_ppc32_sr2) { mfsr(val, 2); break; }
468 if(spr==chud_ppc32_sr3) { mfsr(val, 3); break; }
469 if(spr==chud_ppc32_sr4) { mfsr(val, 4); break; }
470 if(spr==chud_ppc32_sr5) { mfsr(val, 5); break; }
471 if(spr==chud_ppc32_sr6) { mfsr(val, 6); break; }
472 if(spr==chud_ppc32_sr7) { mfsr(val, 7); break; }
473 if(spr==chud_ppc32_sr8) { mfsr(val, 8); break; }
474 if(spr==chud_ppc32_sr9) { mfsr(val, 9); break; }
475 if(spr==chud_ppc32_sr10) { mfsr(val, 10); break; }
476 if(spr==chud_ppc32_sr11) { mfsr(val, 11); break; }
477 if(spr==chud_ppc32_sr12) { mfsr(val, 12); break; }
478 if(spr==chud_ppc32_sr13) { mfsr(val, 13); break; }
479 if(spr==chud_ppc32_sr14) { mfsr(val, 14); break; }
480 if(spr==chud_ppc32_sr15) { mfsr(val, 15); break; }
481
482 /* PPC SPRs - 64-bit implementations */
483 if(spr==chud_ppc64_ctrl) { mfspr(val, chud_ppc64_ctrl); break; }
484
485 /* Implementation Specific SPRs */
486 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_750) {
487 if(spr==chud_750_mmcr0) { mfspr(val, chud_750_mmcr0); break; }
488 if(spr==chud_750_pmc1) { mfspr(val, chud_750_pmc1); break; }
489 if(spr==chud_750_pmc2) { mfspr(val, chud_750_pmc2); break; }
490 if(spr==chud_750_sia) { mfspr(val, chud_750_sia); break; }
491 if(spr==chud_750_mmcr1) { mfspr(val, chud_750_mmcr1); break; }
492 if(spr==chud_750_pmc3) { mfspr(val, chud_750_pmc3); break; }
493 if(spr==chud_750_pmc4) { mfspr(val, chud_750_pmc4); break; }
494 if(spr==chud_750_hid0) { mfspr(val, chud_750_hid0); break; }
495 if(spr==chud_750_hid1) { mfspr(val, chud_750_hid1); break; }
496 if(spr==chud_750_iabr) { mfspr(val, chud_750_iabr); break; }
497 if(spr==chud_750_ictc) { mfspr(val, chud_750_ictc); break; }
498 if(spr==chud_750_thrm1) { mfspr(val, chud_750_thrm1); break; }
499 if(spr==chud_750_thrm2) { mfspr(val, chud_750_thrm2); break; }
500 if(spr==chud_750_thrm3) { mfspr(val, chud_750_thrm3); break; }
501 if(spr==chud_750_l2cr) { mfspr(val, chud_750_l2cr); break; }
502
503 // 750FX only
504 if(spr==chud_750fx_ibat4u) { mfspr(val, chud_750fx_ibat4u); break; }
505 if(spr==chud_750fx_ibat4l) { mfspr(val, chud_750fx_ibat4l); break; }
506 if(spr==chud_750fx_ibat5u) { mfspr(val, chud_750fx_ibat5u); break; }
507 if(spr==chud_750fx_ibat5l) { mfspr(val, chud_750fx_ibat5l); break; }
508 if(spr==chud_750fx_ibat6u) { mfspr(val, chud_750fx_ibat6u); break; }
509 if(spr==chud_750fx_ibat6l) { mfspr(val, chud_750fx_ibat6l); break; }
510 if(spr==chud_750fx_ibat7u) { mfspr(val, chud_750fx_ibat7u); break; }
511 if(spr==chud_750fx_ibat7l) { mfspr(val, chud_750fx_ibat7l); break; }
512 if(spr==chud_750fx_dbat4u) { mfspr(val, chud_750fx_dbat4u); break; }
513 if(spr==chud_750fx_dbat4l) { mfspr(val, chud_750fx_dbat4l); break; }
514 if(spr==chud_750fx_dbat5u) { mfspr(val, chud_750fx_dbat5u); break; }
515 if(spr==chud_750fx_dbat5l) { mfspr(val, chud_750fx_dbat5l); break; }
516 if(spr==chud_750fx_dbat6u) { mfspr(val, chud_750fx_dbat6u); break; }
517 if(spr==chud_750fx_dbat6l) { mfspr(val, chud_750fx_dbat6l); break; }
518 if(spr==chud_750fx_dbat7u) { mfspr(val, chud_750fx_dbat7u); break; }
519 if(spr==chud_750fx_dbat7l) { mfspr(val, chud_750fx_dbat7l); break; }
520
521 // 750FX >= DDR2.x only
522 if(spr==chud_750fx_hid2) { mfspr(val, chud_750fx_hid2); break; }
523 }
524
525 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7400) {
526 if(spr==chud_7400_mmcr2) { mfspr(val, chud_7400_mmcr2); break; }
527 if(spr==chud_7400_bamr) { mfspr(val, chud_7400_bamr); break; }
528 if(spr==chud_7400_mmcr0) { mfspr(val, chud_7400_mmcr0); break; }
529 if(spr==chud_7400_pmc1) { mfspr(val, chud_7400_pmc1); break; }
530 if(spr==chud_7400_pmc2) { mfspr(val, chud_7400_pmc2); break; }
531 if(spr==chud_7400_siar) { mfspr(val, chud_7400_siar); break; }
532 if(spr==chud_7400_mmcr1) { mfspr(val, chud_7400_mmcr1); break; }
533 if(spr==chud_7400_pmc3) { mfspr(val, chud_7400_pmc3); break; }
534 if(spr==chud_7400_pmc4) { mfspr(val, chud_7400_pmc4); break; }
535 if(spr==chud_7400_hid0) { mfspr(val, chud_7400_hid0); break; }
536 if(spr==chud_7400_hid1) { mfspr(val, chud_7400_hid1); break; }
537 if(spr==chud_7400_iabr) { mfspr(val, chud_7400_iabr); break; }
538 if(spr==chud_7400_msscr0) { mfspr(val, chud_7400_msscr0); break; }
539 if(spr==chud_7400_msscr1) { mfspr(val, chud_7400_msscr1); break; } /* private */
540 if(spr==chud_7400_ictc) { mfspr(val, chud_7400_ictc); break; }
541 if(spr==chud_7400_thrm1) { mfspr(val, chud_7400_thrm1); break; }
542 if(spr==chud_7400_thrm2) { mfspr(val, chud_7400_thrm2); break; }
543 if(spr==chud_7400_thrm3) { mfspr(val, chud_7400_thrm3); break; }
544 if(spr==chud_7400_pir) { mfspr(val, chud_7400_pir); break; }
545 if(spr==chud_7400_l2cr) { mfspr(val, chud_7400_l2cr); break; }
546
547 // 7410 only
548 if(spr==chud_7410_l2pmcr) { mfspr(val, chud_7410_l2pmcr); break; }
549 }
550
551 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7450) {
552 if(spr==chud_7450_mmcr2) { mfspr(val, chud_7450_mmcr2); break; }
553 if(spr==chud_7450_pmc5) { mfspr(val, chud_7450_pmc5); break; }
554 if(spr==chud_7450_pmc6) { mfspr(val, chud_7450_pmc6); break; }
555 if(spr==chud_7450_bamr) { mfspr(val, chud_7450_bamr); break; }
556 if(spr==chud_7450_mmcr0) { mfspr(val, chud_7450_mmcr0); break; }
557 if(spr==chud_7450_pmc1) { mfspr(val, chud_7450_pmc1); break; }
558 if(spr==chud_7450_pmc2) { mfspr(val, chud_7450_pmc2); break; }
559 if(spr==chud_7450_siar) { mfspr(val, chud_7450_siar); break; }
560 if(spr==chud_7450_mmcr1) { mfspr(val, chud_7450_mmcr1); break; }
561 if(spr==chud_7450_pmc3) { mfspr(val, chud_7450_pmc3); break; }
562 if(spr==chud_7450_pmc4) { mfspr(val, chud_7450_pmc4); break; }
563 if(spr==chud_7450_tlbmiss) { mfspr(val, chud_7450_tlbmiss); break; }
564 if(spr==chud_7450_ptehi) { mfspr(val, chud_7450_ptehi); break; }
565 if(spr==chud_7450_ptelo) { mfspr(val, chud_7450_ptelo); break; }
566 if(spr==chud_7450_l3pm) { mfspr(val, chud_7450_l3pm); break; }
567 if(spr==chud_7450_hid0) { mfspr(val, chud_7450_hid0); break; }
568 if(spr==chud_7450_hid1) { mfspr(val, chud_7450_hid1); break; }
569 if(spr==chud_7450_iabr) { mfspr(val, chud_7450_iabr); break; }
570 if(spr==chud_7450_ldstdb) { mfspr(val, chud_7450_ldstdb); break; }
571 if(spr==chud_7450_msscr0) { mfspr(val, chud_7450_msscr0); break; }
572 if(spr==chud_7450_msssr0) { mfspr(val, chud_7450_msssr0); break; }
573 if(spr==chud_7450_ldstcr) { mfspr(val, chud_7450_ldstcr); break; }
574 if(spr==chud_7450_ictc) { mfspr(val, chud_7450_ictc); break; }
575 if(spr==chud_7450_ictrl) { mfspr(val, chud_7450_ictrl); break; }
576 if(spr==chud_7450_thrm1) { mfspr(val, chud_7450_thrm1); break; }
577 if(spr==chud_7450_thrm2) { mfspr(val, chud_7450_thrm2); break; }
578 if(spr==chud_7450_thrm3) { mfspr(val, chud_7450_thrm3); break; }
579 if(spr==chud_7450_pir) { mfspr(val, chud_7450_pir); break; }
580 if(spr==chud_7450_l2cr) { mfspr(val, chud_7450_l2cr); break; }
581 if(spr==chud_7450_l3cr) { mfspr(val, chud_7450_l3cr); break; }
582
583 // 7455/7457 only
584 if(spr==chud_7455_sprg4) { mfspr(val, chud_7455_sprg4); break; }
585 if(spr==chud_7455_sprg5) { mfspr(val, chud_7455_sprg5); break; }
586 if(spr==chud_7455_sprg6) { mfspr(val, chud_7455_sprg6); break; }
587 if(spr==chud_7455_sprg7) { mfspr(val, chud_7455_sprg7); break; }
588 if(spr==chud_7455_ibat4u) { mfspr(val, chud_7455_ibat4u); break; }
589 if(spr==chud_7455_ibat4l) { mfspr(val, chud_7455_ibat4l); break; }
590 if(spr==chud_7455_ibat5u) { mfspr(val, chud_7455_ibat5u); break; }
591 if(spr==chud_7455_ibat5l) { mfspr(val, chud_7455_ibat5l); break; }
592 if(spr==chud_7455_ibat6u) { mfspr(val, chud_7455_ibat6u); break; }
593 if(spr==chud_7455_ibat6l) { mfspr(val, chud_7455_ibat6l); break; }
594 if(spr==chud_7455_ibat7u) { mfspr(val, chud_7455_ibat7u); break; }
595 if(spr==chud_7455_ibat7l) { mfspr(val, chud_7455_ibat7l); break; }
596 if(spr==chud_7455_dbat4u) { mfspr(val, chud_7455_dbat4u); break; }
597 if(spr==chud_7455_dbat4l) { mfspr(val, chud_7455_dbat4l); break; }
598 if(spr==chud_7455_dbat5u) { mfspr(val, chud_7455_dbat5u); break; }
599 if(spr==chud_7455_dbat5l) { mfspr(val, chud_7455_dbat5l); break; }
600 if(spr==chud_7455_dbat6u) { mfspr(val, chud_7455_dbat6u); break; }
601 if(spr==chud_7455_dbat6l) { mfspr(val, chud_7455_dbat6l); break; }
602 if(spr==chud_7455_dbat7u) { mfspr(val, chud_7455_dbat7u); break; }
603 if(spr==chud_7455_dbat7l) { mfspr(val, chud_7455_dbat7l); break; }
604 }
605
606 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
607 if(spr==chud_970_pir) { mfspr(val, chud_970_pir); break; }
608 if(spr==chud_970_pmc1) { mfspr(val, chud_970_pmc1); break; }
609 if(spr==chud_970_pmc2) { mfspr(val, chud_970_pmc2); break; }
610 if(spr==chud_970_pmc3) { mfspr(val, chud_970_pmc3); break; }
611 if(spr==chud_970_pmc4) { mfspr(val, chud_970_pmc4); break; }
612 if(spr==chud_970_pmc5) { mfspr(val, chud_970_pmc5); break; }
613 if(spr==chud_970_pmc6) { mfspr(val, chud_970_pmc6); break; }
614 if(spr==chud_970_pmc7) { mfspr(val, chud_970_pmc7); break; }
615 if(spr==chud_970_pmc8) { mfspr(val, chud_970_pmc8); break; }
616 if(spr==chud_970_hdec) { mfspr(val, chud_970_hdec); break; }
617 }
618
619 /* we only get here if none of the above cases qualify */
620 retval = KERN_INVALID_ARGUMENT;
621 } while(0);
622
623 chudxnu_set_interrupts_enabled(oldlevel); /* enable interrupts */
624
625 if(cpu>=0) { // cpu<0 means don't bind
626 chudxnu_unbind_thread(current_thread());
627 }
628
629 *val_p = val;
630
631 return retval;
632 }
633
634 __private_extern__
635 kern_return_t chudxnu_read_spr64(int cpu, int spr, uint64_t *val_p)
636 {
637 kern_return_t retval = KERN_SUCCESS;
638 boolean_t oldlevel;
639
640 /* bind to requested CPU */
641 if(cpu>=0) { // cpu<0 means don't bind
642 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
643 return KERN_INVALID_ARGUMENT;
644 }
645 }
646
647 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
648
649 do {
650 /* PPC SPRs - 32-bit and 64-bit implementations */
651 if(spr==chud_ppc_srr0) { retval = mfspr64(val_p, chud_ppc_srr0); break; }
652 if(spr==chud_ppc_srr1) { retval = mfspr64(val_p, chud_ppc_srr1); break; }
653 if(spr==chud_ppc_dar) { retval = mfspr64(val_p, chud_ppc_dar); break; }
654 if(spr==chud_ppc_dsisr) { retval = mfspr64(val_p, chud_ppc_dsisr); break; }
655 if(spr==chud_ppc_sdr1) { retval = mfspr64(val_p, chud_ppc_sdr1); break; }
656 if(spr==chud_ppc_sprg0) { retval = mfspr64(val_p, chud_ppc_sprg0); break; }
657 if(spr==chud_ppc_sprg1) { retval = mfspr64(val_p, chud_ppc_sprg1); break; }
658 if(spr==chud_ppc_sprg2) { retval = mfspr64(val_p, chud_ppc_sprg2); break; }
659 if(spr==chud_ppc_sprg3) { retval = mfspr64(val_p, chud_ppc_sprg3); break; }
660 if(spr==chud_ppc_dabr) { retval = mfspr64(val_p, chud_ppc_dabr); break; }
661 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
662 struct ppc_thread_state64 state;
663 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
664 kern_return_t kr;
665 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
666 if(KERN_SUCCESS==kr) {
667 *val_p = state.srr1;
668 } else {
669 retval = KERN_FAILURE;
670 }
671 break;
672 }
673
674 /* PPC SPRs - 64-bit implementations */
675 if(spr==chud_ppc64_asr) { retval = mfspr64(val_p, chud_ppc64_asr); break; }
676 if(spr==chud_ppc64_accr) { retval = mfspr64(val_p, chud_ppc64_accr); break; }
677
678 /* Implementation Specific SPRs */
679 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
680 if(spr==chud_970_hid0) { retval = mfspr64(val_p, chud_970_hid0); break; }
681 if(spr==chud_970_hid1) { retval = mfspr64(val_p, chud_970_hid1); break; }
682 if(spr==chud_970_hid4) { retval = mfspr64(val_p, chud_970_hid4); break; }
683 if(spr==chud_970_hid5) { retval = mfspr64(val_p, chud_970_hid5); break; }
684 if(spr==chud_970_mmcr0) { retval = mfspr64(val_p, chud_970_mmcr0); break; }
685 if(spr==chud_970_mmcr1) { retval = mfspr64(val_p, chud_970_mmcr1); break; }
686 if(spr==chud_970_mmcra) { retval = mfspr64(val_p, chud_970_mmcra); break; }
687 if(spr==chud_970_siar) { retval = mfspr64(val_p, chud_970_siar); break; }
688 if(spr==chud_970_sdar) { retval = mfspr64(val_p, chud_970_sdar); break; }
689 if(spr==chud_970_imc) { retval = mfspr64(val_p, chud_970_imc); break; }
690 if(spr==chud_970_rmor) { retval = mfspr64(val_p, chud_970_rmor); break; }
691 if(spr==chud_970_hrmor) { retval = mfspr64(val_p, chud_970_hrmor); break; }
692 if(spr==chud_970_hior) { retval = mfspr64(val_p, chud_970_hior); break; }
693 if(spr==chud_970_lpidr) { retval = mfspr64(val_p, chud_970_lpidr); break; }
694 if(spr==chud_970_lpcr) { retval = mfspr64(val_p, chud_970_lpcr); break; }
695 if(spr==chud_970_dabrx) { retval = mfspr64(val_p, chud_970_dabrx); break; }
696 if(spr==chud_970_hsprg0) { retval = mfspr64(val_p, chud_970_hsprg0); break; }
697 if(spr==chud_970_hsprg1) { retval = mfspr64(val_p, chud_970_hsprg1); break; }
698 if(spr==chud_970_hsrr0) { retval = mfspr64(val_p, chud_970_hsrr0); break; }
699 if(spr==chud_970_hsrr1) { retval = mfspr64(val_p, chud_970_hsrr1); break; }
700 if(spr==chud_970_hdec) { retval = mfspr64(val_p, chud_970_hdec); break; }
701 if(spr==chud_970_trig0) { retval = mfspr64(val_p, chud_970_trig0); break; }
702 if(spr==chud_970_trig1) { retval = mfspr64(val_p, chud_970_trig1); break; }
703 if(spr==chud_970_trig2) { retval = mfspr64(val_p, chud_970_trig2); break; }
704 if(spr==chud_970_scomc) { retval = mfspr64(val_p, chud_970_scomc); break; }
705 if(spr==chud_970_scomd) { retval = mfspr64(val_p, chud_970_scomd); break; }
706 }
707
708 /* we only get here if none of the above cases qualify */
709 *val_p = 0xFFFFFFFFFFFFFFFFLL;
710 retval = KERN_INVALID_ARGUMENT;
711 } while(0);
712
713 chudxnu_set_interrupts_enabled(oldlevel); /* enable interrupts */
714
715 if(cpu>=0) { // cpu<0 means don't bind
716 chudxnu_unbind_thread(current_thread());
717 }
718
719 return retval;
720 }
721
722 __private_extern__
723 kern_return_t chudxnu_write_spr(int cpu, int spr, uint32_t val)
724 {
725 kern_return_t retval = KERN_SUCCESS;
726 boolean_t oldlevel;
727
728 /* bind to requested CPU */
729 if(cpu>=0) { // cpu<0 means don't bind
730 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
731 return KERN_INVALID_ARGUMENT;
732 }
733 }
734
735 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
736
737 do {
738 /* PPC SPRs - 32-bit and 64-bit implementations */
739 if(spr==chud_ppc_srr0) { mtspr(chud_ppc_srr0, val); break; }
740 if(spr==chud_ppc_srr1) { mtspr(chud_ppc_srr1, val); break; }
741 if(spr==chud_ppc_dsisr) { mtspr(chud_ppc_dsisr, val); break; }
742 if(spr==chud_ppc_dar) { mtspr(chud_ppc_dar, val); break; }
743 if(spr==chud_ppc_dec) { mtspr(chud_ppc_dec, val); break; }
744 if(spr==chud_ppc_sdr1) { mtspr(chud_ppc_sdr1, val); break; }
745 if(spr==chud_ppc_sprg0) { mtspr(chud_ppc_sprg0, val); break; }
746 if(spr==chud_ppc_sprg1) { mtspr(chud_ppc_sprg1, val); break; }
747 if(spr==chud_ppc_sprg2) { mtspr(chud_ppc_sprg2, val); break; }
748 if(spr==chud_ppc_sprg3) { mtspr(chud_ppc_sprg3, val); break; }
749 if(spr==chud_ppc_ear) { mtspr(chud_ppc_ear, val); break; }
750 if(spr==chud_ppc_tbl) { mtspr(284, val); break; } /* timebase consists of read registers and write registers */
751 if(spr==chud_ppc_tbu) { mtspr(285, val); break; }
752 if(spr==chud_ppc_pvr) { mtspr(chud_ppc_pvr, val); break; }
753 if(spr==chud_ppc_ibat0u) { mtspr(chud_ppc_ibat0u, val); break; }
754 if(spr==chud_ppc_ibat0l) { mtspr(chud_ppc_ibat0l, val); break; }
755 if(spr==chud_ppc_ibat1u) { mtspr(chud_ppc_ibat1u, val); break; }
756 if(spr==chud_ppc_ibat1l) { mtspr(chud_ppc_ibat1l, val); break; }
757 if(spr==chud_ppc_ibat2u) { mtspr(chud_ppc_ibat2u, val); break; }
758 if(spr==chud_ppc_ibat2l) { mtspr(chud_ppc_ibat2l, val); break; }
759 if(spr==chud_ppc_ibat3u) { mtspr(chud_ppc_ibat3u, val); break; }
760 if(spr==chud_ppc_ibat3l) { mtspr(chud_ppc_ibat3l, val); break; }
761 if(spr==chud_ppc_dbat0u) { mtspr(chud_ppc_dbat0u, val); break; }
762 if(spr==chud_ppc_dbat0l) { mtspr(chud_ppc_dbat0l, val); break; }
763 if(spr==chud_ppc_dbat1u) { mtspr(chud_ppc_dbat1u, val); break; }
764 if(spr==chud_ppc_dbat1l) { mtspr(chud_ppc_dbat1l, val); break; }
765 if(spr==chud_ppc_dbat2u) { mtspr(chud_ppc_dbat2u, val); break; }
766 if(spr==chud_ppc_dbat2l) { mtspr(chud_ppc_dbat2l, val); break; }
767 if(spr==chud_ppc_dbat3u) { mtspr(chud_ppc_dbat3u, val); break; }
768 if(spr==chud_ppc_dbat3l) { mtspr(chud_ppc_dbat3l, val); break; }
769 if(spr==chud_ppc_dabr) { mtspr(chud_ppc_dabr, val); break; }
770 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
771 struct ppc_thread_state64 state;
772 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
773 kern_return_t kr;
774 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
775 if(KERN_SUCCESS==kr) {
776 state.srr1 = val;
777 kr = chudxnu_thread_set_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, count, TRUE /* user only */);
778 if(KERN_SUCCESS!=kr) {
779 retval = KERN_FAILURE;
780 }
781 } else {
782 retval = KERN_FAILURE;
783 }
784 break;
785 }
786
787 /* PPC SPRs - 32-bit implementations */
788 if(spr==chud_ppc32_sr0) { mtsr(0, val); break; }
789 if(spr==chud_ppc32_sr1) { mtsr(1, val); break; }
790 if(spr==chud_ppc32_sr2) { mtsr(2, val); break; }
791 if(spr==chud_ppc32_sr3) { mtsr(3, val); break; }
792 if(spr==chud_ppc32_sr4) { mtsr(4, val); break; }
793 if(spr==chud_ppc32_sr5) { mtsr(5, val); break; }
794 if(spr==chud_ppc32_sr6) { mtsr(6, val); break; }
795 if(spr==chud_ppc32_sr7) { mtsr(7, val); break; }
796 if(spr==chud_ppc32_sr8) { mtsr(8, val); break; }
797 if(spr==chud_ppc32_sr9) { mtsr(9, val); break; }
798 if(spr==chud_ppc32_sr10) { mtsr(10, val); break; }
799 if(spr==chud_ppc32_sr11) { mtsr(11, val); break; }
800 if(spr==chud_ppc32_sr12) { mtsr(12, val); break; }
801 if(spr==chud_ppc32_sr13) { mtsr(13, val); break; }
802 if(spr==chud_ppc32_sr14) { mtsr(14, val); break; }
803 if(spr==chud_ppc32_sr15) { mtsr(15, val); break; }
804
805 /* Implementation Specific SPRs */
806 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_750) {
807 if(spr==chud_750_mmcr0) { mtspr(chud_750_mmcr0, val); break; }
808 if(spr==chud_750_pmc1) { mtspr(chud_750_pmc1, val); break; }
809 if(spr==chud_750_pmc2) { mtspr(chud_750_pmc2, val); break; }
810 if(spr==chud_750_sia) { mtspr(chud_750_sia, val); break; }
811 if(spr==chud_750_mmcr1) { mtspr(chud_750_mmcr1, val); break; }
812 if(spr==chud_750_pmc3) { mtspr(chud_750_pmc3, val); break; }
813 if(spr==chud_750_pmc4) { mtspr(chud_750_pmc4, val); break; }
814 if(spr==chud_750_iabr) { mtspr(chud_750_iabr, val); break; }
815 if(spr==chud_750_ictc) { mtspr(chud_750_ictc, val); break; }
816 if(spr==chud_750_thrm1) { mtspr(chud_750_thrm1, val); break; }
817 if(spr==chud_750_thrm2) { mtspr(chud_750_thrm2, val); break; }
818 if(spr==chud_750_thrm3) { mtspr(chud_750_thrm3, val); break; }
819 if(spr==chud_750_l2cr) {
820 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
821 break;
822 }
823 if(spr==chud_750_hid0) {
824 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
825 break;
826 }
827 if(spr==chud_750_hid1) {
828 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
829 break;
830 }
831
832 // 750FX only
833 if(spr==chud_750fx_ibat4u) { mtspr(chud_750fx_ibat4u, val); break; }
834 if(spr==chud_750fx_ibat4l) { mtspr(chud_750fx_ibat4l, val); break; }
835 if(spr==chud_750fx_ibat5u) { mtspr(chud_750fx_ibat5u, val); break; }
836 if(spr==chud_750fx_ibat5l) { mtspr(chud_750fx_ibat5l, val); break; }
837 if(spr==chud_750fx_ibat6u) { mtspr(chud_750fx_ibat6u, val); break; }
838 if(spr==chud_750fx_ibat6l) { mtspr(chud_750fx_ibat6l, val); break; }
839 if(spr==chud_750fx_ibat7u) { mtspr(chud_750fx_ibat7u, val); break; }
840 if(spr==chud_750fx_ibat7l) { mtspr(chud_750fx_ibat7l, val); break; }
841 if(spr==chud_750fx_dbat4u) { mtspr(chud_750fx_dbat4u, val); break; }
842 if(spr==chud_750fx_dbat4l) { mtspr(chud_750fx_dbat4l, val); break; }
843 if(spr==chud_750fx_dbat5u) { mtspr(chud_750fx_dbat5u, val); break; }
844 if(spr==chud_750fx_dbat5l) { mtspr(chud_750fx_dbat5l, val); break; }
845 if(spr==chud_750fx_dbat6u) { mtspr(chud_750fx_dbat6u, val); break; }
846 if(spr==chud_750fx_dbat6l) { mtspr(chud_750fx_dbat6l, val); break; }
847 if(spr==chud_750fx_dbat7u) { mtspr(chud_750fx_dbat7u, val); break; }
848 if(spr==chud_750fx_dbat7l) { mtspr(chud_750fx_dbat7l, val); break; }
849
850 // 750FX >= DDR2.x
851 if(spr==chud_750fx_hid2) { mtspr(chud_750fx_hid2, val); break; }
852 }
853
854 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7400) {
855 if(spr==chud_7400_mmcr2) { mtspr(chud_7400_mmcr2, val); break; }
856 if(spr==chud_7400_bamr) { mtspr(chud_7400_bamr, val); break; }
857 if(spr==chud_7400_mmcr0) { mtspr(chud_7400_mmcr0, val); break; }
858 if(spr==chud_7400_pmc1) { mtspr(chud_7400_pmc1, val); break; }
859 if(spr==chud_7400_pmc2) { mtspr(chud_7400_pmc2, val); break; }
860 if(spr==chud_7400_siar) { mtspr(chud_7400_siar, val); break; }
861 if(spr==chud_7400_mmcr1) { mtspr(chud_7400_mmcr1, val); break; }
862 if(spr==chud_7400_pmc3) { mtspr(chud_7400_pmc3, val); break; }
863 if(spr==chud_7400_pmc4) { mtspr(chud_7400_pmc4, val); break; }
864 if(spr==chud_7400_iabr) { mtspr(chud_7400_iabr, val); break; }
865 if(spr==chud_7400_ictc) { mtspr(chud_7400_ictc, val); break; }
866 if(spr==chud_7400_thrm1) { mtspr(chud_7400_thrm1, val); break; }
867 if(spr==chud_7400_thrm2) { mtspr(chud_7400_thrm2, val); break; }
868 if(spr==chud_7400_thrm3) { mtspr(chud_7400_thrm3, val); break; }
869 if(spr==chud_7400_pir) { mtspr(chud_7400_pir, val); break; }
870
871 if(spr==chud_7400_l2cr) {
872 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
873 break;
874 }
875 if(spr==chud_7400_hid0) {
876 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
877 break;
878 }
879 if(spr==chud_7400_hid1) {
880 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
881 break;
882 }
883 if(spr==chud_7400_msscr0) {
884 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
885 break;
886 }
887 if(spr==chud_7400_msscr1) { /* private */
888 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
889 break;
890 }
891
892 // 7410 only
893 if(spr==chud_7410_l2pmcr) { mtspr(chud_7410_l2pmcr, val); break; }
894 }
895
896 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7450) {
897 if(spr==chud_7450_mmcr2) { mtspr(chud_7450_mmcr2, val); break; }
898 if(spr==chud_7450_pmc5) { mtspr(chud_7450_pmc5, val); break; }
899 if(spr==chud_7450_pmc6) { mtspr(chud_7450_pmc6, val); break; }
900 if(spr==chud_7450_bamr) { mtspr(chud_7450_bamr, val); break; }
901 if(spr==chud_7450_mmcr0) { mtspr(chud_7450_mmcr0, val); break; }
902 if(spr==chud_7450_pmc1) { mtspr(chud_7450_pmc1, val); break; }
903 if(spr==chud_7450_pmc2) { mtspr(chud_7450_pmc2, val); break; }
904 if(spr==chud_7450_siar) { mtspr(chud_7450_siar, val); break; }
905 if(spr==chud_7450_mmcr1) { mtspr(chud_7450_mmcr1, val); break; }
906 if(spr==chud_7450_pmc3) { mtspr(chud_7450_pmc3, val); break; }
907 if(spr==chud_7450_pmc4) { mtspr(chud_7450_pmc4, val); break; }
908 if(spr==chud_7450_tlbmiss) { mtspr(chud_7450_tlbmiss, val); break; }
909 if(spr==chud_7450_ptehi) { mtspr(chud_7450_ptehi, val); break; }
910 if(spr==chud_7450_ptelo) { mtspr(chud_7450_ptelo, val); break; }
911 if(spr==chud_7450_l3pm) { mtspr(chud_7450_l3pm, val); break; }
912 if(spr==chud_7450_iabr) { mtspr(chud_7450_iabr, val); break; }
913 if(spr==chud_7450_ldstdb) { mtspr(chud_7450_ldstdb, val); break; }
914 if(spr==chud_7450_ictc) { mtspr(chud_7450_ictc, val); break; }
915 if(spr==chud_7450_thrm1) { mtspr(chud_7450_thrm1, val); break; }
916 if(spr==chud_7450_thrm2) { mtspr(chud_7450_thrm2, val); break; }
917 if(spr==chud_7450_thrm3) { mtspr(chud_7450_thrm3, val); break; }
918 if(spr==chud_7450_pir) { mtspr(chud_7450_pir, val); break; }
919
920 if(spr==chud_7450_l2cr) {
921 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
922 break;
923 }
924
925 if(spr==chud_7450_l3cr) {
926 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
927 break;
928 }
929 if(spr==chud_7450_ldstcr) {
930 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
931 break;
932 }
933 if(spr==chud_7450_hid0) {
934 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
935 break;
936 }
937 if(spr==chud_7450_hid1) {
938 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
939 break;
940 }
941 if(spr==chud_7450_msscr0) {
942 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
943 break;
944 }
945 if(spr==chud_7450_msssr0) {
946 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
947 break;
948 }
949 if(spr==chud_7450_ictrl) {
950 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
951 break;
952 }
953
954 // 7455/7457 only
955 if(spr==chud_7455_sprg4) { mtspr(chud_7455_sprg4, val); break; }
956 if(spr==chud_7455_sprg5) { mtspr(chud_7455_sprg5, val); break; }
957 if(spr==chud_7455_sprg6) { mtspr(chud_7455_sprg6, val); break; }
958 if(spr==chud_7455_sprg7) { mtspr(chud_7455_sprg7, val); break; }
959 if(spr==chud_7455_ibat4u) { mtspr(chud_7455_ibat4u, val); break; }
960 if(spr==chud_7455_ibat4l) { mtspr(chud_7455_ibat4l, val); break; }
961 if(spr==chud_7455_ibat5u) { mtspr(chud_7455_ibat5u, val); break; }
962 if(spr==chud_7455_ibat5l) { mtspr(chud_7455_ibat5l, val); break; }
963 if(spr==chud_7455_ibat6u) { mtspr(chud_7455_ibat6u, val); break; }
964 if(spr==chud_7455_ibat6l) { mtspr(chud_7455_ibat6l, val); break; }
965 if(spr==chud_7455_ibat7u) { mtspr(chud_7455_ibat7u, val); break; }
966 if(spr==chud_7455_ibat7l) { mtspr(chud_7455_ibat7l, val); break; }
967 if(spr==chud_7455_dbat4u) { mtspr(chud_7455_dbat4u, val); break; }
968 if(spr==chud_7455_dbat4l) { mtspr(chud_7455_dbat4l, val); break; }
969 if(spr==chud_7455_dbat5u) { mtspr(chud_7455_dbat5u, val); break; }
970 if(spr==chud_7455_dbat5l) { mtspr(chud_7455_dbat5l, val); break; }
971 if(spr==chud_7455_dbat6u) { mtspr(chud_7455_dbat6u, val); break; }
972 if(spr==chud_7455_dbat6l) { mtspr(chud_7455_dbat6l, val); break; }
973 if(spr==chud_7455_dbat7u) { mtspr(chud_7455_dbat7u, val); break; }
974 if(spr==chud_7455_dbat7l) { mtspr(chud_7455_dbat7l, val); break; }
975 }
976
977 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
978 if(spr==chud_970_pir) { mtspr(chud_970_pir, val); break; }
979 if(spr==chud_970_pmc1) { mtspr(chud_970_pmc1, val); break; }
980 if(spr==chud_970_pmc2) { mtspr(chud_970_pmc2, val); break; }
981 if(spr==chud_970_pmc3) { mtspr(chud_970_pmc3, val); break; }
982 if(spr==chud_970_pmc4) { mtspr(chud_970_pmc4, val); break; }
983 if(spr==chud_970_pmc5) { mtspr(chud_970_pmc5, val); break; }
984 if(spr==chud_970_pmc6) { mtspr(chud_970_pmc6, val); break; }
985 if(spr==chud_970_pmc7) { mtspr(chud_970_pmc7, val); break; }
986 if(spr==chud_970_pmc8) { mtspr(chud_970_pmc8, val); break; }
987 if(spr==chud_970_hdec) { mtspr(chud_970_hdec, val); break; }
988 }
989
990 /* we only get here if none of the above cases qualify */
991 retval = KERN_INVALID_ARGUMENT;
992 } while(0);
993
994 chudxnu_set_interrupts_enabled(oldlevel); /* re-enable interrupts */
995
996 if(cpu>=0) { // cpu<0 means don't bind
997 chudxnu_unbind_thread(current_thread());
998 }
999
1000 return retval;
1001 }
1002
1003 __private_extern__
1004 kern_return_t chudxnu_write_spr64(int cpu, int spr, uint64_t val)
1005 {
1006 kern_return_t retval = KERN_SUCCESS;
1007 boolean_t oldlevel;
1008 uint64_t *val_p = &val;
1009
1010 /* bind to requested CPU */
1011 if(cpu>=0) { // cpu<0 means don't bind
1012 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
1013 return KERN_INVALID_ARGUMENT;
1014 }
1015 }
1016
1017 oldlevel = ml_set_interrupts_enabled(FALSE); /* disable interrupts */
1018
1019 do {
1020 /* PPC SPRs - 32-bit and 64-bit implementations */
1021 if(spr==chud_ppc_srr0) { retval = mtspr64(chud_ppc_srr0, val_p); break; }
1022 if(spr==chud_ppc_srr1) { retval = mtspr64(chud_ppc_srr1, val_p); break; }
1023 if(spr==chud_ppc_dar) { retval = mtspr64(chud_ppc_dar, val_p); break; }
1024 if(spr==chud_ppc_dsisr) { retval = mtspr64(chud_ppc_dsisr, val_p); break; }
1025 if(spr==chud_ppc_sdr1) { retval = mtspr64(chud_ppc_sdr1, val_p); break; }
1026 if(spr==chud_ppc_sprg0) { retval = mtspr64(chud_ppc_sprg0, val_p); break; }
1027 if(spr==chud_ppc_sprg1) { retval = mtspr64(chud_ppc_sprg1, val_p); break; }
1028 if(spr==chud_ppc_sprg2) { retval = mtspr64(chud_ppc_sprg2, val_p); break; }
1029 if(spr==chud_ppc_sprg3) { retval = mtspr64(chud_ppc_sprg3, val_p); break; }
1030 if(spr==chud_ppc_dabr) { retval = mtspr64(chud_ppc_dabr, val_p); break; }
1031 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
1032 struct ppc_thread_state64 state;
1033 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
1034 kern_return_t kr;
1035 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
1036 if(KERN_SUCCESS==kr) {
1037 state.srr1 = val;
1038 kr = chudxnu_thread_set_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, count, TRUE /* user only */);
1039 if(KERN_SUCCESS!=kr) {
1040 retval = KERN_FAILURE;
1041 }
1042 } else {
1043 retval = KERN_FAILURE;
1044 }
1045 break;
1046 }
1047
1048 /* PPC SPRs - 64-bit implementations */
1049 if(spr==chud_ppc64_asr) { retval = mtspr64(chud_ppc64_asr, val_p); break; }
1050 if(spr==chud_ppc64_accr) { retval = mtspr64(chud_ppc64_accr, val_p); break; }
1051 if(spr==chud_ppc64_ctrl) { retval = mtspr64(chud_ppc64_ctrl, val_p); break; }
1052
1053 /* Implementation Specific SPRs */
1054 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
1055 if(spr==chud_970_hid0) { retval = mtspr64(chud_970_hid0, val_p); break; }
1056 if(spr==chud_970_hid1) { retval = mtspr64(chud_970_hid1, val_p); break; }
1057 if(spr==chud_970_hid4) { retval = mtspr64(chud_970_hid4, val_p); break; }
1058 if(spr==chud_970_hid5) { retval = mtspr64(chud_970_hid5, val_p); break; }
1059 if(spr==chud_970_mmcr0) { retval = mtspr64(chud_970_mmcr0, val_p); break; }
1060 if(spr==chud_970_mmcr1) { retval = mtspr64(chud_970_mmcr1, val_p); break; }
1061 if(spr==chud_970_mmcra) { retval = mtspr64(chud_970_mmcra, val_p); break; }
1062 if(spr==chud_970_siar) { retval = mtspr64(chud_970_siar, val_p); break; }
1063 if(spr==chud_970_sdar) { retval = mtspr64(chud_970_sdar, val_p); break; }
1064 if(spr==chud_970_imc) { retval = mtspr64(chud_970_imc, val_p); break; }
1065
1066 if(spr==chud_970_rmor) { retval = mtspr64(chud_970_rmor, val_p); break; }
1067 if(spr==chud_970_hrmor) { retval = mtspr64(chud_970_hrmor, val_p); break; }
1068 if(spr==chud_970_hior) { retval = mtspr64(chud_970_hior, val_p); break; }
1069 if(spr==chud_970_lpidr) { retval = mtspr64(chud_970_lpidr, val_p); break; }
1070 if(spr==chud_970_lpcr) { retval = mtspr64(chud_970_lpcr, val_p); break; }
1071 if(spr==chud_970_dabrx) { retval = mtspr64(chud_970_dabrx, val_p); break; }
1072
1073 if(spr==chud_970_hsprg0) { retval = mtspr64(chud_970_hsprg0, val_p); break; }
1074 if(spr==chud_970_hsprg1) { retval = mtspr64(chud_970_hsprg1, val_p); break; }
1075 if(spr==chud_970_hsrr0) { retval = mtspr64(chud_970_hsrr0, val_p); break; }
1076 if(spr==chud_970_hsrr1) { retval = mtspr64(chud_970_hsrr1, val_p); break; }
1077 if(spr==chud_970_hdec) { retval = mtspr64(chud_970_hdec, val_p); break; }
1078 if(spr==chud_970_trig0) { retval = mtspr64(chud_970_trig0, val_p); break; }
1079 if(spr==chud_970_trig1) { retval = mtspr64(chud_970_trig1, val_p); break; }
1080 if(spr==chud_970_trig2) { retval = mtspr64(chud_970_trig2, val_p); break; }
1081 if(spr==chud_970_scomc) { retval = mtspr64(chud_970_scomc, val_p); break; }
1082 if(spr==chud_970_scomd) { retval = mtspr64(chud_970_scomd, val_p); break; }
1083
1084 if(spr==chud_970_hid0) {
1085 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1086 break;
1087 }
1088
1089 if(spr==chud_970_hid1) {
1090 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1091 break;
1092 }
1093
1094 if(spr==chud_970_hid4) {
1095 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1096 break;
1097 }
1098
1099 if(spr==chud_970_hid5) {
1100 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1101 break;
1102 }
1103
1104 }
1105
1106 /* we only get here if none of the above cases qualify */
1107 retval = KERN_INVALID_ARGUMENT;
1108 } while(0);
1109
1110 chudxnu_set_interrupts_enabled(oldlevel); /* re-enable interrupts */
1111
1112 if(cpu>=0) { // cpu<0 means don't bind
1113 chudxnu_unbind_thread(current_thread());
1114 }
1115
1116 return retval;
1117 }
1118
1119 #pragma mark **** cache flush ****
1120
1121 __private_extern__
1122 void chudxnu_flush_caches(void)
1123 {
1124 cacheInit();
1125 }
1126
1127 __private_extern__
1128 void chudxnu_enable_caches(boolean_t enable)
1129 {
1130 if(!enable) {
1131 cacheInit();
1132 cacheDisable();
1133 } else {
1134 cacheInit();
1135 }
1136 }
1137
1138 #pragma mark **** perfmon facility ****
1139
1140 __private_extern__
1141 kern_return_t chudxnu_perfmon_acquire_facility(task_t task)
1142 {
1143 return perfmon_acquire_facility(task);
1144 }
1145
1146 __private_extern__
1147 kern_return_t chudxnu_perfmon_release_facility(task_t task)
1148 {
1149 return perfmon_release_facility(task);
1150 }
1151
1152 #pragma mark **** branch trace buffer ****
1153
1154 extern int pc_trace_buf[1024];
1155
1156 __private_extern__
1157 uint32_t * chudxnu_get_branch_trace_buffer(uint32_t *entries)
1158 {
1159 if(entries) {
1160 *entries = sizeof(pc_trace_buf)/sizeof(int);
1161 }
1162 return pc_trace_buf;
1163 }
1164
1165 #pragma mark **** interrupts enable/disable ****
1166
1167 __private_extern__
1168 boolean_t chudxnu_get_interrupts_enabled(void)
1169 {
1170 return ml_get_interrupts_enabled();
1171 }
1172
1173 __private_extern__
1174 boolean_t chudxnu_set_interrupts_enabled(boolean_t enable)
1175 {
1176 return ml_set_interrupts_enabled(enable);
1177 }
1178
1179 __private_extern__
1180 boolean_t chudxnu_at_interrupt_context(void)
1181 {
1182 return ml_at_interrupt_context();
1183 }
1184
1185 __private_extern__
1186 void chudxnu_cause_interrupt(void)
1187 {
1188 ml_cause_interrupt();
1189 }
1190
1191 #pragma mark **** rupt counters ****
1192
1193 __private_extern__
1194 kern_return_t chudxnu_get_cpu_rupt_counters(int cpu, rupt_counters_t *rupts)
1195 {
1196 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
1197 return KERN_FAILURE;
1198 }
1199
1200 if(rupts) {
1201 boolean_t oldlevel = ml_set_interrupts_enabled(FALSE);
1202 struct per_proc_info *per_proc;
1203
1204 per_proc = PerProcTable[cpu].ppe_vaddr;
1205 rupts->hwResets = per_proc->hwCtr.hwResets;
1206 rupts->hwMachineChecks = per_proc->hwCtr.hwMachineChecks;
1207 rupts->hwDSIs = per_proc->hwCtr.hwDSIs;
1208 rupts->hwISIs = per_proc->hwCtr.hwISIs;
1209 rupts->hwExternals = per_proc->hwCtr.hwExternals;
1210 rupts->hwAlignments = per_proc->hwCtr.hwAlignments;
1211 rupts->hwPrograms = per_proc->hwCtr.hwPrograms;
1212 rupts->hwFloatPointUnavailable = per_proc->hwCtr.hwFloatPointUnavailable;
1213 rupts->hwDecrementers = per_proc->hwCtr.hwDecrementers;
1214 rupts->hwIOErrors = per_proc->hwCtr.hwIOErrors;
1215 rupts->hwSystemCalls = per_proc->hwCtr.hwSystemCalls;
1216 rupts->hwTraces = per_proc->hwCtr.hwTraces;
1217 rupts->hwFloatingPointAssists = per_proc->hwCtr.hwFloatingPointAssists;
1218 rupts->hwPerformanceMonitors = per_proc->hwCtr.hwPerformanceMonitors;
1219 rupts->hwAltivecs = per_proc->hwCtr.hwAltivecs;
1220 rupts->hwInstBreakpoints = per_proc->hwCtr.hwInstBreakpoints;
1221 rupts->hwSystemManagements = per_proc->hwCtr.hwSystemManagements;
1222 rupts->hwAltivecAssists = per_proc->hwCtr.hwAltivecAssists;
1223 rupts->hwThermal = per_proc->hwCtr.hwThermal;
1224 rupts->hwSoftPatches = per_proc->hwCtr.hwSoftPatches;
1225 rupts->hwMaintenances = per_proc->hwCtr.hwMaintenances;
1226 rupts->hwInstrumentations = per_proc->hwCtr.hwInstrumentations;
1227
1228 ml_set_interrupts_enabled(oldlevel);
1229 return KERN_SUCCESS;
1230 } else {
1231 return KERN_FAILURE;
1232 }
1233 }
1234
1235 __private_extern__
1236 kern_return_t chudxnu_clear_cpu_rupt_counters(int cpu)
1237 {
1238 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
1239 return KERN_FAILURE;
1240 }
1241
1242 bzero((char *)&(PerProcTable[cpu].ppe_vaddr->hwCtr), sizeof(struct hwCtrs));
1243 return KERN_SUCCESS;
1244 }
1245
1246 #pragma mark **** alignment exceptions ****
1247
1248 __private_extern__
1249 kern_return_t chudxnu_passup_alignment_exceptions(boolean_t enable)
1250 {
1251 if(enable) {
1252 dgWork.dgFlags |= enaNotifyEM;
1253 } else {
1254 dgWork.dgFlags &= ~enaNotifyEM;
1255 }
1256 return KERN_SUCCESS;
1257 }
1258
1259 #pragma mark **** scom ****
1260 kern_return_t chudxnu_scom_read(uint32_t reg, uint64_t *data)
1261 {
1262 ml_scom_read(reg, data);
1263 return KERN_SUCCESS;
1264 }
1265
1266 kern_return_t chudxnu_scom_write(uint32_t reg, uint64_t data)
1267 {
1268 ml_scom_write(reg, data);
1269 return KERN_SUCCESS;
1270 }
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