osfmk/i386/perfmon.h

   1 /*
   2  * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_OSREFERENCE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License.  The rights granted to you under the
  10  * License may not be used to create, or enable the creation or
  11  * redistribution of, unlawful or unlicensed copies of an Apple operating
  12  * system, or to circumvent, violate, or enable the circumvention or
  13  * violation of, any terms of an Apple operating system software license
  14  * agreement.
  15  *
  16  * Please obtain a copy of the License at
  17  * http://www.opensource.apple.com/apsl/ and read it before using this
  18  * file.
  19  *
  20  * The Original Code and all software distributed under the License are
  21  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  22  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  23  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  25  * Please see the License for the specific language governing rights and
  26  * limitations under the License.
  27  *
  28  * @APPLE_LICENSE_OSREFERENCE_HEADER_END@
  29  */
  30 #ifndef _I386_PERFMON_H_
  31 #define _I386_PERFMON_H_
  32
  33 #include <i386/proc_reg.h>
  34
  35 /*
  36  * Handy macros for bit/bitfield definition and manipulations:
  37  */
  38 #define bit(n)                  (1ULL << (n))
  39 #define field(n,m)              ((bit((m)+1)-1) & ~(bit(n)-1))
  40 #define field_nbit(fld)         (ffs(fld)-1)
  41 #define field_select(fld,x)     ((x) & (fld))
  42 #define field_clear(fld,x)      ((x) & ~(fld))
  43 #define field_unshift(fld,x)    ((x) >> field_nbit(fld))
  44 #define field_shift(fld,x)      ((x) << field_nbit(fld))
  45 #define field_get(fld,x)        (field_unshift(fld,field_select(fld,x)))
  46 #define field_set(fld,x,val)    (field_clear(fld,x) | field_shift(fld,val))
  47
  48 #define PERFMON_AVAILABLE       bit(7)
  49 #define BTS_UNAVAILABLE         bit(11)
  50
  51 static inline boolean_t
  52 pmc_is_available(void)
  53 {
  54         uint32_t        lo;
  55         uint32_t        hi;
  56         int             ret;
  57
  58         ret = rdmsr_carefully(MSR_IA32_MISC_ENABLE, &lo, &hi);
  59
  60         return (ret == 0) && ((lo & PERFMON_AVAILABLE) != 0);
  61 }
  62
  63 /*
  64  * Counter layout:
  65  */
  66 #define PMC_COUNTER_COUNTER             field(0,39)
  67 #define PMC_COUNTER_RESERVED            field(40,64)
  68 #define PMC_COUNTER_MAX                 ((uint64_t) PMC_COUNTER_COUNTER)
  69 typedef struct {
  70         uint64_t        counter         : 40;
  71         uint64_t        reserved        : 24;
  72 } pmc_counter_t;
  73 #define PMC_COUNTER_ZERO { 0, 0 }
  74
  75
  76 /*
  77  * There are 2 basic flavors of PMCsL: P6 and P4/Xeon:
  78  */
  79 typedef enum {
  80         pmc_none,
  81         pmc_P6,
  82         pmc_P4_Xeon,
  83         pmc_unknown
  84 } pmc_machine_t;
  85
  86 /*
  87  * P6 MSRs...
  88  */
  89 #define MSR_P6_COUNTER_ADDR(n)  (0x0c1 + (n))
  90 #define MSR_P6_PES_ADDR(n)      (0x186 + (n))
  91
  92 typedef struct {
  93         uint64_t        event_select    : 8;
  94         uint64_t        umask           : 8;
  95         uint64_t        usr             : 1;
  96         uint64_t        os              : 1;
  97         uint64_t        e               : 1;
  98         uint64_t        pc              : 1;
  99         uint64_t        apic_int        : 1;
 100         uint64_t        reserved1       : 1;
 101         uint64_t        en              : 1;
 102         uint64_t        inv             : 1;
 103         uint64_t        cmask           : 8;
 104 } pmc_evtsel_t;
 105 #define PMC_EVTSEL_ZERO ((pmc_evtsel_t){ 0,0,0,0,0,0,0,0,0,0,0 })
 106
 107 #define MSR_P6_PERFCTR0 0
 108 #define MSR_P6_PERFCTR1 1
 109
 110 /*
 111  * P4/Xeon MSRs...
 112  */
 113 #define MSR_COUNTER_ADDR(n)     (0x300 + (n))
 114 #define MSR_CCCR_ADDR(n)        (0x360 + (n))
 115
 116 typedef enum {
 117         MSR_BPU_COUNTER0        = 0,
 118         MSR_BPU_COUNTER1        = 1,
 119                 #define MSR_BSU_ESCR0   7
 120                 #define MSR_FSB_ESCR0   6
 121                 #define MSR_MOB_ESCR0   2
 122                 #define MSR_PMH_ESCR0   4
 123                 #define MSR_BPU_ESCR0   0
 124                 #define MSR_IS_ESCR0    1
 125                 #define MSR_ITLB_ESCR0  3
 126                 #define MSR_IX_ESCR0    5
 127         MSR_BPU_COUNTER2        = 2,
 128         MSR_BPU_COUNTER3        = 3,
 129                 #define MSR_BSU_ESCR1   7
 130                 #define MSR_FSB_ESCR1   6
 131                 #define MSR_MOB_ESCR1   2
 132                 #define MSR_PMH_ESCR1   4
 133                 #define MSR_BPU_ESCR1   0
 134                 #define MSR_IS_ESCR1    1
 135                 #define MSR_ITLB_ESCR1  3
 136                 #define MSR_IX_ESCR1    5
 137         MSR_MS_COUNTER0         = 4,
 138         MSR_MS_COUNTER1         = 5,
 139                 #define MSR_MS_ESCR0    0
 140                 #define MSR_TBPU_ESCR0  2
 141                 #define MSR_TC_ESCR0    1
 142         MSR_MS_COUNTER2         = 6,
 143         MSR_MS_COUNTER3         = 7,
 144                 #define MSR_MS_ESCR1    0
 145                 #define MSR_TBPU_ESCR1  2
 146                 #define MSR_TC_ESCR1    1
 147         MSR_FLAME_COUNTER0      = 8,
 148         MSR_FLAME_COUNTER1      = 9,
 149                 #define MSR_FIRM_ESCR0  1
 150                 #define MSR_FLAME_ESCR0 0
 151                 #define MSR_DAC_ESCR0   5
 152                 #define MSR_SAT_ESCR0   2
 153                 #define MSR_U2L_ESCR0   3
 154         MSR_FLAME_COUNTER2      = 10,
 155         MSR_FLAME_COUNTER3      = 11,
 156                 #define MSR_FIRM_ESCR1  1
 157                 #define MSR_FLAME_ESCR1 0
 158                 #define MSR_DAC_ESCR1   5
 159                 #define MSR_SAT_ESCR1   2
 160                 #define MSR_U2L_ESCR1   3
 161         MSR_IQ_COUNTER0         = 12,
 162         MSR_IQ_COUNTER1         = 13,
 163         MSR_IQ_COUNTER4         = 16,
 164                 #define MSR_CRU_ESCR0   4
 165                 #define MSR_CRU_ESCR2   5
 166                 #define MSR_CRU_ESCR4   6
 167                 #define MSR_IQ_ESCR0    0
 168                 #define MSR_RAT_ESCR0   2
 169                 #define MSR_SSU_ESCR0   3
 170                 #define MSR_AFL_ESCR0   1
 171         MSR_IQ_COUNTER2         = 14,
 172         MSR_IQ_COUNTER3         = 15,
 173         MSR_IQ_COUNTER5         = 17,
 174                 #define MSR_CRU_ESCR1   4
 175                 #define MSR_CRU_ESCR3   5
 176                 #define MSR_CRU_ESCR5   6
 177                 #define MSR_IQ_ESCR1    0
 178                 #define MSR_RAT_ESCR1   2
 179                 #define MSR_AFL_ESCR1   1
 180 } pmc_id_t;
 181
 182 typedef int pmc_escr_id_t;
 183 #define PMC_ESID_MAX                    7
 184
 185 /*
 186  * ESCR MSR layout:
 187  */
 188 #define PMC_ECSR_NOHTT_RESERVED         field(0,1)
 189 #define PMC_ECSR_T0_USR                 bit(0)
 190 #define PMC_ECSR_T0_OS                  bit(1)
 191 #define PMC_ECSR_T1_USR                 bit(2)
 192 #define PMC_ECSR_T1_OS                  bit(3)
 193 #define PMC_ECSR_USR                    bit(2)
 194 #define PMC_ECSR_OS                     bit(3)
 195 #define PMC_ECSR_TAG_ENABLE             bit(4)
 196 #define PMC_ECSR_TAG_VALUE              field(5,8)
 197 #define PMC_ECSR_EVENT_MASK             field(9,24)
 198 #define PMC_ECSR_EVENT_SELECT           field(25,30)
 199 #define PMC_ECSR_RESERVED2              field(30,64)
 200 typedef struct {
 201         uint64_t        reserved1       : 2;
 202         uint64_t        usr             : 1;
 203         uint64_t        os              : 1;
 204         uint64_t        tag_enable      : 1;
 205         uint64_t        tag_value       : 4;
 206         uint64_t        event_mask      : 16;
 207         uint64_t        event_select    : 6;
 208         uint64_t        reserved2       : 33;
 209 } pmc_escr_nohtt_t;
 210 typedef struct {
 211         uint64_t        t0_usr          : 1;
 212         uint64_t        t0_os           : 1;
 213         uint64_t        t1_usr          : 1;
 214         uint64_t        t1_os           : 1;
 215         uint64_t        tag_enable      : 1;
 216         uint64_t        tag_value       : 4;
 217         uint64_t        event_mask      : 16;
 218         uint64_t        event_select    : 6;
 219         uint64_t        reserved2       : 33;
 220 } pmc_escr_htt_t;
 221 typedef union {
 222         pmc_escr_nohtt_t        u_nohtt;
 223         pmc_escr_htt_t          u_htt;
 224         uint64_t                u_u64;
 225 } pmc_escr_t;
 226 #define PMC_ESCR_ZERO   { .u_u64 = 0ULL }
 227
 228 /*
 229  * CCCR MSR layout:
 230  */
 231 #define PMC_CCCR_RESERVED1              field(1,11)
 232 #define PMC_CCCR_ENABLE                 bit(12)
 233 #define PMC_CCCR_ECSR_SELECT            field(13,15)
 234 #define PMC_CCCR_RESERVED2              field(16,17)
 235 #define PMC_CCCR_HTT_ACTIVE             field(16,17)
 236 #define PMC_CCCR_COMPARE                bit(18)
 237 #define PMC_CCCR_COMPLEMENT             bit(19)
 238 #define PMC_CCCR_THRESHOLD              field(20,23)
 239 #define PMC_CCCR_EDGE                   bit(24)
 240 #define PMC_CCCR_FORCE_OVF              bit(25)
 241 #define PMC_CCCR_OVF_PMI                bit(26)
 242 #define PMC_CCCR_NOHTT_RESERVED2        field(27,29)
 243 #define PMC_CCCR_OVF_PMI_T0             bit(26)
 244 #define PMC_CCCR_OVF_PMI_T1             bit(27)
 245 #define PMC_CCCR_HTT_RESERVED2          field(28,29)
 246 #define PMC_CCCR_CASCADE                bit(30)
 247 #define PMC_CCCR_OVF                    bit(31)
 248 typedef struct {
 249         uint64_t        reserved1       : 12;
 250         uint64_t        enable          : 1;
 251         uint64_t        escr_select     : 3;
 252         uint64_t        reserved2       : 2;
 253         uint64_t        compare         : 1;
 254         uint64_t        complement      : 1;
 255         uint64_t        threshold       : 4;
 256         uint64_t        edge            : 1;
 257         uint64_t        force_ovf       : 1;
 258         uint64_t        ovf_pmi         : 1;
 259         uint64_t        reserved3       : 3;
 260         uint64_t        cascade         : 1;
 261         uint64_t        ovf             : 1;
 262         uint64_t        reserved4       : 32;
 263 } pmc_cccr_nohtt_t;
 264 typedef struct {
 265         uint64_t        reserved1       : 12;
 266         uint64_t        enable          : 1;
 267         uint64_t        escr_select     : 3;
 268         uint64_t        active_thread   : 2;
 269         uint64_t        compare         : 1;
 270         uint64_t        complement      : 1;
 271         uint64_t        threshold       : 4;
 272         uint64_t        edge            : 1;
 273         uint64_t        force_OVF       : 1;
 274         uint64_t        ovf_pmi_t0      : 1;
 275         uint64_t        ovf_pmi_t1      : 1;
 276         uint64_t        reserved3       : 2;
 277         uint64_t        cascade         : 1;
 278         uint64_t        ovf             : 1;
 279         uint64_t        reserved4       : 32;
 280 } pmc_cccr_htt_t;
 281 typedef union {
 282         pmc_cccr_nohtt_t        u_nohtt;
 283         pmc_cccr_htt_t          u_htt;
 284         uint64_t                u_u64;
 285 } pmc_cccr_t;
 286 #define PMC_CCCR_ZERO   { .u_u64 = 0ULL }
 287
 288 typedef void (pmc_ovf_func_t)(pmc_id_t id, void *state);
 289
 290 /*
 291  * In-kernel PMC access primitives:
 292  */
 293 /* Generic: */
 294 extern int pmc_init(void);
 295 extern int pmc_machine_type(pmc_machine_t *type);
 296 extern boolean_t pmc_is_reserved(pmc_id_t id);
 297 extern int pmc_reserve(pmc_id_t id);
 298 extern int pmc_free(pmc_id_t id);
 299 extern int pmc_counter_read(pmc_id_t id, pmc_counter_t *val);
 300 extern int pmc_counter_write(pmc_id_t id, pmc_counter_t *val);
 301
 302 /* P6-specific: */
 303 extern int pmc_evtsel_read(pmc_id_t id, pmc_evtsel_t *evtsel);
 304 extern int pmc_evtsel_write(pmc_id_t id, pmc_evtsel_t *evtsel);
 305
 306 /* P4/Xeon-specific: */
 307 extern int pmc_cccr_read(pmc_id_t id, pmc_cccr_t *cccr);
 308 extern int pmc_cccr_write(pmc_id_t id, pmc_cccr_t *cccr);
 309 extern int pmc_escr_read(pmc_id_t id, pmc_escr_id_t esid, pmc_escr_t *escr);
 310 extern int pmc_escr_write(pmc_id_t id, pmc_escr_id_t esid, pmc_escr_t *escr);
 311 extern int pmc_set_ovf_func(pmc_id_t id, pmc_ovf_func_t *func);
 312
 313 #endif /* _I386_PERFMON_H_ */