osfmk/ppc/commpage/bzero_128.s

   1 /*
   2  * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28
  29 #define ASSEMBLER
  30 #include <sys/appleapiopts.h>
  31 #include <ppc/asm.h>
  32 #include <machine/cpu_capabilities.h>
  33 #include <machine/commpage.h>
  34
  35         .text
  36         .align  2
  37 /*
  38  * WARNING: this code is written for 32-bit mode, and ported by the kernel if necessary
  39  * to 64-bit mode for use in the 64-bit commpage.  This "port" consists of the following
  40  * simple transformations:
  41  *      - all word compares are changed to doubleword
  42  *      - all "srwi[.]" opcodes are changed to "srdi[.]"
  43  * Nothing else is done.  For this to work, the following rules must be
  44  * carefully followed:
  45  *      - do not use carry or overflow
  46  *      - only use record mode if you are sure the results are mode-invariant
  47  *        for example, all "andi." and almost all "rlwinm." are fine
  48  *      - do not use "slwi", "slw", or "srw"
  49  * An imaginative programmer could break the porting model in other ways, but the above
  50  * are the most likely problem areas.  It is perhaps surprising how well in practice
  51  * this simple method works.
  52  */
  53
  54 // **********************
  55 // * B Z E R O _ 1 2 8  *
  56 // **********************
  57 //
  58 // For 64-bit processors with a 128-byte cache line.
  59 //
  60 // Register use:
  61 //              r0 = zero
  62 //              r3 = original ptr, not changed since memset returns it
  63 //              r4 = count of bytes to set
  64 //              r9 = working operand ptr
  65 // WARNING: We do not touch r2 and r10-r12, which some callers depend on.
  66
  67         .align  5
  68 bzero_128:                                              // void bzero(void *b, size_t len);
  69         cmplwi  cr7,r4,128              // too short for DCBZ128?
  70         li              r0,0                    // get a 0
  71         neg             r5,r3                   // start to compute #bytes to align
  72         mr              r9,r3                   // make copy of operand ptr (can't change r3)
  73         blt             cr7,Ltail               // length < 128, too short for DCBZ
  74
  75 // At least 128 bytes long, so compute alignment and #cache blocks.
  76
  77         andi.   r5,r5,0x7F              // r5 <-  #bytes to 128-byte align
  78         sub             r4,r4,r5                // adjust length
  79         srwi    r8,r4,7                 // r8 <- 128-byte chunks
  80         rlwinm  r4,r4,0,0x7F    // mask length down to remaining bytes
  81         mtctr   r8                              // set up loop count
  82         beq             Ldcbz                   // skip if already aligned (r8!=0)
  83
  84 // 128-byte align
  85
  86         mtcrf   0x01,r5                 // start to move #bytes to align to cr6 and cr7
  87         cmpwi   cr1,r8,0                // any 128-byte cache lines to 0?
  88         mtcrf   0x02,r5
  89
  90         bf              31,1f                   // byte?
  91         stb             r0,0(r9)
  92         addi    r9,r9,1
  93 1:
  94         bf              30,2f                   // halfword?
  95         sth             r0,0(r9)
  96         addi    r9,r9,2
  97 2:
  98         bf              29,3f                   // word?
  99         stw             r0,0(r9)
 100         addi    r9,r9,4
 101 3:
 102         bf              28,4f                   // doubleword?
 103         std             r0,0(r9)
 104         addi    r9,r9,8
 105 4:
 106         bf              27,5f                   // quadword?
 107         std             r0,0(r9)
 108         std             r0,8(r9)
 109         addi    r9,r9,16
 110 5:
 111         bf              26,6f                   // 32-byte chunk?
 112         std             r0,0(r9)
 113         std             r0,8(r9)
 114         std             r0,16(r9)
 115         std             r0,24(r9)
 116         addi    r9,r9,32
 117 6:
 118         bf              25,7f                   // 64-byte chunk?
 119         std             r0,0(r9)
 120         std             r0,8(r9)
 121         std             r0,16(r9)
 122         std             r0,24(r9)
 123         std             r0,32(r9)
 124         std             r0,40(r9)
 125         std             r0,48(r9)
 126         std             r0,56(r9)
 127         addi    r9,r9,64
 128 7:
 129         beq             cr1,Ltail               // no chunks to dcbz128
 130
 131 // Loop doing 128-byte version of DCBZ instruction.
 132 // NB: if the memory is cache-inhibited, the kernel will clear cr7
 133 // when it emulates the alignment exception.  Eventually, we may want
 134 // to check for this case.
 135
 136 Ldcbz:
 137         dcbz128 0,r9                    // zero another 32 bytes
 138         addi    r9,r9,128
 139         bdnz    Ldcbz
 140
 141 // Store trailing bytes.
 142 //              r0 = 0
 143 //              r4 = count
 144 //              r9 = ptr
 145
 146 Ltail:
 147         srwi.   r5,r4,4                 // r5 <- 16-byte chunks to 0
 148         mtcrf   0x01,r4                 // remaining byte count to cr7
 149         mtctr   r5
 150         beq             2f                              // skip if no 16-byte chunks
 151 1:                                                              // loop over 16-byte chunks
 152         std             r0,0(r9)
 153         std             r0,8(r9)
 154         addi    r9,r9,16
 155         bdnz    1b
 156 2:
 157         bf              28,4f                   // 8-byte chunk?
 158         std             r0,0(r9)
 159         addi    r9,r9,8
 160 4:
 161         bf              29,5f                   // word?
 162         stw             r0,0(r9)
 163         addi    r9,r9,4
 164 5:
 165         bf              30,6f                   // halfword?
 166         sth             r0,0(r9)
 167         addi    r9,r9,2
 168 6:
 169         bflr    31                              // byte?
 170         stb             r0,0(r9)
 171         blr
 172
 173         COMMPAGE_DESCRIPTOR(bzero_128,_COMM_PAGE_BZERO,kCache128+k64Bit,0, \
 174                                 kCommPageMTCRF+kCommPageBoth+kPort32to64)