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1 /*
2 * Copyright (c) 2008 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 *
31 */
32 #ifndef _I386_LAPIC_H_
33 #define _I386_LAPIC_H_
34
35 #define LAPIC_START 0xFEE00000
36 #define LAPIC_SIZE 0x00000400
37
38 #define LAPIC_ID 0x00000020
39 #define LAPIC_ID_SHIFT 24
40 #define LAPIC_ID_MASK 0xFF
41 #define LAPIC_VERSION 0x00000030
42 #define LAPIC_VERSION_MASK 0xFF
43 #define LAPIC_TPR 0x00000080
44 #define LAPIC_TPR_MASK 0xFF
45 #define LAPIC_APR 0x00000090
46 #define LAPIC_APR_MASK 0xFF
47 #define LAPIC_PPR 0x000000A0
48 #define LAPIC_PPR_MASK 0xFF
49 #define LAPIC_EOI 0x000000B0
50 #define LAPIC_REMOTE_READ 0x000000C0
51 #define LAPIC_LDR 0x000000D0
52 #define LAPIC_LDR_SHIFT 24
53 #define LAPIC_DFR 0x000000E0
54 #define LAPIC_DFR_FLAT 0xFFFFFFFF
55 #define LAPIC_DFR_CLUSTER 0x0FFFFFFF
56 #define LAPIC_DFR_SHIFT 28
57 #define LAPIC_SVR 0x000000F0
58 #define LAPIC_SVR_MASK 0x0FF
59 #define LAPIC_SVR_ENABLE 0x100
60 #define LAPIC_SVR_FOCUS_OFF 0x200
61 #define LAPIC_ISR_BASE 0x00000100
62 #define LAPIC_TMR_BASE 0x00000180
63 #define LAPIC_IRR_BASE 0x00000200
64 #define LAPIC_ERROR_STATUS 0x00000280
65 #define LAPIC_LVT_CMCI 0x000002F0
66 #define LAPIC_ICR 0x00000300
67 #define LAPIC_ICR_VECTOR_MASK 0x000FF
68 #define LAPIC_ICR_DM_MASK 0x00700
69 #define LAPIC_ICR_DM_FIXED 0x00000
70 #define LAPIC_ICR_DM_LOWEST 0x00100
71 #define LAPIC_ICR_DM_SMI 0x00200
72 #define LAPIC_ICR_DM_REMOTE 0x00300
73 #define LAPIC_ICR_DM_NMI 0x00400
74 #define LAPIC_ICR_DM_INIT 0x00500
75 #define LAPIC_ICR_DM_STARTUP 0x00600
76 #define LAPIC_ICR_DM_LOGICAL 0x00800
77 #define LAPIC_ICR_DS_PENDING 0x01000
78 #define LAPIC_ICR_LEVEL_ASSERT 0x04000
79 #define LAPIC_ICR_TRIGGER_LEVEL 0x08000
80 #define LAPIC_ICR_RR_MASK 0x30000
81 #define LAPIC_ICR_RR_INVALID 0x00000
82 #define LAPIC_ICR_RR_INPROGRESS 0x10000
83 #define LAPIC_ICR_RR_VALID 0x20000
84 #define LAPIC_ICR_DSS_MASK 0xC0000
85 #define LAPIC_ICR_DSS_DEST 0x00000
86 #define LAPIC_ICR_DSS_SELF 0x40000
87 #define LAPIC_ICR_DSS_ALL 0x80000
88 #define LAPIC_ICR_DSS_OTHERS 0xC0000
89 #define LAPIC_ICRD 0x00000310
90 #define LAPIC_ICRD_DEST_SHIFT 24
91 #define LAPIC_LVT_TIMER 0x00000320
92 #define LAPIC_LVT_THERMAL 0x00000330
93 #define LAPIC_LVT_PERFCNT 0x00000340
94 #define LAPIC_LVT_LINT0 0x00000350
95 #define LAPIC_LVT_LINT1 0x00000360
96 #define LAPIC_LVT_ERROR 0x00000370
97 #define LAPIC_LVT_VECTOR_MASK 0x000FF
98 #define LAPIC_LVT_DM_SHIFT 8
99 #define LAPIC_LVT_DM_MASK 0x00007
100 #define LAPIC_LVT_DM_FIXED 0x00000
101 #define LAPIC_LVT_DM_NMI 0x00400
102 #define LAPIC_LVT_DM_EXTINT 0x00700
103 #define LAPIC_LVT_DS_PENDING 0x01000
104 #define LAPIC_LVT_IP_PLRITY_LOW 0x02000
105 #define LAPIC_LVT_REMOTE_IRR 0x04000
106 #define LAPIC_LVT_TM_LEVEL 0x08000
107 #define LAPIC_LVT_MASKED 0x10000
108 #define LAPIC_LVT_PERIODIC 0x20000
109 #define LAPIC_TIMER_INITIAL_COUNT 0x00000380
110 #define LAPIC_TIMER_CURRENT_COUNT 0x00000390
111 #define LAPIC_TIMER_DIVIDE_CONFIG 0x000003E0
112 /* divisor encoded by bits 0,1,3 with bit 2 always 0: */
113 #define LAPIC_TIMER_DIVIDE_MASK 0x0000000F
114 #define LAPIC_TIMER_DIVIDE_2 0x00000000
115 #define LAPIC_TIMER_DIVIDE_4 0x00000001
116 #define LAPIC_TIMER_DIVIDE_8 0x00000002
117 #define LAPIC_TIMER_DIVIDE_16 0x00000003
118 #define LAPIC_TIMER_DIVIDE_32 0x00000008
119 #define LAPIC_TIMER_DIVIDE_64 0x00000009
120 #define LAPIC_TIMER_DIVIDE_128 0x0000000A
121 #define LAPIC_TIMER_DIVIDE_1 0x0000000B
122
123 #define LAPIC_ID_MAX (LAPIC_ID_MASK)
124
125 #define CPU_NUMBER(r) \
126 movl %gs:CPU_NUMBER_GS,r
127
128 #define CPU_NUMBER_FROM_LAPIC(r) \
129 movl EXT(lapic_id),r; \
130 movl 0(r),r; \
131 shrl $(LAPIC_ID_SHIFT),r; \
132 andl $(LAPIC_ID_MASK),r; \
133 movl EXT(lapic_to_cpu)(,r,4),r
134
135 #ifndef ASSEMBLER
136 #include <stdint.h>
137 #include <sys/cdefs.h>
138 #include <mach/boolean.h>
139 #include <mach/kern_return.h>
140 typedef enum {
141 periodic,
142 one_shot
143 } lapic_timer_mode_t;
144 typedef enum {
145 divide_by_1 = LAPIC_TIMER_DIVIDE_1,
146 divide_by_2 = LAPIC_TIMER_DIVIDE_2,
147 divide_by_4 = LAPIC_TIMER_DIVIDE_4,
148 divide_by_8 = LAPIC_TIMER_DIVIDE_8,
149 divide_by_16 = LAPIC_TIMER_DIVIDE_16,
150 divide_by_32 = LAPIC_TIMER_DIVIDE_32,
151 divide_by_64 = LAPIC_TIMER_DIVIDE_64,
152 divide_by_128 = LAPIC_TIMER_DIVIDE_128
153 } lapic_timer_divide_t;
154 typedef uint32_t lapic_timer_count_t;
155
156 /*
157 * By default, use high vectors to leave vector space for systems
158 * with multiple I/O APIC's. However some systems that boot with
159 * local APIC disabled will hang in SMM when vectors greater than
160 * 0x5F are used. Those systems are not expected to have I/O APIC
161 * so 16 (0x50 - 0x40) vectors for legacy PIC support is perfect.
162 */
163 #define LAPIC_DEFAULT_INTERRUPT_BASE 0xD0
164 #define LAPIC_REDUCED_INTERRUPT_BASE 0x50
165 /*
166 * Specific lapic interrupts are relative to this base
167 * in priority order from high to low:
168 */
169
170 #define LAPIC_PERFCNT_INTERRUPT 0xF
171 #define LAPIC_TIMER_INTERRUPT 0xE
172 #define LAPIC_INTERPROCESSOR_INTERRUPT 0xD
173 #define LAPIC_THERMAL_INTERRUPT 0xC
174 #define LAPIC_ERROR_INTERRUPT 0xB
175 #define LAPIC_SPURIOUS_INTERRUPT 0xA
176 #define LAPIC_CMCI_INTERRUPT 0x9
177 #define LAPIC_PMC_SW_INTERRUPT 0x8
178 #define LAPIC_PM_INTERRUPT 0x7
179
180 #define LAPIC_PMC_SWI_VECTOR (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_PMC_SW_INTERRUPT)
181
182 /* The vector field is ignored for NMI interrupts via the LAPIC
183 * or otherwise, so this is not an offset from the interrupt
184 * base.
185 */
186 #define LAPIC_NMI_INTERRUPT 0x2
187 #define LAPIC_FUNC_TABLE_SIZE (LAPIC_PERFCNT_INTERRUPT + 1)
188
189 #define LAPIC_WRITE(reg,val) \
190 *((volatile uint32_t *)(lapic_start + LAPIC_##reg)) = (val)
191 #define LAPIC_READ(reg) \
192 (*((volatile uint32_t *)(lapic_start + LAPIC_##reg)))
193 #define LAPIC_READ_OFFSET(reg,off) \
194 (*((volatile uint32_t *)(lapic_start + LAPIC_##reg + (off))))
195
196 #define LAPIC_VECTOR(src) \
197 (lapic_interrupt_base + LAPIC_##src##_INTERRUPT)
198
199 #define LAPIC_ISR_IS_SET(base,src) \
200 (LAPIC_READ_OFFSET(ISR_BASE,((base+LAPIC_##src##_INTERRUPT)/32)*0x10) \
201 & (1 <<((base + LAPIC_##src##_INTERRUPT)%32)))
202
203 extern vm_offset_t lapic_start;
204
205 extern void lapic_init(void);
206 extern void lapic_configure(void);
207 extern void lapic_shutdown(void);
208 extern void lapic_smm_restore(void);
209 extern boolean_t lapic_probe(void);
210 extern void lapic_dump(void);
211 extern int lapic_interrupt(
212 int interrupt, x86_saved_state_t *state);
213 extern void lapic_end_of_interrupt(void);
214 extern void lapic_unmask_perfcnt_interrupt(void);
215 extern void lapic_send_ipi(int cpu, int interupt);
216
217 extern int lapic_to_cpu[];
218 extern int cpu_to_lapic[];
219 extern int lapic_interrupt_base;
220 extern void lapic_cpu_map(int lapic, int cpu_num);
221 extern uint32_t ml_get_apicid(uint32_t cpu);
222 extern uint32_t ml_get_cpuid(uint32_t lapic_index);
223
224 extern void lapic_set_timer(
225 boolean_t interrupt,
226 lapic_timer_mode_t mode,
227 lapic_timer_divide_t divisor,
228 lapic_timer_count_t initial_count);
229
230 extern void lapic_get_timer(
231 lapic_timer_mode_t *mode,
232 lapic_timer_divide_t *divisor,
233 lapic_timer_count_t *initial_count,
234 lapic_timer_count_t *current_count);
235
236 typedef int (*i386_intr_func_t)(x86_saved_state_t *state);
237 extern void lapic_set_intr_func(int intr, i386_intr_func_t func);
238
239 static inline void lapic_set_timer_func(i386_intr_func_t func)
240 {
241 lapic_set_intr_func(LAPIC_VECTOR(TIMER), func);
242 }
243 static inline void lapic_set_pmi_func(i386_intr_func_t func)
244 {
245 lapic_set_intr_func(LAPIC_VECTOR(PERFCNT), func);
246 }
247 static inline void lapic_set_thermal_func(i386_intr_func_t func)
248 {
249 lapic_set_intr_func(LAPIC_VECTOR(THERMAL), func);
250 }
251 static inline void lapic_set_cmci_func(i386_intr_func_t func)
252 {
253 lapic_set_intr_func(LAPIC_VECTOR(CMCI), func);
254 }
255 static inline void lapic_set_pm_func(i386_intr_func_t func)
256 {
257 lapic_set_intr_func(LAPIC_VECTOR(PM), func);
258 }
259
260 #ifdef MP_DEBUG
261 #define LAPIC_CPU_MAP_DUMP() lapic_cpu_map_dump()
262 #define LAPIC_DUMP() lapic_dump()
263 #else
264 #define LAPIC_CPU_MAP_DUMP()
265 #define LAPIC_DUMP()
266 #endif /* MP_DEBUG */
267
268 #endif /* ASSEMBLER */
269
270 #endif /* _I386_LAPIC_H_ */
271