EXTERNAL_HEADERS/architecture/ppc/fp_regs.h

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * The contents of this file constitute Original Code as defined in and
   7  * are subject to the Apple Public Source License Version 1.1 (the
   8  * "License").  You may not use this file except in compliance with the
   9  * License.  Please obtain a copy of the License at
  10  * http://www.apple.com/publicsource and read it before using this file.
  11  *
  12  * This Original Code and all software distributed under the License are
  13  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  14  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  15  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
  17  * License for the specific language governing rights and limitations
  18  * under the License.
  19  *
  20  * @APPLE_LICENSE_HEADER_END@
  21  */
  22 /* Copyright (c) 1996 NeXT Software, Inc.  All rights reserved.
  23  *
  24  *      File:   architecture/ppc/fp_regs.h
  25  *      Author: Doug Mitchell, NeXT Software, Inc.
  26  *
  27  *      ppc floating point registers.
  28  *
  29  * HISTORY
  30  * 29-Dec-96  Umesh Vaishampayan  (umeshv@NeXT.com)
  31  *      Ported from m98k.
  32  * 05-Nov-92  Doug Mitchell at NeXT
  33  *      Created.
  34  */
  35
  36 #ifndef _ARCH_PPC_FP_REGS_H_
  37 #define _ARCH_PPC_FP_REGS_H_
  38
  39 #include <architecture/ppc/reg_help.h>
  40
  41 #if !defined(__ASSEMBLER__)
  42 /*
  43  * Floating point status and control register.
  44  *
  45  * This struct is aligned to an 8-byte boundary because 64-bit
  46  * load/store instructions (lfd/stfd) are used to access it. The
  47  * FPSCR can only be read/written through other FP registers.
  48  */
  49 typedef struct {
  50         unsigned        unused[1] __attribute__(( aligned(8) ));
  51         unsigned        fx:BIT_WIDTH(31),       // exception summary
  52                         fex:BIT_WIDTH(30),      // enabled exception summary
  53                         vx:BIT_WIDTH(29),       // invalid op exception
  54                                                 //    summary
  55                         ox:BIT_WIDTH(28),       // overflow exception
  56                         ux:BIT_WIDTH(27),       // underflow exception
  57                         zx:BIT_WIDTH(26),       // divide by zero exception
  58                         xx:BIT_WIDTH(25),       // inexact exception
  59                         vx_snan:BIT_WIDTH(24),  // not a number exception
  60                         vx_isi:BIT_WIDTH(23),   // exception
  61                         vx_idi:BIT_WIDTH(22),   // exception
  62                         vx_zdz:BIT_WIDTH(21),   // exception
  63                         vx_imz:BIT_WIDTH(20),   // exception
  64                         vx_xvc:BIT_WIDTH(19),   // exception
  65                         fr:BIT_WIDTH(18),       // fraction rounded
  66                         fi:BIT_WIDTH(17),       // fraction inexact
  67                         class:BIT_WIDTH(16),    // class descriptor
  68                         fl:BIT_WIDTH(15),       // negative
  69                         fg:BIT_WIDTH(14),       // positive
  70                         fe:BIT_WIDTH(13),       // equal or zero
  71                         fu:BIT_WIDTH(12),       // not a number
  72                         rsvd1:BIT_WIDTH(11),    // reserved
  73                         vx_soft:BIT_WIDTH(10),  // software request exception
  74                         rsvd2:BIT_WIDTH(9),     // reserved
  75                         vx_cvi:BIT_WIDTH(8),    // invalid integer convert
  76                                                 //    exception
  77                         ve:BIT_WIDTH(7),        // invalid op exception enable
  78                         oe:BIT_WIDTH(6),        // overflow exception enable
  79                         ue:BIT_WIDTH(5),        // underflow exception enable
  80                         ze:BIT_WIDTH(4),        // divide by zero exception
  81                                                 //    enable
  82                         xe:BIT_WIDTH(3),        // inexact exception enable
  83                         ni:BIT_WIDTH(2),        // non-IEEE exception enable
  84                         rn:BITS_WIDTH(1,0);     // rounding control
  85 } ppc_fp_scr_t;
  86
  87 /*
  88  * Values for fp_scr_t.rn (rounding control).
  89  */
  90 typedef enum {
  91         RN_NEAREST = 0,
  92         RN_TOWARD_ZERO = 1,
  93         RN_TOWARD_PLUS = 2,
  94         RN_TOWARD_MINUS = 3
  95 } ppc_fp_rn_t;
  96
  97 /*
  98  * ppc_fpf_t -- data types that MAY be in floating point register file
  99  * Actual data types supported is implementation dependent
 100  */
 101 typedef union {
 102         float           f;              // 32 bit IEEE single
 103         double          d;              // 64 bit IEEE double
 104
 105         /*
 106          * Insure compiler aligns struct appropriately
 107          */
 108         unsigned        x[2] __attribute__(( aligned(8) ));
 109 } ppc_fpf_t;
 110
 111 /*
 112  * Number of FP registers.
 113  */
 114 #define PPC_NFP_REGS    32
 115
 116 /*
 117  * Read/write FPSCR.
 118  * FIXME - these don't work, you need to go thru a fp register.
 119  */
 120 typedef union {
 121         double          __dbl;
 122         ppc_fp_scr_t    __scr;
 123 } __fp_un_t;
 124
 125 static __inline__ ppc_fp_scr_t
 126 get_fp_scr()
 127 {
 128         __fp_un_t       __fp_un;
 129
 130         __asm__ volatile ("mffs. %0           /* mffs */"       \
 131                 : "=f" (__fp_un.__dbl));
 132         return (__fp_un.__scr);
 133 }
 134
 135 static __inline__ void
 136 set_fp_scr(ppc_fp_scr_t fp_scr)
 137 {
 138         __fp_un_t       __fp_un;
 139
 140         __fp_un.__scr = fp_scr;
 141         __asm__ volatile ("mtfsf 0xff, %0;    /* mtfsf */ "     \
 142           : : "f" (__fp_un.__dbl));
 143 }
 144
 145 #endif /* ! __ASSEMBLER__ */
 146
 147 #endif /* _ARCH_PPC_FP_REGS_H_ */