pexpert/pexpert/ppc/protos.h

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * The contents of this file constitute Original Code as defined in and
   7  * are subject to the Apple Public Source License Version 1.1 (the
   8  * "License").  You may not use this file except in compliance with the
   9  * License.  Please obtain a copy of the License at
  10  * http://www.apple.com/publicsource and read it before using this file.
  11  *
  12  * This Original Code and all software distributed under the License are
  13  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  14  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  15  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
  17  * License for the specific language governing rights and limitations
  18  * under the License.
  19  *
  20  * @APPLE_LICENSE_HEADER_END@
  21  */
  22 #ifndef _PEXPERT_PPC_PROTOS_H_
  23 #define _PEXPERT_PPC_PROTOS_H_
  24
  25 #define mtsprg(n, reg)  __asm__ volatile("mtsprg  " # n ", %0" : : "r" (reg))
  26 #define mfsprg(reg, n)  __asm__ volatile("mfsprg  %0, " # n : "=r" (reg))
  27
  28 #define mtspr(spr, val)  __asm__ volatile("mtspr  " # spr ", %0" : : "r" (val))
  29 #define mfspr(reg, spr)  __asm__ volatile("mfspr  %0, " # spr : "=r" (reg))
  30
  31 /*
  32  * Various memory/IO synchronisation instructions
  33  */
  34
  35         /*      Use eieio as a memory barrier to order stores.
  36          *      Useful for device control and PTE maintenance.
  37          */
  38
  39 #define eieio() \
  40         __asm__ volatile("eieio")
  41
  42         /*      Use sync to ensure previous stores have completed.
  43                 This is  required when manipulating locks and/or
  44                 maintaining PTEs or other shared structures on SMP
  45                 machines.
  46         */
  47
  48 #define sync() \
  49         __asm__ volatile("sync")
  50
  51         /*      Use isync to sychronize context; that is, the ensure
  52                 no prefetching of instructions happen before the
  53                 instruction.
  54         */
  55
  56 #define isync() \
  57         __asm__ volatile("isync")
  58
  59
  60 //------------------------------------------------------------------------
  61 // from ppc/endian.h
  62 static __inline__ unsigned int byte_reverse_word(unsigned int word);
  63 static __inline__ unsigned int byte_reverse_word(unsigned int word) {
  64         unsigned int result;
  65         __asm__ volatile("lwbrx %0, 0, %1" : "=r" (result) : "r" (&word));
  66         return result;
  67 }
  68
  69 //------------------------------------------------------------------------
  70 // from ppc/serial_io.h
  71 extern void initialize_serial(void * scc_phys_base, uint32_t serial_baud);
  72
  73
  74 //------------------------------------------------------------------------
  75 // from osfmk/ppc/POWERMAC/video_console.c
  76
  77 extern void initialize_screen(void *, unsigned int);
  78
  79 extern void vc_progress_initialize( void * desc,
  80                                     const unsigned char * data,
  81                                     const unsigned char * clut );
  82
  83 extern void vc_display_icon( void * desc,
  84                              const unsigned char * data );
  85
  86 //-------------------------------------------------------------------------
  87 // from osfmk/console/panic_dialog.c
  88 extern void panic_ui_initialize(const unsigned char * clut);
  89
  90 // from osfmk/ppc/serial_console.c
  91 extern int  switch_to_serial_console(void);
  92 extern void switch_to_old_console(int old_console);
  93
  94 typedef unsigned spl_t;
  95
  96 //------------------------------------------------------------------------
  97 // from bsd/dev/ppc/busses.h which clashes with mach/device/device_types.h
  98 typedef int             io_req_t;
  99
 100
 101 //typedef struct ipc_port         *ipc_port_t;
 102
 103 extern void            cninit(void);
 104
 105 /*
 106  *      Temporarily stolen from Firmware.h
 107  */
 108
 109 extern void dbgTrace(unsigned int item1, unsigned int item2, unsigned int item3);
 110 #if 1           /* (TEST/DEBUG) - eliminate inline */
 111 extern __inline__ void dbgTrace(unsigned int item1, unsigned int item2, unsigned int item3) {
 112
 113         __asm__ volatile("mr   r3,%0" : : "r" (item1) : "r3");
 114         __asm__ volatile("mr   r4,%0" : : "r" (item2) : "r4");
 115         __asm__ volatile("mr   r5,%0" : : "r" (item3) : "r5");
 116         __asm__ volatile("lis  r0,hi16(CutTrace)" : : : "r0");
 117         __asm__ volatile("ori  r0,r0,lo16(CutTrace)" : : : "r0");
 118         __asm__ volatile("sc");
 119         return;
 120 }
 121 #endif
 122
 123 extern void DoPreempt(void);
 124 extern __inline__ void DoPreempt(void) {
 125         __asm__ volatile("lis  r0,hi16(DoPreemptCall)" : : : "r0");
 126         __asm__ volatile("ori  r0,r0,lo16(DoPreemptCall)" : : : "r0");
 127         __asm__ volatile("sc");
 128         return;
 129 }
 130
 131 extern void CreateFakeIO(void);
 132 extern __inline__ void CreateFakeIO(void) {
 133         __asm__ volatile("lis  r0,hi16(CreateFakeIOCall)" : : : "r0");
 134         __asm__ volatile("ori  r0,r0,lo16(CreateFakeIOCall)" : : : "r0");
 135         __asm__ volatile("sc");
 136                 return;
 137 }
 138
 139 extern void StoreReal(unsigned int val, unsigned int addr);
 140 extern void ReadReal(unsigned int raddr, unsigned int *vaddr);
 141 extern unsigned int LLTraceSet(unsigned int tflags);
 142 extern void GratefulDebInit(void);
 143 extern void GratefulDebDisp(unsigned int coord, unsigned int data);
 144 extern void checkNMI(void);
 145
 146 #endif /* _PEXPERT_PPC_PROTOS_H_ */