osfmk/i386/machine_routines_asm.s

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * The contents of this file constitute Original Code as defined in and
   7  * are subject to the Apple Public Source License Version 1.1 (the
   8  * "License").  You may not use this file except in compliance with the
   9  * License.  Please obtain a copy of the License at
  10  * http://www.apple.com/publicsource and read it before using this file.
  11  *
  12  * This Original Code and all software distributed under the License are
  13  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  14  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  15  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
  17  * License for the specific language governing rights and limitations
  18  * under the License.
  19  *
  20  * @APPLE_LICENSE_HEADER_END@
  21  */
  22 #include <i386/asm.h>
  23
  24 /*
  25 **      ml_get_timebase()
  26 **
  27 **      Entry   - %esp contains pointer to 64 bit structure.
  28 **
  29 **      Exit    - 64 bit structure filled in.
  30 **
  31 */
  32 ENTRY(ml_get_timebase)
  33
  34         movl    S_ARG0, %ecx
  35
  36         rdtsc
  37
  38         movl    %edx, 0(%ecx)
  39         movl    %eax, 4(%ecx)
  40
  41         ret
  42
  43
  44 /* PCI config cycle probing
  45  *
  46  *      boolean_t ml_probe_read(vm_offset_t paddr, unsigned int *val)
  47  *
  48  *      Read the memory location at physical address paddr.
  49  *  This is a part of a device probe, so there is a good chance we will
  50  *  have a machine check here. So we have to be able to handle that.
  51  *  We assume that machine checks are enabled both in MSR and HIDs
  52  */
  53 ENTRY(ml_probe_read)
  54
  55         movl S_ARG0, %ecx
  56         movl S_ARG1, %eax
  57         movl 0(%ecx), %ecx
  58         movl %ecx, 0(%eax)
  59         movl $1, %eax
  60
  61         ret
  62
  63
  64 /* PCI config cycle probing - 64-bit
  65  *
  66  *      boolean_t ml_probe_read_64(addr64_t paddr, unsigned int *val)
  67  *
  68  *      Read the memory location at physical address paddr.
  69  *  This is a part of a device probe, so there is a good chance we will
  70  *  have a machine check here. So we have to be able to handle that.
  71  *  We assume that machine checks are enabled both in MSR and HIDs
  72  */
  73 ENTRY(ml_probe_read_64)
  74
  75         /* Only use lower 32 bits of address for now */
  76         movl S_ARG0, %ecx
  77         movl S_ARG2, %eax
  78         movl 0(%ecx), %ecx
  79         movl %ecx, 0(%eax)
  80         movl $1, %eax
  81
  82         ret
  83
  84
  85 /* Read physical address byte
  86  *
  87  *      unsigned int ml_phys_read_byte(vm_offset_t paddr)
  88  *      unsigned int ml_phys_read_byte_64(addr64_t paddr)
  89  *
  90  *      Read the byte at physical address paddr. Memory should not be cache inhibited.
  91  */
  92 ENTRY(ml_phys_read_byte_64)
  93
  94         /* Only use lower 32 bits of address for now */
  95         movl S_ARG0, %ecx
  96         xor %eax, %eax
  97         movb 0(%ecx), %eax
  98
  99         ret
 100
 101 ENTRY(ml_phys_read_byte)
 102
 103         movl S_ARG0, %ecx
 104         xor %eax, %eax
 105         movb 0(%ecx), %eax
 106
 107         ret
 108
 109
 110 /* Read physical address half word
 111  *
 112  *      unsigned int ml_phys_read_half(vm_offset_t paddr)
 113  *      unsigned int ml_phys_read_half_64(addr64_t paddr)
 114  *
 115  *      Read the half word at physical address paddr. Memory should not be cache inhibited.
 116  */
 117 ENTRY(ml_phys_read_half_64)
 118
 119         /* Only use lower 32 bits of address for now */
 120         movl S_ARG0, %ecx
 121         xor %eax, %eax
 122         movw 0(%ecx), %eax
 123
 124         ret
 125
 126 ENTRY(ml_phys_read_half)
 127
 128         movl S_ARG0, %ecx
 129         xor %eax, %eax
 130         movw 0(%ecx), %eax
 131
 132         ret
 133
 134
 135 /* Read physical address word
 136  *
 137  *      unsigned int ml_phys_read(vm_offset_t paddr)
 138  *      unsigned int ml_phys_read_64(addr64_t paddr)
 139  *      unsigned int ml_phys_read_word(vm_offset_t paddr)
 140  *      unsigned int ml_phys_read_word_64(addr64_t paddr)
 141  *
 142  *      Read the word at physical address paddr. Memory should not be cache inhibited.
 143  */
 144 ENTRY(ml_phys_read_64)
 145 ENTRY(ml_phys_read_word_64)
 146
 147         /* Only use lower 32 bits of address for now */
 148         movl S_ARG0, %ecx
 149         movl 0(%ecx), %eax
 150
 151         ret
 152
 153 ENTRY(ml_phys_read)
 154 ENTRY(ml_phys_read_word)
 155
 156         movl S_ARG0, %ecx
 157         movl 0(%ecx), %eax
 158
 159         ret
 160
 161
 162 /* Read physical address double
 163  *
 164  *      unsigned long long ml_phys_read_double(vm_offset_t paddr)
 165  *      unsigned long long ml_phys_read_double_64(addr64_t paddr)
 166  *
 167  *      Read the double word at physical address paddr. Memory should not be cache inhibited.
 168  */
 169 ENTRY(ml_phys_read_double_64)
 170
 171         /* Only use lower 32 bits of address for now */
 172         movl S_ARG0, %ecx
 173         movl 0(%ecx), %eax
 174         movl 4(%ecx), %edx
 175
 176         ret
 177
 178 ENTRY(ml_phys_read_double)
 179
 180         movl S_ARG0, %ecx
 181         movl 0(%ecx), %eax
 182         movl 4(%ecx), %edx
 183
 184         ret
 185
 186
 187 /* Write physical address byte
 188  *
 189  *      void ml_phys_write_byte(vm_offset_t paddr, unsigned int data)
 190  *      void ml_phys_write_byte_64(addr64_t paddr, unsigned int data)
 191  *
 192  *      Write the byte at physical address paddr. Memory should not be cache inhibited.
 193  */
 194 ENTRY(ml_phys_write_byte_64)
 195
 196         /* Only use lower 32 bits of address for now */
 197         movl S_ARG0, %ecx
 198         movl S_ARG2, %eax
 199         movb %eax, 0(%ecx)
 200
 201         ret
 202
 203 ENTRY(ml_phys_write_byte)
 204
 205         movl S_ARG0, %ecx
 206         movl S_ARG1, %eax
 207         movb %eax, 0(%ecx)
 208
 209         ret
 210
 211
 212 /* Write physical address half word
 213  *
 214  *      void ml_phys_write_half(vm_offset_t paddr, unsigned int data)
 215  *      void ml_phys_write_half_64(addr64_t paddr, unsigned int data)
 216  *
 217  *      Write the byte at physical address paddr. Memory should not be cache inhibited.
 218  */
 219 ENTRY(ml_phys_write_half_64)
 220
 221         /* Only use lower 32 bits of address for now */
 222         movl S_ARG0, %ecx
 223         movl S_ARG2, %eax
 224         movw %eax, 0(%ecx)
 225
 226         ret
 227
 228 ENTRY(ml_phys_write_half)
 229
 230         movl S_ARG0, %ecx
 231         movl S_ARG1, %eax
 232         movw %eax, 0(%ecx)
 233
 234         ret
 235
 236
 237 /* Write physical address word
 238  *
 239  *      void ml_phys_write(vm_offset_t paddr, unsigned int data)
 240  *      void ml_phys_write_64(addr64_t paddr, unsigned int data)
 241  *      void ml_phys_write_word(vm_offset_t paddr, unsigned int data)
 242  *      void ml_phys_write_word_64(addr64_t paddr, unsigned int data)
 243  *
 244  *      Write the word at physical address paddr. Memory should not be cache inhibited.
 245  */
 246 ENTRY(ml_phys_write_64)
 247 ENTRY(ml_phys_write_word_64)
 248
 249         /* Only use lower 32 bits of address for now */
 250         movl S_ARG0, %ecx
 251         movl S_ARG2, %eax
 252         movl %eax, 0(%ecx)
 253
 254         ret
 255
 256 ENTRY(ml_phys_write)
 257 ENTRY(ml_phys_write_word)
 258
 259         movl S_ARG0, %ecx
 260         movl S_ARG1, %eax
 261         movl %eax, 0(%ecx)
 262
 263         ret
 264
 265
 266 /* Write physical address double word
 267  *
 268  *      void ml_phys_write_double(vm_offset_t paddr, unsigned long long data)
 269  *      void ml_phys_write_double_64(addr64_t paddr, unsigned long long data)
 270  *
 271  *      Write the double word at physical address paddr. Memory should not be cache inhibited.
 272  */
 273 ENTRY(ml_phys_write_double_64)
 274
 275         /* Only use lower 32 bits of address for now */
 276         movl S_ARG0, %ecx
 277         movl S_ARG2, %eax
 278         movl %eax, 0(%ecx)
 279         movl S_ARG3, %eax
 280         movl %eax, 4(%ecx)
 281
 282         ret
 283
 284 ENTRY(ml_phys_write_double)
 285
 286         movl S_ARG0, %ecx
 287         movl S_ARG1, %eax
 288         movl %eax, 0(%ecx)
 289         movl S_ARG2, %eax
 290         movl %eax, 4(%ecx)
 291
 292         ret