osfmk/i386/cpuid.h

   1 /*
   2  * Copyright (c) 2000-2003 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * The contents of this file constitute Original Code as defined in and
   7  * are subject to the Apple Public Source License Version 1.1 (the
   8  * "License").  You may not use this file except in compliance with the
   9  * License.  Please obtain a copy of the License at
  10  * http://www.apple.com/publicsource and read it before using this file.
  11  *
  12  * This Original Code and all software distributed under the License are
  13  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  14  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  15  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
  17  * License for the specific language governing rights and limitations
  18  * under the License.
  19  *
  20  * @APPLE_LICENSE_HEADER_END@
  21  */
  22 /*
  23  * @OSF_COPYRIGHT@
  24  */
  25
  26 /*
  27  * x86 CPU identification
  28  *
  29  */
  30
  31 #ifndef _MACHINE_CPUID_H_
  32 #define _MACHINE_CPUID_H_
  33
  34 #include <sys/appleapiopts.h>
  35
  36 #ifdef __APPLE_API_PRIVATE
  37
  38 #define CPUID_VID_SIZE          12
  39 #define CPUID_VID_INTEL         "GenuineIntel"
  40 #define CPUID_VID_UMC           "UMC UMC UMC "
  41 #define CPUID_VID_AMD           "AuthenticAMD"
  42 #define CPUID_VID_CYRIX         "CyrixInstead"
  43 #define CPUID_VID_NEXTGEN       "NexGenDriven"
  44
  45 #define CPUID_FEATURE_FPU    0x00000001 /* Floating point unit on-chip */
  46 #define CPUID_FEATURE_VME    0x00000002 /* Virtual Mode Extension */
  47 #define CPUID_FEATURE_DE     0x00000004 /* Debugging Extension */
  48 #define CPUID_FEATURE_PSE    0x00000008 /* Page Size Extension */
  49 #define CPUID_FEATURE_TSC    0x00000010 /* Time Stamp Counter */
  50 #define CPUID_FEATURE_MSR    0x00000020 /* Model Specific Registers */
  51 #define CPUID_FEATURE_PAE    0x00000040 /* Physical Address Extension */
  52 #define CPUID_FEATURE_MCE    0x00000080 /* Machine Check Exception */
  53 #define CPUID_FEATURE_CX8    0x00000100 /* CMPXCHG8B */
  54 #define CPUID_FEATURE_APIC   0x00000200 /* On-chip APIC */
  55 #define CPUID_FEATURE_SEP    0x00000800 /* Fast System Call */
  56 #define CPUID_FEATURE_MTRR   0x00001000 /* Memory Type Range Register */
  57 #define CPUID_FEATURE_PGE    0x00002000 /* Page Global Enable */
  58 #define CPUID_FEATURE_MCA    0x00004000 /* Machine Check Architecture */
  59 #define CPUID_FEATURE_CMOV   0x00008000 /* Conditional Move Instruction */
  60 #define CPUID_FEATURE_PAT    0x00010000 /* Page Attribute Table */
  61 #define CPUID_FEATURE_PSE36  0x00020000 /* 36-bit Page Size Extension */
  62 #define CPUID_FEATURE_PSN    0x00040000 /* Processor Serial Number */
  63 #define CPUID_FEATURE_CLFSH  0x00080000 /* CLFLUSH Instruction supported */
  64 #define CPUID_FEATURE_DS     0x00200000 /* Debug Store */
  65 #define CPUID_FEATURE_ACPI   0x00400000 /* Thermal Monitor, SW-controlled clock */
  66 #define CPUID_FEATURE_MMX    0x00800000 /* MMX supported */
  67 #define CPUID_FEATURE_FXSR   0x01000000 /* Fast floating point save/restore */
  68 #define CPUID_FEATURE_SSE    0x02000000 /* Streaming SIMD extensions */
  69 #define CPUID_FEATURE_SSE2   0x04000000 /* Streaming SIMD extensions 2 */
  70 #define CPUID_FEATURE_SS     0x08000000 /* Self-Snoop */
  71 #define CPUID_FEATURE_HTT    0x10000000 /* Hyper-Threading Technology */
  72 #define CPUID_FEATURE_TM     0x20000000 /* Thermal Monitor */
  73
  74 #define CPUID_TYPE_OEM              0x0 /* Original processor */
  75 #define CPUID_TYPE_OVERDRIVE        0x1 /* Overdrive processor */
  76 #define CPUID_TYPE_DUAL             0x2 /* Can be used as dual processor */
  77 #define CPUID_TYPE_RESERVED         0x3 /* Reserved */
  78
  79 #define CPUID_FAMILY_386            0x3 /* Intel 386 (not part of CPUID) */
  80 #define CPUID_FAMILY_486            0x4 /* Intel 486 */
  81 #define CPUID_FAMILY_P5             0x5 /* Intel Pentium */
  82 #define CPUID_FAMILY_PPRO           0x6 /* Intel Pentium Pro, II, III */
  83 #define CPUID_FAMILY_PENTIUM4       0xF /* Intel Pentium 4 */
  84
  85 #define CPUID_MODEL_I386_DX         0x0 /* Intel 386 (not part of CPUID) */
  86
  87 #define CPUID_MODEL_I486_DX         0x0 /* Intel 486DX */
  88 #define CPUID_MODEL_I486_DX_S       0x1 /* Intel 486DX-S */
  89 #define CPUID_MODEL_I486_SX         0x2 /* Intel 486SX */
  90 #define CPUID_MODEL_I486_DX2        0x3 /* Intel 486DX2 */
  91 #define CPUID_MODEL_I486_SL         0x4 /* Intel 486SL */
  92 #define CPUID_MODEL_I486_SX2        0x5 /* Intel 486SX2 */
  93 #define CPUID_MODEL_I486_DX2WB      0x7 /* Intel 486DX2WB */
  94 #define CPUID_MODEL_I486_DX4        0x8 /* Intel 486DX4 */
  95 #define CPUID_MODEL_I486_DX4WB      0x9 /* Intel 486DX4WB */
  96
  97 #define CPUID_MODEL_AM486_DX        0x1 /* AMD 486DX */
  98 #define CPUID_MODEL_AM486_DX2       0x3 /* AMD 486DX2 */
  99 #define CPUID_MODEL_AM486_DX2WB     0x7 /* AMD 486DX2WB */
 100 #define CPUID_MODEL_AM486_DX4       0x8 /* AMD 486DX4 */
 101 #define CPUID_MODEL_AM486_DX4WB     0x9 /* AMD 486DX4WB */
 102 #define CPUID_MODEL_AM486_5X86      0xE /* AMD 5x86 */
 103 #define CPUID_MODEL_AM486_5X86WB    0xF /* AMD 5x86WB */
 104
 105 #define CPUID_MODEL_CYRIX5X86       0x9 /* CYRIX 5X86 */
 106
 107 #define CPUID_MODEL_UMC5SD          0x1 /* UMC U5SD */
 108 #define CPUID_MODEL_UMC5S           0x2 /* UMC U5S */
 109 #define CPUID_MODEL_UMC486_DX2      0x3 /* UMC U486_DX2 */
 110 #define CPUID_MODEL_UMC486_SX2      0x5 /* UMC U486_SX2 */
 111
 112 #define CPUID_MODEL_P5A             0x0 /* Intel P5 60/66 Step A */
 113 #define CPUID_MODEL_P5              0x1 /* Intel P5 60/66 */
 114 #define CPUID_MODEL_P54             0x2 /* Intel P5 75/80/100/120/133/166 */
 115 #define CPUID_MODEL_P24T            0x3 /* Intel P5 Overdrive 63/83 */
 116
 117 #define CPUID_MODEL_P6              0x1 /* Intel P6 */
 118 #define CPUID_MODEL_PII             0x3 /* Intel PII */
 119 #define CPUID_MODEL_P65             0x5 /* Intel PII/Xeon/Celeron model 5 */
 120 #define CPUID_MODEL_P66             0x6 /* Intel Celeron model 6 */
 121 #define CPUID_MODEL_P67             0x7 /* Intel PIII/Xeon model 7 */
 122 #define CPUID_MODEL_P68             0x8 /* Intel PIII/Xeon/Celeron model 8 */
 123 #define CPUID_MODEL_P6A             0xA /* Intel PIII Xeon model A */
 124 #define CPUID_MODEL_P6B             0xB /* Intel PIII model B */
 125
 126 #define CPUID_CACHE_SIZE        16      /* Number of descriptor vales */
 127
 128 #define CPUID_CACHE_NULL           0x00 /* NULL */
 129 #define CPUID_CACHE_ITLB_4K        0x01 /* Instruction TLB, 4K pages */
 130 #define CPUID_CACHE_ITLB_4M        0x02 /* Instruction TLB, 4M pages */
 131 #define CPUID_CACHE_DTLB_4K        0x03 /* Data TLB, 4K pages */
 132 #define CPUID_CACHE_DTLB_4M        0x04 /* Data TLB, 4M pages */
 133 #define CPUID_CACHE_ICACHE_8K      0x06 /* Instruction cache, 8K */
 134 #define CPUID_CACHE_ICACHE_16K     0x08 /* Instruction cache, 16K */
 135 #define CPUID_CACHE_DCACHE_8K      0x0A /* Data cache, 8K */
 136 #define CPUID_CACHE_DCACHE_16K     0x0C /* Data cache, 16K */
 137 #define CPUID_CACHE_UCACHE_128K    0x41 /* 2nd-level cache, 128K */
 138 #define CPUID_CACHE_UCACHE_256K    0x42 /* 2nd-level cache, 256K */
 139 #define CPUID_CACHE_UCACHE_512K    0x43 /* 2nd-level cache, 512K */
 140 #define CPUID_CACHE_UCACHE_1M      0x44 /* 2nd-level cache, 1M */
 141 #define CPUID_CACHE_UCACHE_2M      0x45 /* 2nd-level cache, 2M */
 142 #define CPUID_CACHE_ITLB_64        0x50 /* Instruction TLB, 64 entries */
 143 #define CPUID_CACHE_ITLB_128       0x51 /* Instruction TLB, 128 entries */
 144 #define CPUID_CACHE_ITLB_256       0x52 /* Instruction TLB, 256 entries */
 145 #define CPUID_CACHE_DTLB_64        0x5B /* Data TLB, 64 entries */
 146 #define CPUID_CACHE_DTLB_128       0x5C /* Data TLB, 128 entries */
 147 #define CPUID_CACHE_DTLB_256       0x5D /* Data TLB, 256 entries */
 148 #define CPUID_CACHE_DCACHE_8K_64   0x66 /* Data cache, 8K, 64 byte line size */
 149 #define CPUID_CACHE_DCACHE_16K_64  0x67 /* Data cache, 16K, 64 byte line size */
 150 #define CPUID_CACHE_DCACHE_32K_64  0x68 /* Data cache, 32K, 64 byte line size */
 151 #define CPUID_CACHE_TRACE_12K      0x70 /* Trace cache 12K-uop, 8-way */
 152 #define CPUID_CACHE_TRACE_16K      0x71 /* Trace cache 16K-uop, 8-way */
 153 #define CPUID_CACHE_TRACE_32K      0x72 /* Trace cache 32K-uop, 8-way */
 154 #define CPUID_CACHE_UCACHE_128K_64 0x79 /* 2nd-level, 128K, 8-way, 64 bytes */
 155 #define CPUID_CACHE_UCACHE_256K_64 0x7A /* 2nd-level, 256K, 8-way, 64 bytes */
 156 #define CPUID_CACHE_UCACHE_512K_64 0x7B /* 2nd-level, 512K, 8-way, 64 bytes */
 157 #define CPUID_CACHE_UCACHE_1M_64   0x7C /* 2nd-level, 1M, 8-way, 64 bytes */
 158 #define CPUID_CACHE_UCACHE_256K_32 0x82 /* 2nd-level, 256K, 8-way, 32 bytes */
 159 #define CPUID_CACHE_UCACHE_512K_32 0x83 /* 2nd-level, 512K, 8-way, 32 bytes */
 160 #define CPUID_CACHE_UCACHE_1M_32   0x84 /* 2nd-level, 1M, 8-way, 32 bytes */
 161 #define CPUID_CACHE_UCACHE_2M_32   0x85 /* 2nd-level, 2M, 8-way, 32 bytes */
 162
 163 #ifndef ASSEMBLER
 164 #include <stdint.h>
 165 #include <mach/mach_types.h>
 166 #include <kern/kern_types.h>
 167 #include <mach/machine.h>
 168
 169
 170 static inline void
 171 do_cpuid(uint32_t selector, uint32_t *data)
 172 {
 173         asm("cpuid"
 174                 : "=a" (data[0]),
 175                   "=b" (data[1]),
 176                   "=c" (data[2]),
 177                   "=d" (data[3])
 178                 : "a"(selector));
 179 }
 180
 181 /*
 182  * Cache ID descriptor structure.
 183  * Note: description string absent in kernel.
 184  */
 185 typedef enum { Lnone, L1I, L1D, L2U, LCACHE_MAX } cache_type_t ;
 186 typedef struct {
 187         unsigned char   value;          /* Descriptor value */
 188         cache_type_t    type;           /* Cache type */
 189         unsigned int    size;           /* Cache size */
 190         unsigned int    linesize;       /* Cache line size */
 191 #ifdef KERNEL
 192         char            *description;   /* Cache description */
 193 #endif /* KERNEL */
 194 } cpuid_cache_desc_t;
 195
 196 #ifdef KERNEL
 197 #define CACHE_DESC(value,type,size,linesize,text) \
 198         { value, type, size, linesize, text }
 199 #else
 200 #define CACHE_DESC(value,type,size,linesize,text) \
 201         { value, type, size, linesize }
 202 #endif /* KERNEL */
 203
 204 /* Physical CPU info */
 205 typedef struct {
 206         char            cpuid_vendor[16];
 207         char            cpuid_brand_string[48];
 208
 209         uint32_t        cpuid_value;
 210         cpu_type_t      cpuid_type;
 211         uint8_t         cpuid_family;
 212         uint8_t         cpuid_model;
 213         uint8_t         cpuid_extmodel;
 214         uint8_t         cpuid_extfamily;
 215         uint8_t         cpuid_stepping;
 216         uint32_t        cpuid_features;
 217         uint32_t        cpuid_signature;
 218         uint8_t         cpuid_brand;
 219
 220         uint32_t        cache_size[LCACHE_MAX];
 221         uint32_t        cache_linesize;
 222
 223         char            model_string[64];  /* sanitized model string */
 224         uint8_t         cache_info[64];    /* list of cache descriptors */
 225
 226 } i386_cpu_info_t;
 227
 228
 229 /*
 230  * External declarations
 231  */
 232 extern cpu_type_t       cpuid_cputype(int);
 233 extern void             cpuid_cpu_display(char *, int);
 234 extern void             cpuid_features_display(char *, int);
 235 extern char *           cpuid_get_feature_names(uint32_t, char *, unsigned);
 236
 237 extern uint32_t         cpuid_features(void);
 238 extern uint32_t         cpuid_family(void);
 239
 240 extern char *           cpuid_intel_get_model_name(uint8_t, uint8_t,
 241                                                    uint8_t, uint32_t);
 242
 243 extern i386_cpu_info_t  *cpuid_info(void);
 244
 245 extern uint32_t         cpuid_feature;  /* XXX obsolescent */
 246 #endif /* ASSEMBLER */
 247
 248 #endif /* __APPLE_API_PRIVATE */
 249 #endif /* _MACHINE_CPUID_H_ */