osfmk/i386/commpage/cacheflush.s

   1 /*
   2  * Copyright (c) 2003-2006 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_OSREFERENCE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License.  The rights granted to you under the
  10  * License may not be used to create, or enable the creation or
  11  * redistribution of, unlawful or unlicensed copies of an Apple operating
  12  * system, or to circumvent, violate, or enable the circumvention or
  13  * violation of, any terms of an Apple operating system software license
  14  * agreement.
  15  *
  16  * Please obtain a copy of the License at
  17  * http://www.opensource.apple.com/apsl/ and read it before using this
  18  * file.
  19  *
  20  * The Original Code and all software distributed under the License are
  21  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  22  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  23  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  25  * Please see the License for the specific language governing rights and
  26  * limitations under the License.
  27  *
  28  * @APPLE_LICENSE_OSREFERENCE_HEADER_END@
  29  */
  30
  31 #include <machine/cpu_capabilities.h>
  32 #include <machine/commpage.h>
  33
  34         .text
  35         .align  2, 0x90
  36
  37 // void sysFlushDcache( void *p, size_t len );
  38 // 32-bit version
  39
  40 Lsys_flush_dcache:
  41         movl    4(%esp),%ecx            // get length
  42         movl    8(%esp),%edx            // get ptr
  43         testl   %ecx,%ecx               // length 0?
  44         jz      2f                      // yes
  45         mfence                          // ensure previous stores make it to memory
  46 1:
  47         clflush (%edx)                  // flush a line
  48         addl    $64,%edx
  49         subl    $64,%ecx
  50         jnc     1b
  51         mfence                          // make sure memory is updated before we return
  52 2:
  53         ret
  54
  55         COMMPAGE_DESCRIPTOR(sys_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,kCache64,0)
  56
  57
  58 // void sysFlushDcache( void *p, size_t len );
  59 // 64-bit version
  60         .code64
  61 Lsys_flush_dcache_64:                   // %rdi = ptr,  %rsi = length
  62         testq   %rsi,%rsi               // length 0?
  63         jz      2f                      // yes
  64         mfence                          // ensure previous stores make it to memory
  65 1:
  66         clflush (%rdi)                  // flush a line
  67         addq    $64,%rdi
  68         subq    $64,%rsi
  69         jnc     1b
  70         mfence                          // make sure memory is updated before we return
  71 2:
  72         ret
  73         .code32
  74         COMMPAGE_DESCRIPTOR(sys_flush_dcache_64,_COMM_PAGE_FLUSH_DCACHE,kCache64,0)
  75
  76
  77 // void sysIcacheInvalidate( void *p, size_t len );
  78
  79 Lsys_icache_invalidate:
  80         // This is a NOP on intel processors, since the intent of the API
  81         // is to make data executable, and Intel L1Is are coherent with L1D.
  82         // We can use same routine both in 32 and 64-bit mode, since it is
  83         // just a RET instruction.
  84         ret
  85
  86         COMMPAGE_DESCRIPTOR(sys_icache_invalidate,_COMM_PAGE_FLUSH_ICACHE,0,0)