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[apple/xnu.git] / osfmk / chud / ppc / chud_cpu_ppc.c
1 /*
2 * Copyright (c) 2003-2004 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_OSREFERENCE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the
10 * License may not be used to create, or enable the creation or
11 * redistribution of, unlawful or unlicensed copies of an Apple operating
12 * system, or to circumvent, violate, or enable the circumvention or
13 * violation of, any terms of an Apple operating system software license
14 * agreement.
15 *
16 * Please obtain a copy of the License at
17 * http://www.opensource.apple.com/apsl/ and read it before using this
18 * file.
19 *
20 * The Original Code and all software distributed under the License are
21 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
22 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
23 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
25 * Please see the License for the specific language governing rights and
26 * limitations under the License.
27 *
28 * @APPLE_LICENSE_OSREFERENCE_HEADER_END@
29 */
30 #include <mach/mach_types.h>
31 #include <mach/mach_host.h>
32
33 #include <kern/host.h>
34 #include <kern/processor.h>
35
36 #include <chud/chud_xnu.h>
37 #include <chud/ppc/chud_spr.h>
38 #include <chud/ppc/chud_cpu_asm.h>
39 #include <ppc/machine_routines.h>
40 #include <ppc/exception.h>
41 #include <ppc/hw_perfmon.h>
42 #include <ppc/Diagnostics.h>
43
44 // the macros in proc_reg.h fail with "expression must be absolute"
45
46 #undef mtsprg
47 #undef mfsprg
48 #define mtsprg(n, reg) __asm__ volatile("mtsprg " # n ", %0" : : "r" (reg))
49 #define mfsprg(reg, n) __asm__ volatile("mfsprg %0, " # n : "=r" (reg))
50
51 #undef mtspr
52 #undef mfspr
53 #define mtspr(spr, reg) __asm__ volatile ("mtspr %0, %1" : : "n" (spr), "r" (reg))
54 #define mfspr(reg, spr) __asm__ volatile("mfspr %0, %1" : "=r" (reg) : "n" (spr));
55
56 #undef mtsr
57 #undef mfsr
58 #define mtsr(sr, reg) __asm__ volatile("sync" "@" "mtsr sr%0, %1 " "@" "isync" : : "i" (sr), "r" (reg));
59 #define mfsr(reg, sr) __asm__ volatile("mfsr %0, sr%1" : "=r" (reg) : "i" (sr));
60
61 #pragma mark **** cpu enable/disable ****
62
63 extern kern_return_t processor_start(processor_t processor); // osfmk/kern/processor.c
64 extern kern_return_t processor_exit(processor_t processor); // osfmk/kern/processor.c
65
66 __private_extern__
67 kern_return_t chudxnu_enable_cpu(int cpu, boolean_t enable)
68 {
69 chudxnu_unbind_thread(current_thread());
70
71 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
72 return KERN_FAILURE;
73 }
74
75 if((PerProcTable[cpu].ppe_vaddr != (struct per_proc_info *)NULL)
76 && cpu != master_cpu) {
77 processor_t processor = cpu_to_processor(cpu);
78
79 if(enable) {
80 return processor_start(processor);
81 } else {
82 return processor_exit(processor);
83 }
84 }
85 return KERN_FAILURE;
86 }
87
88 #pragma mark **** nap ****
89
90 __private_extern__
91 kern_return_t chudxnu_enable_cpu_nap(int cpu, boolean_t enable)
92 {
93 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
94 return KERN_FAILURE;
95 }
96
97 if(PerProcTable[cpu].ppe_vaddr != (struct per_proc_info *)NULL) {
98 ml_enable_nap(cpu, enable);
99 return KERN_SUCCESS;
100 }
101
102 return KERN_FAILURE;
103 }
104
105 __private_extern__
106 boolean_t chudxnu_cpu_nap_enabled(int cpu)
107 {
108 boolean_t prev;
109
110 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
111 cpu = 0;
112 }
113
114 prev = ml_enable_nap(cpu, TRUE);
115 ml_enable_nap(cpu, prev);
116
117 return prev;
118 }
119
120 #pragma mark **** shadowed spr ****
121
122 __private_extern__
123 kern_return_t chudxnu_set_shadowed_spr(int cpu, int spr, uint32_t val)
124 {
125 cpu_subtype_t target_cpu_subtype;
126 uint32_t available;
127 kern_return_t retval = KERN_FAILURE;
128 struct per_proc_info *per_proc;
129 boolean_t didBind = FALSE;
130
131 if(cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
132 return KERN_FAILURE;
133 }
134
135 if(cpu<0) { // cpu<0 means don't bind (current cpu)
136 cpu = chudxnu_cpu_number();
137 didBind = FALSE;
138 } else {
139 chudxnu_bind_thread(current_thread(), cpu);
140 didBind = TRUE;
141 }
142
143 per_proc = PerProcTable[cpu].ppe_vaddr;
144 available = per_proc->pf.Available;
145 target_cpu_subtype = per_proc->cpu_subtype;
146
147 if(spr==chud_750_l2cr) {
148 switch(target_cpu_subtype) {
149 case CPU_SUBTYPE_POWERPC_750:
150 case CPU_SUBTYPE_POWERPC_7400:
151 case CPU_SUBTYPE_POWERPC_7450:
152 if(available & pfL2) {
153 // int enable = (val & 0x80000000) ? TRUE : FALSE;
154 // if(enable) {
155 // per_proc->pf.l2cr = val;
156 // } else {
157 // per_proc->pf.l2cr = 0;
158 // }
159 per_proc->pf.l2cr = val;
160 cacheInit();
161 // mtspr(l2cr, per_proc->pf.l2cr); // XXXXXXX why is this necessary? XXXXXXX
162 retval = KERN_SUCCESS;
163 } else {
164 retval = KERN_FAILURE;
165 }
166 break;
167 default:
168 retval = KERN_INVALID_ARGUMENT;
169 break;
170 }
171 }
172 else if(spr==chud_7450_l3cr) {
173 switch(target_cpu_subtype) {
174 case CPU_SUBTYPE_POWERPC_7450:
175 if(available & pfL3) {
176 int enable = (val & 0x80000000) ? TRUE : FALSE;
177 if(enable) {
178 per_proc->pf.l3cr = val;
179 } else {
180 per_proc->pf.l3cr = 0;
181 }
182 cacheInit();
183 retval = KERN_SUCCESS;
184 } else {
185 retval = KERN_FAILURE;
186 }
187 break;
188 default:
189 retval = KERN_INVALID_ARGUMENT;
190 break;
191 }
192 }
193 else if(spr==chud_750_hid0) {
194 switch(target_cpu_subtype) {
195 case CPU_SUBTYPE_POWERPC_750:
196 cacheInit();
197 cacheDisable(); /* disable caches */
198 mtspr(chud_750_hid0, val);
199 per_proc->pf.pfHID0 = val;
200 cacheInit(); /* reenable caches */
201 retval = KERN_SUCCESS;
202 break;
203 case CPU_SUBTYPE_POWERPC_7400:
204 case CPU_SUBTYPE_POWERPC_7450:
205 mtspr(chud_750_hid0, val);
206 per_proc->pf.pfHID0 = val;
207 retval = KERN_SUCCESS;
208 break;
209 default:
210 retval = KERN_INVALID_ARGUMENT;
211 break;
212 }
213 }
214 else if(spr==chud_750_hid1) {
215 switch(target_cpu_subtype) {
216 case CPU_SUBTYPE_POWERPC_750:
217 case CPU_SUBTYPE_POWERPC_7400:
218 case CPU_SUBTYPE_POWERPC_7450:
219 mtspr(chud_750_hid1, val);
220 per_proc->pf.pfHID1 = val;
221 retval = KERN_SUCCESS;
222 break;
223 default:
224 retval = KERN_INVALID_ARGUMENT;
225 break;
226 }
227 }
228 else if(spr==chud_750fx_hid2 && target_cpu_subtype==CPU_SUBTYPE_POWERPC_750) {
229 mtspr(chud_750fx_hid2, val);
230 per_proc->pf.pfHID2 = val;
231 retval = KERN_SUCCESS;
232 }
233 else if(spr==chud_7400_msscr0 && (target_cpu_subtype==CPU_SUBTYPE_POWERPC_7400 || target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450)) {
234 mtspr(chud_7400_msscr0, val);
235 per_proc->pf.pfMSSCR0 = val;
236 retval = KERN_SUCCESS;
237 }
238 else if(spr==chud_7400_msscr1 && (target_cpu_subtype==CPU_SUBTYPE_POWERPC_7400 || target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450)) { // called msssr0 on 7450
239 mtspr(chud_7400_msscr1, val);
240 per_proc->pf.pfMSSCR1 = val;
241 retval = KERN_SUCCESS;
242 }
243 else if(spr==chud_7450_ldstcr && target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450) {
244 mtspr(chud_7450_ldstcr, val);
245 per_proc->pf.pfLDSTCR = val;
246 retval = KERN_SUCCESS;
247 }
248 else if(spr==chud_7450_ictrl && target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450) {
249 mtspr(chud_7450_ictrl, val);
250 per_proc->pf.pfICTRL = val;
251 retval = KERN_SUCCESS;
252 } else {
253 retval = KERN_INVALID_ARGUMENT;
254 }
255
256 if(didBind) {
257 chudxnu_unbind_thread(current_thread());
258 }
259
260 return retval;
261 }
262
263 __private_extern__
264 kern_return_t chudxnu_set_shadowed_spr64(int cpu, int spr, uint64_t val)
265 {
266 cpu_subtype_t target_cpu_subtype;
267 kern_return_t retval = KERN_FAILURE;
268 struct per_proc_info *per_proc;
269 boolean_t didBind = FALSE;
270
271 if(cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
272 return KERN_FAILURE;
273 }
274
275 if(cpu<0) { // cpu<0 means don't bind (current cpu)
276 cpu = chudxnu_cpu_number();
277 didBind = FALSE;
278 } else {
279 chudxnu_bind_thread(current_thread(), cpu);
280 didBind = TRUE;
281 }
282
283 per_proc = PerProcTable[cpu].ppe_vaddr;
284 target_cpu_subtype = per_proc->cpu_subtype;
285
286 if(spr==chud_970_hid0) {
287 switch(target_cpu_subtype) {
288 case CPU_SUBTYPE_POWERPC_970:
289 mtspr64(chud_970_hid0, &val);
290 per_proc->pf.pfHID0 = val;
291 retval = KERN_SUCCESS;
292 break;
293 default:
294 retval = KERN_INVALID_ARGUMENT;
295 break;
296 }
297 }
298 else if(spr==chud_970_hid1) {
299 switch(target_cpu_subtype) {
300 case CPU_SUBTYPE_POWERPC_970:
301 mtspr64(chud_970_hid1, &val);
302 per_proc->pf.pfHID1 = val;
303 retval = KERN_SUCCESS;
304 break;
305 default:
306 retval = KERN_INVALID_ARGUMENT;
307 break;
308 }
309 }
310 else if(spr==chud_970_hid4) {
311 switch(target_cpu_subtype) {
312 case CPU_SUBTYPE_POWERPC_970:
313 mtspr64(chud_970_hid4, &val);
314 per_proc->pf.pfHID4 = val;
315 retval = KERN_SUCCESS;
316 break;
317 default:
318 retval = KERN_INVALID_ARGUMENT;
319 break;
320 }
321 }
322 else if(spr==chud_970_hid5) {
323 switch(target_cpu_subtype) {
324 case CPU_SUBTYPE_POWERPC_970:
325 mtspr64(chud_970_hid5, &val);
326 per_proc->pf.pfHID5 = val;
327 retval = KERN_SUCCESS;
328 break;
329 default:
330 retval = KERN_INVALID_ARGUMENT;
331 break;
332 }
333 } else {
334 retval = KERN_INVALID_ARGUMENT;
335 }
336
337 if(didBind) {
338 chudxnu_unbind_thread(current_thread());
339 }
340
341 return retval;
342 }
343
344 __private_extern__
345 uint32_t chudxnu_get_orig_cpu_l2cr(int cpu)
346 {
347 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
348 cpu = 0;
349 }
350 return PerProcTable[cpu].ppe_vaddr->pf.l2crOriginal;
351 }
352
353 __private_extern__
354 uint32_t chudxnu_get_orig_cpu_l3cr(int cpu)
355 {
356 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
357 cpu = 0;
358 }
359 return PerProcTable[cpu].ppe_vaddr->pf.l3crOriginal;
360 }
361
362 #pragma mark **** spr ****
363
364 __private_extern__
365 kern_return_t chudxnu_read_spr(int cpu, int spr, uint32_t *val_p)
366 {
367 kern_return_t retval = KERN_SUCCESS;
368 boolean_t oldlevel;
369 uint32_t val = 0xFFFFFFFF;
370
371 /* bind to requested CPU */
372 if(cpu>=0) { // cpu<0 means don't bind
373 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
374 return KERN_INVALID_ARGUMENT;
375 }
376 }
377
378 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
379
380 do {
381 /* PPC SPRs - 32-bit and 64-bit implementations */
382 if(spr==chud_ppc_srr0) { mfspr(val, chud_ppc_srr0); break; }
383 if(spr==chud_ppc_srr1) { mfspr(val, chud_ppc_srr1); break; }
384 if(spr==chud_ppc_dsisr) { mfspr(val, chud_ppc_dsisr); break; }
385 if(spr==chud_ppc_dar) { mfspr(val, chud_ppc_dar); break; }
386 if(spr==chud_ppc_dec) { mfspr(val, chud_ppc_dec); break; }
387 if(spr==chud_ppc_sdr1) { mfspr(val, chud_ppc_sdr1); break; }
388 if(spr==chud_ppc_sprg0) { mfspr(val, chud_ppc_sprg0); break; }
389 if(spr==chud_ppc_sprg1) { mfspr(val, chud_ppc_sprg1); break; }
390 if(spr==chud_ppc_sprg2) { mfspr(val, chud_ppc_sprg2); break; }
391 if(spr==chud_ppc_sprg3) { mfspr(val, chud_ppc_sprg3); break; }
392 if(spr==chud_ppc_ear) { mfspr(val, chud_ppc_ear); break; }
393 if(spr==chud_ppc_tbl) { mfspr(val, 268); break; } /* timebase consists of read registers and write registers */
394 if(spr==chud_ppc_tbu) { mfspr(val, 269); break; }
395 if(spr==chud_ppc_pvr) { mfspr(val, chud_ppc_pvr); break; }
396 if(spr==chud_ppc_ibat0u) { mfspr(val, chud_ppc_ibat0u); break; }
397 if(spr==chud_ppc_ibat0l) { mfspr(val, chud_ppc_ibat0l); break; }
398 if(spr==chud_ppc_ibat1u) { mfspr(val, chud_ppc_ibat1u); break; }
399 if(spr==chud_ppc_ibat1l) { mfspr(val, chud_ppc_ibat1l); break; }
400 if(spr==chud_ppc_ibat2u) { mfspr(val, chud_ppc_ibat2u); break; }
401 if(spr==chud_ppc_ibat2l) { mfspr(val, chud_ppc_ibat2l); break; }
402 if(spr==chud_ppc_ibat3u) { mfspr(val, chud_ppc_ibat3u); break; }
403 if(spr==chud_ppc_ibat3l) { mfspr(val, chud_ppc_ibat3l); break; }
404 if(spr==chud_ppc_dbat0u) { mfspr(val, chud_ppc_dbat0u); break; }
405 if(spr==chud_ppc_dbat0l) { mfspr(val, chud_ppc_dbat0l); break; }
406 if(spr==chud_ppc_dbat1u) { mfspr(val, chud_ppc_dbat1u); break; }
407 if(spr==chud_ppc_dbat1l) { mfspr(val, chud_ppc_dbat1l); break; }
408 if(spr==chud_ppc_dbat2u) { mfspr(val, chud_ppc_dbat2u); break; }
409 if(spr==chud_ppc_dbat2l) { mfspr(val, chud_ppc_dbat2l); break; }
410 if(spr==chud_ppc_dbat3u) { mfspr(val, chud_ppc_dbat3u); break; }
411 if(spr==chud_ppc_dbat3l) { mfspr(val, chud_ppc_dbat3l); break; }
412 if(spr==chud_ppc_dabr) { mfspr(val, chud_ppc_dabr); break; }
413 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
414 struct ppc_thread_state64 state;
415 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
416 kern_return_t kr;
417 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
418 if(KERN_SUCCESS==kr) {
419 val = state.srr1;
420 } else {
421 retval = KERN_FAILURE;
422 }
423 break;
424 }
425
426 /* PPC SPRs - 32-bit implementations */
427 if(spr==chud_ppc32_sr0) { mfsr(val, 0); break; }
428 if(spr==chud_ppc32_sr1) { mfsr(val, 1); break; }
429 if(spr==chud_ppc32_sr2) { mfsr(val, 2); break; }
430 if(spr==chud_ppc32_sr3) { mfsr(val, 3); break; }
431 if(spr==chud_ppc32_sr4) { mfsr(val, 4); break; }
432 if(spr==chud_ppc32_sr5) { mfsr(val, 5); break; }
433 if(spr==chud_ppc32_sr6) { mfsr(val, 6); break; }
434 if(spr==chud_ppc32_sr7) { mfsr(val, 7); break; }
435 if(spr==chud_ppc32_sr8) { mfsr(val, 8); break; }
436 if(spr==chud_ppc32_sr9) { mfsr(val, 9); break; }
437 if(spr==chud_ppc32_sr10) { mfsr(val, 10); break; }
438 if(spr==chud_ppc32_sr11) { mfsr(val, 11); break; }
439 if(spr==chud_ppc32_sr12) { mfsr(val, 12); break; }
440 if(spr==chud_ppc32_sr13) { mfsr(val, 13); break; }
441 if(spr==chud_ppc32_sr14) { mfsr(val, 14); break; }
442 if(spr==chud_ppc32_sr15) { mfsr(val, 15); break; }
443
444 /* PPC SPRs - 64-bit implementations */
445 if(spr==chud_ppc64_ctrl) { mfspr(val, chud_ppc64_ctrl); break; }
446
447 /* Implementation Specific SPRs */
448 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_750) {
449 if(spr==chud_750_mmcr0) { mfspr(val, chud_750_mmcr0); break; }
450 if(spr==chud_750_pmc1) { mfspr(val, chud_750_pmc1); break; }
451 if(spr==chud_750_pmc2) { mfspr(val, chud_750_pmc2); break; }
452 if(spr==chud_750_sia) { mfspr(val, chud_750_sia); break; }
453 if(spr==chud_750_mmcr1) { mfspr(val, chud_750_mmcr1); break; }
454 if(spr==chud_750_pmc3) { mfspr(val, chud_750_pmc3); break; }
455 if(spr==chud_750_pmc4) { mfspr(val, chud_750_pmc4); break; }
456 if(spr==chud_750_hid0) { mfspr(val, chud_750_hid0); break; }
457 if(spr==chud_750_hid1) { mfspr(val, chud_750_hid1); break; }
458 if(spr==chud_750_iabr) { mfspr(val, chud_750_iabr); break; }
459 if(spr==chud_750_ictc) { mfspr(val, chud_750_ictc); break; }
460 if(spr==chud_750_thrm1) { mfspr(val, chud_750_thrm1); break; }
461 if(spr==chud_750_thrm2) { mfspr(val, chud_750_thrm2); break; }
462 if(spr==chud_750_thrm3) { mfspr(val, chud_750_thrm3); break; }
463 if(spr==chud_750_l2cr) { mfspr(val, chud_750_l2cr); break; }
464
465 // 750FX only
466 if(spr==chud_750fx_ibat4u) { mfspr(val, chud_750fx_ibat4u); break; }
467 if(spr==chud_750fx_ibat4l) { mfspr(val, chud_750fx_ibat4l); break; }
468 if(spr==chud_750fx_ibat5u) { mfspr(val, chud_750fx_ibat5u); break; }
469 if(spr==chud_750fx_ibat5l) { mfspr(val, chud_750fx_ibat5l); break; }
470 if(spr==chud_750fx_ibat6u) { mfspr(val, chud_750fx_ibat6u); break; }
471 if(spr==chud_750fx_ibat6l) { mfspr(val, chud_750fx_ibat6l); break; }
472 if(spr==chud_750fx_ibat7u) { mfspr(val, chud_750fx_ibat7u); break; }
473 if(spr==chud_750fx_ibat7l) { mfspr(val, chud_750fx_ibat7l); break; }
474 if(spr==chud_750fx_dbat4u) { mfspr(val, chud_750fx_dbat4u); break; }
475 if(spr==chud_750fx_dbat4l) { mfspr(val, chud_750fx_dbat4l); break; }
476 if(spr==chud_750fx_dbat5u) { mfspr(val, chud_750fx_dbat5u); break; }
477 if(spr==chud_750fx_dbat5l) { mfspr(val, chud_750fx_dbat5l); break; }
478 if(spr==chud_750fx_dbat6u) { mfspr(val, chud_750fx_dbat6u); break; }
479 if(spr==chud_750fx_dbat6l) { mfspr(val, chud_750fx_dbat6l); break; }
480 if(spr==chud_750fx_dbat7u) { mfspr(val, chud_750fx_dbat7u); break; }
481 if(spr==chud_750fx_dbat7l) { mfspr(val, chud_750fx_dbat7l); break; }
482
483 // 750FX >= DDR2.x only
484 if(spr==chud_750fx_hid2) { mfspr(val, chud_750fx_hid2); break; }
485 }
486
487 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7400) {
488 if(spr==chud_7400_mmcr2) { mfspr(val, chud_7400_mmcr2); break; }
489 if(spr==chud_7400_bamr) { mfspr(val, chud_7400_bamr); break; }
490 if(spr==chud_7400_mmcr0) { mfspr(val, chud_7400_mmcr0); break; }
491 if(spr==chud_7400_pmc1) { mfspr(val, chud_7400_pmc1); break; }
492 if(spr==chud_7400_pmc2) { mfspr(val, chud_7400_pmc2); break; }
493 if(spr==chud_7400_siar) { mfspr(val, chud_7400_siar); break; }
494 if(spr==chud_7400_mmcr1) { mfspr(val, chud_7400_mmcr1); break; }
495 if(spr==chud_7400_pmc3) { mfspr(val, chud_7400_pmc3); break; }
496 if(spr==chud_7400_pmc4) { mfspr(val, chud_7400_pmc4); break; }
497 if(spr==chud_7400_hid0) { mfspr(val, chud_7400_hid0); break; }
498 if(spr==chud_7400_hid1) { mfspr(val, chud_7400_hid1); break; }
499 if(spr==chud_7400_iabr) { mfspr(val, chud_7400_iabr); break; }
500 if(spr==chud_7400_msscr0) { mfspr(val, chud_7400_msscr0); break; }
501 if(spr==chud_7400_msscr1) { mfspr(val, chud_7400_msscr1); break; } /* private */
502 if(spr==chud_7400_ictc) { mfspr(val, chud_7400_ictc); break; }
503 if(spr==chud_7400_thrm1) { mfspr(val, chud_7400_thrm1); break; }
504 if(spr==chud_7400_thrm2) { mfspr(val, chud_7400_thrm2); break; }
505 if(spr==chud_7400_thrm3) { mfspr(val, chud_7400_thrm3); break; }
506 if(spr==chud_7400_pir) { mfspr(val, chud_7400_pir); break; }
507 if(spr==chud_7400_l2cr) { mfspr(val, chud_7400_l2cr); break; }
508
509 // 7410 only
510 if(spr==chud_7410_l2pmcr) { mfspr(val, chud_7410_l2pmcr); break; }
511 }
512
513 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7450) {
514 if(spr==chud_7450_mmcr2) { mfspr(val, chud_7450_mmcr2); break; }
515 if(spr==chud_7450_pmc5) { mfspr(val, chud_7450_pmc5); break; }
516 if(spr==chud_7450_pmc6) { mfspr(val, chud_7450_pmc6); break; }
517 if(spr==chud_7450_bamr) { mfspr(val, chud_7450_bamr); break; }
518 if(spr==chud_7450_mmcr0) { mfspr(val, chud_7450_mmcr0); break; }
519 if(spr==chud_7450_pmc1) { mfspr(val, chud_7450_pmc1); break; }
520 if(spr==chud_7450_pmc2) { mfspr(val, chud_7450_pmc2); break; }
521 if(spr==chud_7450_siar) { mfspr(val, chud_7450_siar); break; }
522 if(spr==chud_7450_mmcr1) { mfspr(val, chud_7450_mmcr1); break; }
523 if(spr==chud_7450_pmc3) { mfspr(val, chud_7450_pmc3); break; }
524 if(spr==chud_7450_pmc4) { mfspr(val, chud_7450_pmc4); break; }
525 if(spr==chud_7450_tlbmiss) { mfspr(val, chud_7450_tlbmiss); break; }
526 if(spr==chud_7450_ptehi) { mfspr(val, chud_7450_ptehi); break; }
527 if(spr==chud_7450_ptelo) { mfspr(val, chud_7450_ptelo); break; }
528 if(spr==chud_7450_l3pm) { mfspr(val, chud_7450_l3pm); break; }
529 if(spr==chud_7450_hid0) { mfspr(val, chud_7450_hid0); break; }
530 if(spr==chud_7450_hid1) { mfspr(val, chud_7450_hid1); break; }
531 if(spr==chud_7450_iabr) { mfspr(val, chud_7450_iabr); break; }
532 if(spr==chud_7450_ldstdb) { mfspr(val, chud_7450_ldstdb); break; }
533 if(spr==chud_7450_msscr0) { mfspr(val, chud_7450_msscr0); break; }
534 if(spr==chud_7450_msssr0) { mfspr(val, chud_7450_msssr0); break; }
535 if(spr==chud_7450_ldstcr) { mfspr(val, chud_7450_ldstcr); break; }
536 if(spr==chud_7450_ictc) { mfspr(val, chud_7450_ictc); break; }
537 if(spr==chud_7450_ictrl) { mfspr(val, chud_7450_ictrl); break; }
538 if(spr==chud_7450_thrm1) { mfspr(val, chud_7450_thrm1); break; }
539 if(spr==chud_7450_thrm2) { mfspr(val, chud_7450_thrm2); break; }
540 if(spr==chud_7450_thrm3) { mfspr(val, chud_7450_thrm3); break; }
541 if(spr==chud_7450_pir) { mfspr(val, chud_7450_pir); break; }
542 if(spr==chud_7450_l2cr) { mfspr(val, chud_7450_l2cr); break; }
543 if(spr==chud_7450_l3cr) { mfspr(val, chud_7450_l3cr); break; }
544
545 // 7455/7457 only
546 if(spr==chud_7455_sprg4) { mfspr(val, chud_7455_sprg4); break; }
547 if(spr==chud_7455_sprg5) { mfspr(val, chud_7455_sprg5); break; }
548 if(spr==chud_7455_sprg6) { mfspr(val, chud_7455_sprg6); break; }
549 if(spr==chud_7455_sprg7) { mfspr(val, chud_7455_sprg7); break; }
550 if(spr==chud_7455_ibat4u) { mfspr(val, chud_7455_ibat4u); break; }
551 if(spr==chud_7455_ibat4l) { mfspr(val, chud_7455_ibat4l); break; }
552 if(spr==chud_7455_ibat5u) { mfspr(val, chud_7455_ibat5u); break; }
553 if(spr==chud_7455_ibat5l) { mfspr(val, chud_7455_ibat5l); break; }
554 if(spr==chud_7455_ibat6u) { mfspr(val, chud_7455_ibat6u); break; }
555 if(spr==chud_7455_ibat6l) { mfspr(val, chud_7455_ibat6l); break; }
556 if(spr==chud_7455_ibat7u) { mfspr(val, chud_7455_ibat7u); break; }
557 if(spr==chud_7455_ibat7l) { mfspr(val, chud_7455_ibat7l); break; }
558 if(spr==chud_7455_dbat4u) { mfspr(val, chud_7455_dbat4u); break; }
559 if(spr==chud_7455_dbat4l) { mfspr(val, chud_7455_dbat4l); break; }
560 if(spr==chud_7455_dbat5u) { mfspr(val, chud_7455_dbat5u); break; }
561 if(spr==chud_7455_dbat5l) { mfspr(val, chud_7455_dbat5l); break; }
562 if(spr==chud_7455_dbat6u) { mfspr(val, chud_7455_dbat6u); break; }
563 if(spr==chud_7455_dbat6l) { mfspr(val, chud_7455_dbat6l); break; }
564 if(spr==chud_7455_dbat7u) { mfspr(val, chud_7455_dbat7u); break; }
565 if(spr==chud_7455_dbat7l) { mfspr(val, chud_7455_dbat7l); break; }
566 }
567
568 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
569 if(spr==chud_970_pir) { mfspr(val, chud_970_pir); break; }
570 if(spr==chud_970_pmc1) { mfspr(val, chud_970_pmc1); break; }
571 if(spr==chud_970_pmc2) { mfspr(val, chud_970_pmc2); break; }
572 if(spr==chud_970_pmc3) { mfspr(val, chud_970_pmc3); break; }
573 if(spr==chud_970_pmc4) { mfspr(val, chud_970_pmc4); break; }
574 if(spr==chud_970_pmc5) { mfspr(val, chud_970_pmc5); break; }
575 if(spr==chud_970_pmc6) { mfspr(val, chud_970_pmc6); break; }
576 if(spr==chud_970_pmc7) { mfspr(val, chud_970_pmc7); break; }
577 if(spr==chud_970_pmc8) { mfspr(val, chud_970_pmc8); break; }
578 if(spr==chud_970_hdec) { mfspr(val, chud_970_hdec); break; }
579 }
580
581 /* we only get here if none of the above cases qualify */
582 retval = KERN_INVALID_ARGUMENT;
583 } while(0);
584
585 chudxnu_set_interrupts_enabled(oldlevel); /* enable interrupts */
586
587 if(cpu>=0) { // cpu<0 means don't bind
588 chudxnu_unbind_thread(current_thread());
589 }
590
591 *val_p = val;
592
593 return retval;
594 }
595
596 __private_extern__
597 kern_return_t chudxnu_read_spr64(int cpu, int spr, uint64_t *val_p)
598 {
599 kern_return_t retval = KERN_SUCCESS;
600 boolean_t oldlevel;
601
602 /* bind to requested CPU */
603 if(cpu>=0) { // cpu<0 means don't bind
604 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
605 return KERN_INVALID_ARGUMENT;
606 }
607 }
608
609 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
610
611 do {
612 /* PPC SPRs - 32-bit and 64-bit implementations */
613 if(spr==chud_ppc_srr0) { retval = mfspr64(val_p, chud_ppc_srr0); break; }
614 if(spr==chud_ppc_srr1) { retval = mfspr64(val_p, chud_ppc_srr1); break; }
615 if(spr==chud_ppc_dar) { retval = mfspr64(val_p, chud_ppc_dar); break; }
616 if(spr==chud_ppc_dsisr) { retval = mfspr64(val_p, chud_ppc_dsisr); break; }
617 if(spr==chud_ppc_sdr1) { retval = mfspr64(val_p, chud_ppc_sdr1); break; }
618 if(spr==chud_ppc_sprg0) { retval = mfspr64(val_p, chud_ppc_sprg0); break; }
619 if(spr==chud_ppc_sprg1) { retval = mfspr64(val_p, chud_ppc_sprg1); break; }
620 if(spr==chud_ppc_sprg2) { retval = mfspr64(val_p, chud_ppc_sprg2); break; }
621 if(spr==chud_ppc_sprg3) { retval = mfspr64(val_p, chud_ppc_sprg3); break; }
622 if(spr==chud_ppc_dabr) { retval = mfspr64(val_p, chud_ppc_dabr); break; }
623 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
624 struct ppc_thread_state64 state;
625 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
626 kern_return_t kr;
627 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
628 if(KERN_SUCCESS==kr) {
629 *val_p = state.srr1;
630 } else {
631 retval = KERN_FAILURE;
632 }
633 break;
634 }
635
636 /* PPC SPRs - 64-bit implementations */
637 if(spr==chud_ppc64_asr) { retval = mfspr64(val_p, chud_ppc64_asr); break; }
638 if(spr==chud_ppc64_accr) { retval = mfspr64(val_p, chud_ppc64_accr); break; }
639
640 /* Implementation Specific SPRs */
641 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
642 if(spr==chud_970_hid0) { retval = mfspr64(val_p, chud_970_hid0); break; }
643 if(spr==chud_970_hid1) { retval = mfspr64(val_p, chud_970_hid1); break; }
644 if(spr==chud_970_hid4) { retval = mfspr64(val_p, chud_970_hid4); break; }
645 if(spr==chud_970_hid5) { retval = mfspr64(val_p, chud_970_hid5); break; }
646 if(spr==chud_970_mmcr0) { retval = mfspr64(val_p, chud_970_mmcr0); break; }
647 if(spr==chud_970_mmcr1) { retval = mfspr64(val_p, chud_970_mmcr1); break; }
648 if(spr==chud_970_mmcra) { retval = mfspr64(val_p, chud_970_mmcra); break; }
649 if(spr==chud_970_siar) { retval = mfspr64(val_p, chud_970_siar); break; }
650 if(spr==chud_970_sdar) { retval = mfspr64(val_p, chud_970_sdar); break; }
651 if(spr==chud_970_imc) { retval = mfspr64(val_p, chud_970_imc); break; }
652 if(spr==chud_970_rmor) { retval = mfspr64(val_p, chud_970_rmor); break; }
653 if(spr==chud_970_hrmor) { retval = mfspr64(val_p, chud_970_hrmor); break; }
654 if(spr==chud_970_hior) { retval = mfspr64(val_p, chud_970_hior); break; }
655 if(spr==chud_970_lpidr) { retval = mfspr64(val_p, chud_970_lpidr); break; }
656 if(spr==chud_970_lpcr) { retval = mfspr64(val_p, chud_970_lpcr); break; }
657 if(spr==chud_970_dabrx) { retval = mfspr64(val_p, chud_970_dabrx); break; }
658 if(spr==chud_970_hsprg0) { retval = mfspr64(val_p, chud_970_hsprg0); break; }
659 if(spr==chud_970_hsprg1) { retval = mfspr64(val_p, chud_970_hsprg1); break; }
660 if(spr==chud_970_hsrr0) { retval = mfspr64(val_p, chud_970_hsrr0); break; }
661 if(spr==chud_970_hsrr1) { retval = mfspr64(val_p, chud_970_hsrr1); break; }
662 if(spr==chud_970_hdec) { retval = mfspr64(val_p, chud_970_hdec); break; }
663 if(spr==chud_970_trig0) { retval = mfspr64(val_p, chud_970_trig0); break; }
664 if(spr==chud_970_trig1) { retval = mfspr64(val_p, chud_970_trig1); break; }
665 if(spr==chud_970_trig2) { retval = mfspr64(val_p, chud_970_trig2); break; }
666 if(spr==chud_970_scomc) { retval = mfspr64(val_p, chud_970_scomc); break; }
667 if(spr==chud_970_scomd) { retval = mfspr64(val_p, chud_970_scomd); break; }
668 }
669
670 /* we only get here if none of the above cases qualify */
671 *val_p = 0xFFFFFFFFFFFFFFFFLL;
672 retval = KERN_INVALID_ARGUMENT;
673 } while(0);
674
675 chudxnu_set_interrupts_enabled(oldlevel); /* enable interrupts */
676
677 if(cpu>=0) { // cpu<0 means don't bind
678 chudxnu_unbind_thread(current_thread());
679 }
680
681 return retval;
682 }
683
684 __private_extern__
685 kern_return_t chudxnu_write_spr(int cpu, int spr, uint32_t val)
686 {
687 kern_return_t retval = KERN_SUCCESS;
688 boolean_t oldlevel;
689
690 /* bind to requested CPU */
691 if(cpu>=0) { // cpu<0 means don't bind
692 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
693 return KERN_INVALID_ARGUMENT;
694 }
695 }
696
697 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
698
699 do {
700 /* PPC SPRs - 32-bit and 64-bit implementations */
701 if(spr==chud_ppc_srr0) { mtspr(chud_ppc_srr0, val); break; }
702 if(spr==chud_ppc_srr1) { mtspr(chud_ppc_srr1, val); break; }
703 if(spr==chud_ppc_dsisr) { mtspr(chud_ppc_dsisr, val); break; }
704 if(spr==chud_ppc_dar) { mtspr(chud_ppc_dar, val); break; }
705 if(spr==chud_ppc_dec) { mtspr(chud_ppc_dec, val); break; }
706 if(spr==chud_ppc_sdr1) { mtspr(chud_ppc_sdr1, val); break; }
707 if(spr==chud_ppc_sprg0) { mtspr(chud_ppc_sprg0, val); break; }
708 if(spr==chud_ppc_sprg1) { mtspr(chud_ppc_sprg1, val); break; }
709 if(spr==chud_ppc_sprg2) { mtspr(chud_ppc_sprg2, val); break; }
710 if(spr==chud_ppc_sprg3) { mtspr(chud_ppc_sprg3, val); break; }
711 if(spr==chud_ppc_ear) { mtspr(chud_ppc_ear, val); break; }
712 if(spr==chud_ppc_tbl) { mtspr(284, val); break; } /* timebase consists of read registers and write registers */
713 if(spr==chud_ppc_tbu) { mtspr(285, val); break; }
714 if(spr==chud_ppc_pvr) { mtspr(chud_ppc_pvr, val); break; }
715 if(spr==chud_ppc_ibat0u) { mtspr(chud_ppc_ibat0u, val); break; }
716 if(spr==chud_ppc_ibat0l) { mtspr(chud_ppc_ibat0l, val); break; }
717 if(spr==chud_ppc_ibat1u) { mtspr(chud_ppc_ibat1u, val); break; }
718 if(spr==chud_ppc_ibat1l) { mtspr(chud_ppc_ibat1l, val); break; }
719 if(spr==chud_ppc_ibat2u) { mtspr(chud_ppc_ibat2u, val); break; }
720 if(spr==chud_ppc_ibat2l) { mtspr(chud_ppc_ibat2l, val); break; }
721 if(spr==chud_ppc_ibat3u) { mtspr(chud_ppc_ibat3u, val); break; }
722 if(spr==chud_ppc_ibat3l) { mtspr(chud_ppc_ibat3l, val); break; }
723 if(spr==chud_ppc_dbat0u) { mtspr(chud_ppc_dbat0u, val); break; }
724 if(spr==chud_ppc_dbat0l) { mtspr(chud_ppc_dbat0l, val); break; }
725 if(spr==chud_ppc_dbat1u) { mtspr(chud_ppc_dbat1u, val); break; }
726 if(spr==chud_ppc_dbat1l) { mtspr(chud_ppc_dbat1l, val); break; }
727 if(spr==chud_ppc_dbat2u) { mtspr(chud_ppc_dbat2u, val); break; }
728 if(spr==chud_ppc_dbat2l) { mtspr(chud_ppc_dbat2l, val); break; }
729 if(spr==chud_ppc_dbat3u) { mtspr(chud_ppc_dbat3u, val); break; }
730 if(spr==chud_ppc_dbat3l) { mtspr(chud_ppc_dbat3l, val); break; }
731 if(spr==chud_ppc_dabr) { mtspr(chud_ppc_dabr, val); break; }
732 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
733 struct ppc_thread_state64 state;
734 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
735 kern_return_t kr;
736 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
737 if(KERN_SUCCESS==kr) {
738 state.srr1 = val;
739 kr = chudxnu_thread_set_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, count, TRUE /* user only */);
740 if(KERN_SUCCESS!=kr) {
741 retval = KERN_FAILURE;
742 }
743 } else {
744 retval = KERN_FAILURE;
745 }
746 break;
747 }
748
749 /* PPC SPRs - 32-bit implementations */
750 if(spr==chud_ppc32_sr0) { mtsr(0, val); break; }
751 if(spr==chud_ppc32_sr1) { mtsr(1, val); break; }
752 if(spr==chud_ppc32_sr2) { mtsr(2, val); break; }
753 if(spr==chud_ppc32_sr3) { mtsr(3, val); break; }
754 if(spr==chud_ppc32_sr4) { mtsr(4, val); break; }
755 if(spr==chud_ppc32_sr5) { mtsr(5, val); break; }
756 if(spr==chud_ppc32_sr6) { mtsr(6, val); break; }
757 if(spr==chud_ppc32_sr7) { mtsr(7, val); break; }
758 if(spr==chud_ppc32_sr8) { mtsr(8, val); break; }
759 if(spr==chud_ppc32_sr9) { mtsr(9, val); break; }
760 if(spr==chud_ppc32_sr10) { mtsr(10, val); break; }
761 if(spr==chud_ppc32_sr11) { mtsr(11, val); break; }
762 if(spr==chud_ppc32_sr12) { mtsr(12, val); break; }
763 if(spr==chud_ppc32_sr13) { mtsr(13, val); break; }
764 if(spr==chud_ppc32_sr14) { mtsr(14, val); break; }
765 if(spr==chud_ppc32_sr15) { mtsr(15, val); break; }
766
767 /* Implementation Specific SPRs */
768 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_750) {
769 if(spr==chud_750_mmcr0) { mtspr(chud_750_mmcr0, val); break; }
770 if(spr==chud_750_pmc1) { mtspr(chud_750_pmc1, val); break; }
771 if(spr==chud_750_pmc2) { mtspr(chud_750_pmc2, val); break; }
772 if(spr==chud_750_sia) { mtspr(chud_750_sia, val); break; }
773 if(spr==chud_750_mmcr1) { mtspr(chud_750_mmcr1, val); break; }
774 if(spr==chud_750_pmc3) { mtspr(chud_750_pmc3, val); break; }
775 if(spr==chud_750_pmc4) { mtspr(chud_750_pmc4, val); break; }
776 if(spr==chud_750_iabr) { mtspr(chud_750_iabr, val); break; }
777 if(spr==chud_750_ictc) { mtspr(chud_750_ictc, val); break; }
778 if(spr==chud_750_thrm1) { mtspr(chud_750_thrm1, val); break; }
779 if(spr==chud_750_thrm2) { mtspr(chud_750_thrm2, val); break; }
780 if(spr==chud_750_thrm3) { mtspr(chud_750_thrm3, val); break; }
781 if(spr==chud_750_l2cr) {
782 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
783 break;
784 }
785 if(spr==chud_750_hid0) {
786 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
787 break;
788 }
789 if(spr==chud_750_hid1) {
790 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
791 break;
792 }
793
794 // 750FX only
795 if(spr==chud_750fx_ibat4u) { mtspr(chud_750fx_ibat4u, val); break; }
796 if(spr==chud_750fx_ibat4l) { mtspr(chud_750fx_ibat4l, val); break; }
797 if(spr==chud_750fx_ibat5u) { mtspr(chud_750fx_ibat5u, val); break; }
798 if(spr==chud_750fx_ibat5l) { mtspr(chud_750fx_ibat5l, val); break; }
799 if(spr==chud_750fx_ibat6u) { mtspr(chud_750fx_ibat6u, val); break; }
800 if(spr==chud_750fx_ibat6l) { mtspr(chud_750fx_ibat6l, val); break; }
801 if(spr==chud_750fx_ibat7u) { mtspr(chud_750fx_ibat7u, val); break; }
802 if(spr==chud_750fx_ibat7l) { mtspr(chud_750fx_ibat7l, val); break; }
803 if(spr==chud_750fx_dbat4u) { mtspr(chud_750fx_dbat4u, val); break; }
804 if(spr==chud_750fx_dbat4l) { mtspr(chud_750fx_dbat4l, val); break; }
805 if(spr==chud_750fx_dbat5u) { mtspr(chud_750fx_dbat5u, val); break; }
806 if(spr==chud_750fx_dbat5l) { mtspr(chud_750fx_dbat5l, val); break; }
807 if(spr==chud_750fx_dbat6u) { mtspr(chud_750fx_dbat6u, val); break; }
808 if(spr==chud_750fx_dbat6l) { mtspr(chud_750fx_dbat6l, val); break; }
809 if(spr==chud_750fx_dbat7u) { mtspr(chud_750fx_dbat7u, val); break; }
810 if(spr==chud_750fx_dbat7l) { mtspr(chud_750fx_dbat7l, val); break; }
811
812 // 750FX >= DDR2.x
813 if(spr==chud_750fx_hid2) { mtspr(chud_750fx_hid2, val); break; }
814 }
815
816 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7400) {
817 if(spr==chud_7400_mmcr2) { mtspr(chud_7400_mmcr2, val); break; }
818 if(spr==chud_7400_bamr) { mtspr(chud_7400_bamr, val); break; }
819 if(spr==chud_7400_mmcr0) { mtspr(chud_7400_mmcr0, val); break; }
820 if(spr==chud_7400_pmc1) { mtspr(chud_7400_pmc1, val); break; }
821 if(spr==chud_7400_pmc2) { mtspr(chud_7400_pmc2, val); break; }
822 if(spr==chud_7400_siar) { mtspr(chud_7400_siar, val); break; }
823 if(spr==chud_7400_mmcr1) { mtspr(chud_7400_mmcr1, val); break; }
824 if(spr==chud_7400_pmc3) { mtspr(chud_7400_pmc3, val); break; }
825 if(spr==chud_7400_pmc4) { mtspr(chud_7400_pmc4, val); break; }
826 if(spr==chud_7400_iabr) { mtspr(chud_7400_iabr, val); break; }
827 if(spr==chud_7400_ictc) { mtspr(chud_7400_ictc, val); break; }
828 if(spr==chud_7400_thrm1) { mtspr(chud_7400_thrm1, val); break; }
829 if(spr==chud_7400_thrm2) { mtspr(chud_7400_thrm2, val); break; }
830 if(spr==chud_7400_thrm3) { mtspr(chud_7400_thrm3, val); break; }
831 if(spr==chud_7400_pir) { mtspr(chud_7400_pir, val); break; }
832
833 if(spr==chud_7400_l2cr) {
834 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
835 break;
836 }
837 if(spr==chud_7400_hid0) {
838 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
839 break;
840 }
841 if(spr==chud_7400_hid1) {
842 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
843 break;
844 }
845 if(spr==chud_7400_msscr0) {
846 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
847 break;
848 }
849 if(spr==chud_7400_msscr1) { /* private */
850 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
851 break;
852 }
853
854 // 7410 only
855 if(spr==chud_7410_l2pmcr) { mtspr(chud_7410_l2pmcr, val); break; }
856 }
857
858 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7450) {
859 if(spr==chud_7450_mmcr2) { mtspr(chud_7450_mmcr2, val); break; }
860 if(spr==chud_7450_pmc5) { mtspr(chud_7450_pmc5, val); break; }
861 if(spr==chud_7450_pmc6) { mtspr(chud_7450_pmc6, val); break; }
862 if(spr==chud_7450_bamr) { mtspr(chud_7450_bamr, val); break; }
863 if(spr==chud_7450_mmcr0) { mtspr(chud_7450_mmcr0, val); break; }
864 if(spr==chud_7450_pmc1) { mtspr(chud_7450_pmc1, val); break; }
865 if(spr==chud_7450_pmc2) { mtspr(chud_7450_pmc2, val); break; }
866 if(spr==chud_7450_siar) { mtspr(chud_7450_siar, val); break; }
867 if(spr==chud_7450_mmcr1) { mtspr(chud_7450_mmcr1, val); break; }
868 if(spr==chud_7450_pmc3) { mtspr(chud_7450_pmc3, val); break; }
869 if(spr==chud_7450_pmc4) { mtspr(chud_7450_pmc4, val); break; }
870 if(spr==chud_7450_tlbmiss) { mtspr(chud_7450_tlbmiss, val); break; }
871 if(spr==chud_7450_ptehi) { mtspr(chud_7450_ptehi, val); break; }
872 if(spr==chud_7450_ptelo) { mtspr(chud_7450_ptelo, val); break; }
873 if(spr==chud_7450_l3pm) { mtspr(chud_7450_l3pm, val); break; }
874 if(spr==chud_7450_iabr) { mtspr(chud_7450_iabr, val); break; }
875 if(spr==chud_7450_ldstdb) { mtspr(chud_7450_ldstdb, val); break; }
876 if(spr==chud_7450_ictc) { mtspr(chud_7450_ictc, val); break; }
877 if(spr==chud_7450_thrm1) { mtspr(chud_7450_thrm1, val); break; }
878 if(spr==chud_7450_thrm2) { mtspr(chud_7450_thrm2, val); break; }
879 if(spr==chud_7450_thrm3) { mtspr(chud_7450_thrm3, val); break; }
880 if(spr==chud_7450_pir) { mtspr(chud_7450_pir, val); break; }
881
882 if(spr==chud_7450_l2cr) {
883 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
884 break;
885 }
886
887 if(spr==chud_7450_l3cr) {
888 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
889 break;
890 }
891 if(spr==chud_7450_ldstcr) {
892 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
893 break;
894 }
895 if(spr==chud_7450_hid0) {
896 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
897 break;
898 }
899 if(spr==chud_7450_hid1) {
900 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
901 break;
902 }
903 if(spr==chud_7450_msscr0) {
904 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
905 break;
906 }
907 if(spr==chud_7450_msssr0) {
908 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
909 break;
910 }
911 if(spr==chud_7450_ictrl) {
912 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
913 break;
914 }
915
916 // 7455/7457 only
917 if(spr==chud_7455_sprg4) { mtspr(chud_7455_sprg4, val); break; }
918 if(spr==chud_7455_sprg5) { mtspr(chud_7455_sprg5, val); break; }
919 if(spr==chud_7455_sprg6) { mtspr(chud_7455_sprg6, val); break; }
920 if(spr==chud_7455_sprg7) { mtspr(chud_7455_sprg7, val); break; }
921 if(spr==chud_7455_ibat4u) { mtspr(chud_7455_ibat4u, val); break; }
922 if(spr==chud_7455_ibat4l) { mtspr(chud_7455_ibat4l, val); break; }
923 if(spr==chud_7455_ibat5u) { mtspr(chud_7455_ibat5u, val); break; }
924 if(spr==chud_7455_ibat5l) { mtspr(chud_7455_ibat5l, val); break; }
925 if(spr==chud_7455_ibat6u) { mtspr(chud_7455_ibat6u, val); break; }
926 if(spr==chud_7455_ibat6l) { mtspr(chud_7455_ibat6l, val); break; }
927 if(spr==chud_7455_ibat7u) { mtspr(chud_7455_ibat7u, val); break; }
928 if(spr==chud_7455_ibat7l) { mtspr(chud_7455_ibat7l, val); break; }
929 if(spr==chud_7455_dbat4u) { mtspr(chud_7455_dbat4u, val); break; }
930 if(spr==chud_7455_dbat4l) { mtspr(chud_7455_dbat4l, val); break; }
931 if(spr==chud_7455_dbat5u) { mtspr(chud_7455_dbat5u, val); break; }
932 if(spr==chud_7455_dbat5l) { mtspr(chud_7455_dbat5l, val); break; }
933 if(spr==chud_7455_dbat6u) { mtspr(chud_7455_dbat6u, val); break; }
934 if(spr==chud_7455_dbat6l) { mtspr(chud_7455_dbat6l, val); break; }
935 if(spr==chud_7455_dbat7u) { mtspr(chud_7455_dbat7u, val); break; }
936 if(spr==chud_7455_dbat7l) { mtspr(chud_7455_dbat7l, val); break; }
937 }
938
939 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
940 if(spr==chud_970_pir) { mtspr(chud_970_pir, val); break; }
941 if(spr==chud_970_pmc1) { mtspr(chud_970_pmc1, val); break; }
942 if(spr==chud_970_pmc2) { mtspr(chud_970_pmc2, val); break; }
943 if(spr==chud_970_pmc3) { mtspr(chud_970_pmc3, val); break; }
944 if(spr==chud_970_pmc4) { mtspr(chud_970_pmc4, val); break; }
945 if(spr==chud_970_pmc5) { mtspr(chud_970_pmc5, val); break; }
946 if(spr==chud_970_pmc6) { mtspr(chud_970_pmc6, val); break; }
947 if(spr==chud_970_pmc7) { mtspr(chud_970_pmc7, val); break; }
948 if(spr==chud_970_pmc8) { mtspr(chud_970_pmc8, val); break; }
949 if(spr==chud_970_hdec) { mtspr(chud_970_hdec, val); break; }
950 }
951
952 /* we only get here if none of the above cases qualify */
953 retval = KERN_INVALID_ARGUMENT;
954 } while(0);
955
956 chudxnu_set_interrupts_enabled(oldlevel); /* re-enable interrupts */
957
958 if(cpu>=0) { // cpu<0 means don't bind
959 chudxnu_unbind_thread(current_thread());
960 }
961
962 return retval;
963 }
964
965 __private_extern__
966 kern_return_t chudxnu_write_spr64(int cpu, int spr, uint64_t val)
967 {
968 kern_return_t retval = KERN_SUCCESS;
969 boolean_t oldlevel;
970 uint64_t *val_p = &val;
971
972 /* bind to requested CPU */
973 if(cpu>=0) { // cpu<0 means don't bind
974 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
975 return KERN_INVALID_ARGUMENT;
976 }
977 }
978
979 oldlevel = ml_set_interrupts_enabled(FALSE); /* disable interrupts */
980
981 do {
982 /* PPC SPRs - 32-bit and 64-bit implementations */
983 if(spr==chud_ppc_srr0) { retval = mtspr64(chud_ppc_srr0, val_p); break; }
984 if(spr==chud_ppc_srr1) { retval = mtspr64(chud_ppc_srr1, val_p); break; }
985 if(spr==chud_ppc_dar) { retval = mtspr64(chud_ppc_dar, val_p); break; }
986 if(spr==chud_ppc_dsisr) { retval = mtspr64(chud_ppc_dsisr, val_p); break; }
987 if(spr==chud_ppc_sdr1) { retval = mtspr64(chud_ppc_sdr1, val_p); break; }
988 if(spr==chud_ppc_sprg0) { retval = mtspr64(chud_ppc_sprg0, val_p); break; }
989 if(spr==chud_ppc_sprg1) { retval = mtspr64(chud_ppc_sprg1, val_p); break; }
990 if(spr==chud_ppc_sprg2) { retval = mtspr64(chud_ppc_sprg2, val_p); break; }
991 if(spr==chud_ppc_sprg3) { retval = mtspr64(chud_ppc_sprg3, val_p); break; }
992 if(spr==chud_ppc_dabr) { retval = mtspr64(chud_ppc_dabr, val_p); break; }
993 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
994 struct ppc_thread_state64 state;
995 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
996 kern_return_t kr;
997 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
998 if(KERN_SUCCESS==kr) {
999 state.srr1 = val;
1000 kr = chudxnu_thread_set_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, count, TRUE /* user only */);
1001 if(KERN_SUCCESS!=kr) {
1002 retval = KERN_FAILURE;
1003 }
1004 } else {
1005 retval = KERN_FAILURE;
1006 }
1007 break;
1008 }
1009
1010 /* PPC SPRs - 64-bit implementations */
1011 if(spr==chud_ppc64_asr) { retval = mtspr64(chud_ppc64_asr, val_p); break; }
1012 if(spr==chud_ppc64_accr) { retval = mtspr64(chud_ppc64_accr, val_p); break; }
1013 if(spr==chud_ppc64_ctrl) { retval = mtspr64(chud_ppc64_ctrl, val_p); break; }
1014
1015 /* Implementation Specific SPRs */
1016 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
1017 if(spr==chud_970_hid0) { retval = mtspr64(chud_970_hid0, val_p); break; }
1018 if(spr==chud_970_hid1) { retval = mtspr64(chud_970_hid1, val_p); break; }
1019 if(spr==chud_970_hid4) { retval = mtspr64(chud_970_hid4, val_p); break; }
1020 if(spr==chud_970_hid5) { retval = mtspr64(chud_970_hid5, val_p); break; }
1021 if(spr==chud_970_mmcr0) { retval = mtspr64(chud_970_mmcr0, val_p); break; }
1022 if(spr==chud_970_mmcr1) { retval = mtspr64(chud_970_mmcr1, val_p); break; }
1023 if(spr==chud_970_mmcra) { retval = mtspr64(chud_970_mmcra, val_p); break; }
1024 if(spr==chud_970_siar) { retval = mtspr64(chud_970_siar, val_p); break; }
1025 if(spr==chud_970_sdar) { retval = mtspr64(chud_970_sdar, val_p); break; }
1026 if(spr==chud_970_imc) { retval = mtspr64(chud_970_imc, val_p); break; }
1027
1028 if(spr==chud_970_rmor) { retval = mtspr64(chud_970_rmor, val_p); break; }
1029 if(spr==chud_970_hrmor) { retval = mtspr64(chud_970_hrmor, val_p); break; }
1030 if(spr==chud_970_hior) { retval = mtspr64(chud_970_hior, val_p); break; }
1031 if(spr==chud_970_lpidr) { retval = mtspr64(chud_970_lpidr, val_p); break; }
1032 if(spr==chud_970_lpcr) { retval = mtspr64(chud_970_lpcr, val_p); break; }
1033 if(spr==chud_970_dabrx) { retval = mtspr64(chud_970_dabrx, val_p); break; }
1034
1035 if(spr==chud_970_hsprg0) { retval = mtspr64(chud_970_hsprg0, val_p); break; }
1036 if(spr==chud_970_hsprg1) { retval = mtspr64(chud_970_hsprg1, val_p); break; }
1037 if(spr==chud_970_hsrr0) { retval = mtspr64(chud_970_hsrr0, val_p); break; }
1038 if(spr==chud_970_hsrr1) { retval = mtspr64(chud_970_hsrr1, val_p); break; }
1039 if(spr==chud_970_hdec) { retval = mtspr64(chud_970_hdec, val_p); break; }
1040 if(spr==chud_970_trig0) { retval = mtspr64(chud_970_trig0, val_p); break; }
1041 if(spr==chud_970_trig1) { retval = mtspr64(chud_970_trig1, val_p); break; }
1042 if(spr==chud_970_trig2) { retval = mtspr64(chud_970_trig2, val_p); break; }
1043 if(spr==chud_970_scomc) { retval = mtspr64(chud_970_scomc, val_p); break; }
1044 if(spr==chud_970_scomd) { retval = mtspr64(chud_970_scomd, val_p); break; }
1045
1046 if(spr==chud_970_hid0) {
1047 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1048 break;
1049 }
1050
1051 if(spr==chud_970_hid1) {
1052 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1053 break;
1054 }
1055
1056 if(spr==chud_970_hid4) {
1057 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1058 break;
1059 }
1060
1061 if(spr==chud_970_hid5) {
1062 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1063 break;
1064 }
1065
1066 }
1067
1068 /* we only get here if none of the above cases qualify */
1069 retval = KERN_INVALID_ARGUMENT;
1070 } while(0);
1071
1072 chudxnu_set_interrupts_enabled(oldlevel); /* re-enable interrupts */
1073
1074 if(cpu>=0) { // cpu<0 means don't bind
1075 chudxnu_unbind_thread(current_thread());
1076 }
1077
1078 return retval;
1079 }
1080
1081 #pragma mark **** cache flush ****
1082
1083 __private_extern__
1084 void chudxnu_flush_caches(void)
1085 {
1086 cacheInit();
1087 }
1088
1089 __private_extern__
1090 void chudxnu_enable_caches(boolean_t enable)
1091 {
1092 if(!enable) {
1093 cacheInit();
1094 cacheDisable();
1095 } else {
1096 cacheInit();
1097 }
1098 }
1099
1100 #pragma mark **** perfmon facility ****
1101
1102 __private_extern__
1103 kern_return_t chudxnu_perfmon_acquire_facility(task_t task)
1104 {
1105 return perfmon_acquire_facility(task);
1106 }
1107
1108 __private_extern__
1109 kern_return_t chudxnu_perfmon_release_facility(task_t task)
1110 {
1111 return perfmon_release_facility(task);
1112 }
1113
1114 #pragma mark **** rupt counters ****
1115
1116 __private_extern__
1117 kern_return_t chudxnu_get_cpu_rupt_counters(int cpu, rupt_counters_t *rupts)
1118 {
1119 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
1120 return KERN_FAILURE;
1121 }
1122
1123 if(rupts) {
1124 boolean_t oldlevel = ml_set_interrupts_enabled(FALSE);
1125 struct per_proc_info *per_proc;
1126
1127 per_proc = PerProcTable[cpu].ppe_vaddr;
1128 rupts->hwResets = per_proc->hwCtr.hwResets;
1129 rupts->hwMachineChecks = per_proc->hwCtr.hwMachineChecks;
1130 rupts->hwDSIs = per_proc->hwCtr.hwDSIs;
1131 rupts->hwISIs = per_proc->hwCtr.hwISIs;
1132 rupts->hwExternals = per_proc->hwCtr.hwExternals;
1133 rupts->hwAlignments = per_proc->hwCtr.hwAlignments;
1134 rupts->hwPrograms = per_proc->hwCtr.hwPrograms;
1135 rupts->hwFloatPointUnavailable = per_proc->hwCtr.hwFloatPointUnavailable;
1136 rupts->hwDecrementers = per_proc->hwCtr.hwDecrementers;
1137 rupts->hwIOErrors = per_proc->hwCtr.hwIOErrors;
1138 rupts->hwSystemCalls = per_proc->hwCtr.hwSystemCalls;
1139 rupts->hwTraces = per_proc->hwCtr.hwTraces;
1140 rupts->hwFloatingPointAssists = per_proc->hwCtr.hwFloatingPointAssists;
1141 rupts->hwPerformanceMonitors = per_proc->hwCtr.hwPerformanceMonitors;
1142 rupts->hwAltivecs = per_proc->hwCtr.hwAltivecs;
1143 rupts->hwInstBreakpoints = per_proc->hwCtr.hwInstBreakpoints;
1144 rupts->hwSystemManagements = per_proc->hwCtr.hwSystemManagements;
1145 rupts->hwAltivecAssists = per_proc->hwCtr.hwAltivecAssists;
1146 rupts->hwThermal = per_proc->hwCtr.hwThermal;
1147 rupts->hwSoftPatches = per_proc->hwCtr.hwSoftPatches;
1148 rupts->hwMaintenances = per_proc->hwCtr.hwMaintenances;
1149 rupts->hwInstrumentations = per_proc->hwCtr.hwInstrumentations;
1150
1151 ml_set_interrupts_enabled(oldlevel);
1152 return KERN_SUCCESS;
1153 } else {
1154 return KERN_FAILURE;
1155 }
1156 }
1157
1158 __private_extern__
1159 kern_return_t chudxnu_clear_cpu_rupt_counters(int cpu)
1160 {
1161 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
1162 return KERN_FAILURE;
1163 }
1164
1165 bzero((char *)&(PerProcTable[cpu].ppe_vaddr->hwCtr), sizeof(struct hwCtrs));
1166 return KERN_SUCCESS;
1167 }
1168
1169 #pragma mark **** alignment exceptions ****
1170
1171 __private_extern__
1172 kern_return_t chudxnu_passup_alignment_exceptions(boolean_t enable)
1173 {
1174 if(enable) {
1175 dgWork.dgFlags |= enaNotifyEM;
1176 } else {
1177 dgWork.dgFlags &= ~enaNotifyEM;
1178 }
1179 return KERN_SUCCESS;
1180 }
1181
1182 #pragma mark **** scom ****
1183 kern_return_t chudxnu_scom_read(uint32_t reg, uint64_t *data)
1184 {
1185 ml_scom_read(reg, data);
1186 return KERN_SUCCESS;
1187 }
1188
1189 kern_return_t chudxnu_scom_write(uint32_t reg, uint64_t data)
1190 {
1191 ml_scom_write(reg, data);
1192 return KERN_SUCCESS;
1193 }
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