osfmk/chud/ppc/chud_cpu_asm.s

   1 /*
   2  * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_OSREFERENCE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License.  The rights granted to you under the
  10  * License may not be used to create, or enable the creation or
  11  * redistribution of, unlawful or unlicensed copies of an Apple operating
  12  * system, or to circumvent, violate, or enable the circumvention or
  13  * violation of, any terms of an Apple operating system software license
  14  * agreement.
  15  *
  16  * Please obtain a copy of the License at
  17  * http://www.opensource.apple.com/apsl/ and read it before using this
  18  * file.
  19  *
  20  * The Original Code and all software distributed under the License are
  21  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  22  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  23  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  25  * Please see the License for the specific language governing rights and
  26  * limitations under the License.
  27  *
  28  * @APPLE_LICENSE_OSREFERENCE_HEADER_END@
  29  */
  30
  31 #define ASSEMBLER
  32 #include <chud/ppc/chud_spr.h>
  33 #include <ppc/asm.h>
  34 #include <mach/kern_return.h>
  35
  36 /*
  37  * kern_return_t mfspr64(uint64_t *val, int spr);
  38  *
  39  * r3: address to store value in
  40  * r4: spr to read from
  41  *
  42  */
  43
  44 ;           Force a line boundry here
  45             .align  5
  46             .globl  EXT(mfspr64)
  47
  48 EXT(mfspr64):
  49             ;; generic PPC 64-bit wide SPRs
  50             cmpwi       r4,chud_ppc_srr0
  51             beq         mfspr64_srr0
  52             cmpwi       r4,chud_ppc_srr1
  53             beq         mfspr64_srr1
  54             cmpwi       r4,chud_ppc_dar
  55             beq         mfspr64_dar
  56             cmpwi       r4,chud_ppc_sdr1
  57             beq         mfspr64_sdr1
  58             cmpwi       r4,chud_ppc_sprg0
  59             beq         mfspr64_sprg0
  60             cmpwi       r4,chud_ppc_sprg1
  61             beq         mfspr64_sprg1
  62             cmpwi       r4,chud_ppc_sprg2
  63             beq         mfspr64_sprg2
  64             cmpwi       r4,chud_ppc_sprg3
  65             beq         mfspr64_sprg3
  66             cmpwi       r4,chud_ppc64_asr
  67             beq         mfspr64_asr
  68             cmpwi       r4,chud_ppc_dabr
  69             beq         mfspr64_dabr
  70
  71             ;; GPUL specific 64-bit wide SPRs
  72             cmpwi       r4,chud_970_hid0
  73             beq         mfspr64_hid0
  74             cmpwi       r4,chud_970_hid1
  75             beq         mfspr64_hid1
  76             cmpwi       r4,chud_970_hid4
  77             beq         mfspr64_hid4
  78             cmpwi       r4,chud_970_hid5
  79             beq         mfspr64_hid5
  80             cmpwi       r4,chud_970_mmcr0
  81             beq         mfspr64_mmcr0
  82             cmpwi       r4,chud_970_mmcr1
  83             beq         mfspr64_mmcr1
  84             cmpwi       r4,chud_970_mmcra
  85             beq         mfspr64_mmcra
  86             cmpwi       r4,chud_970_siar
  87             beq         mfspr64_siar
  88             cmpwi       r4,chud_970_sdar
  89             beq         mfspr64_sdar
  90             cmpwi       r4,chud_970_imc
  91             beq         mfspr64_imc
  92             cmpwi       r4,chud_970_rmor
  93             beq         mfspr64_rmor
  94             cmpwi       r4,chud_970_hrmor
  95             beq         mfspr64_hrmor
  96             cmpwi       r4,chud_970_hior
  97             beq         mfspr64_hior
  98             cmpwi       r4,chud_970_lpidr
  99             beq         mfspr64_lpidr
 100             cmpwi       r4,chud_970_lpcr
 101             beq         mfspr64_lpcr
 102             cmpwi       r4,chud_970_dabrx
 103             beq         mfspr64_dabrx
 104             cmpwi       r4,chud_970_hsprg0
 105             beq         mfspr64_hsprg0
 106             cmpwi       r4,chud_970_hsprg1
 107             beq         mfspr64_hsprg1
 108             cmpwi       r4,chud_970_hsrr0
 109             beq         mfspr64_hsrr0
 110             cmpwi       r4,chud_970_hsrr1
 111             beq         mfspr64_hsrr1
 112             cmpwi       r4,chud_970_hdec
 113             beq         mfspr64_hdec
 114             cmpwi       r4,chud_970_trig0
 115             beq         mfspr64_trig0
 116             cmpwi       r4,chud_970_trig1
 117             beq         mfspr64_trig1
 118             cmpwi       r4,chud_970_trig2
 119             beq         mfspr64_trig2
 120             cmpwi       r4,chud_ppc64_accr
 121             beq         mfspr64_accr
 122             cmpwi       r4,chud_970_scomc
 123             beq         mfspr64_scomc
 124             cmpwi       r4,chud_970_scomd
 125             beq         mfspr64_scomd
 126
 127             b           mfspr64_failure
 128
 129 mfspr64_srr0:
 130             mfspr       r5,chud_ppc_srr0
 131             std         r5,0(r3)
 132             b           mfspr64_success
 133 mfspr64_srr1:
 134             mfspr       r5,chud_ppc_srr1
 135             std         r5,0(r3)
 136             b           mfspr64_success
 137 mfspr64_dar:
 138             mfspr       r5,chud_ppc_dar
 139             std         r5,0(r3)
 140             b           mfspr64_success
 141 mfspr64_sdr1:
 142             mfspr       r5,chud_ppc_sdr1
 143             std         r5,0(r3)
 144             b           mfspr64_success
 145 mfspr64_sprg0:
 146             mfspr       r5,chud_ppc_sprg0
 147             std         r5,0(r3)
 148             b           mfspr64_success
 149 mfspr64_sprg1:
 150             mfspr       r5,chud_ppc_sprg1
 151             std         r5,0(r3)
 152             b           mfspr64_success
 153 mfspr64_sprg2:
 154             mfspr       r5,chud_ppc_sprg2
 155             std         r5,0(r3)
 156             b           mfspr64_success
 157 mfspr64_sprg3:
 158             mfspr       r5,chud_ppc_sprg3
 159             std         r5,0(r3)
 160             b           mfspr64_success
 161 mfspr64_asr:
 162             mfspr       r5,chud_ppc64_asr
 163             std         r5,0(r3)
 164             b           mfspr64_success
 165 mfspr64_dabr:
 166             mfspr       r5,chud_ppc_dabr
 167             std         r5,0(r3)
 168             b           mfspr64_success
 169 mfspr64_hid0:
 170             mfspr       r5,chud_970_hid0
 171             std         r5,0(r3)
 172             b           mfspr64_success
 173 mfspr64_hid1:
 174             mfspr       r5,chud_970_hid1
 175             std         r5,0(r3)
 176             b           mfspr64_success
 177 mfspr64_hid4:
 178             mfspr       r5,chud_970_hid4
 179             std         r5,0(r3)
 180             b           mfspr64_success
 181 mfspr64_hid5:
 182             mfspr       r5,chud_970_hid5
 183             std         r5,0(r3)
 184             b           mfspr64_success
 185 mfspr64_mmcr0:
 186             mfspr       r5,chud_970_mmcr0
 187             std         r5,0(r3)
 188             b           mfspr64_success
 189 mfspr64_mmcr1:
 190             mfspr       r5,chud_970_mmcr1
 191             std         r5,0(r3)
 192             b           mfspr64_success
 193 mfspr64_mmcra:
 194             mfspr       r5,chud_970_mmcra
 195             std         r5,0(r3)
 196             b           mfspr64_success
 197 mfspr64_siar:
 198             mfspr       r5,chud_970_siar
 199             std         r5,0(r3)
 200             b           mfspr64_success
 201 mfspr64_sdar:
 202             mfspr       r5,chud_970_sdar
 203             std         r5,0(r3)
 204             b           mfspr64_success
 205 mfspr64_imc:
 206             mfspr       r5,chud_970_imc
 207             std         r5,0(r3)
 208             b           mfspr64_success
 209 mfspr64_rmor:
 210             mfspr       r5,chud_970_rmor
 211             std         r5,0(r3)
 212             b           mfspr64_success
 213 mfspr64_hrmor:
 214             mfspr       r5,chud_970_hrmor
 215             std         r5,0(r3)
 216             b           mfspr64_success
 217 mfspr64_hior:
 218             mfspr       r5,chud_970_hior
 219             std         r5,0(r3)
 220             b           mfspr64_success
 221 mfspr64_lpidr:
 222             mfspr       r5,chud_970_lpidr
 223             std         r5,0(r3)
 224             b           mfspr64_success
 225 mfspr64_lpcr:
 226             mfspr       r5,chud_970_lpcr
 227             std         r5,0(r3)
 228             b           mfspr64_success
 229 mfspr64_dabrx:
 230             mfspr       r5,chud_970_dabrx
 231             std         r5,0(r3)
 232             b           mfspr64_success
 233 mfspr64_hsprg0:
 234             mfspr       r5,chud_970_hsprg0
 235             std         r5,0(r3)
 236             b           mfspr64_success
 237 mfspr64_hsprg1:
 238             mfspr       r5,chud_970_hsprg1
 239             std         r5,0(r3)
 240             b           mfspr64_success
 241 mfspr64_hsrr0:
 242             mfspr       r5,chud_970_hsrr0
 243             std         r5,0(r3)
 244             b           mfspr64_success
 245 mfspr64_hsrr1:
 246             mfspr       r5,chud_970_hsrr1
 247             std         r5,0(r3)
 248             b           mfspr64_success
 249 mfspr64_hdec:
 250             mfspr       r5,chud_970_hdec
 251             std         r5,0(r3)
 252             b           mfspr64_success
 253 mfspr64_trig0:
 254             mfspr       r5,chud_970_trig0
 255             std         r5,0(r3)
 256             b           mfspr64_success
 257 mfspr64_trig1:
 258             mfspr       r5,chud_970_trig1
 259             std         r5,0(r3)
 260             b           mfspr64_success
 261 mfspr64_trig2:
 262             mfspr       r5,chud_970_trig2
 263             std         r5,0(r3)
 264             b           mfspr64_success
 265 mfspr64_accr:
 266             mfspr       r5,chud_ppc64_accr
 267             std         r5,0(r3)
 268             b           mfspr64_success
 269 mfspr64_scomc:
 270             mfspr       r5,chud_970_scomc
 271             std         r5,0(r3)
 272             b           mfspr64_success
 273 mfspr64_scomd:
 274             mfspr       r5,chud_970_scomd
 275             std         r5,0(r3)
 276             b           mfspr64_success
 277
 278 mfspr64_failure:
 279             li          r3,KERN_FAILURE
 280             blr
 281
 282 mfspr64_success:
 283             li          r3,KERN_SUCCESS
 284             blr
 285
 286
 287 /*
 288  * kern_return_t mtspr64(int spr, uint64_t *val);
 289  *
 290  * r3: spr to write to
 291  * r4: address to get value from
 292  *
 293  */
 294
 295 ;           Force a line boundry here
 296             .align  5
 297             .globl  EXT(mtspr64)
 298
 299 EXT(mtspr64):
 300             ;; generic PPC 64-bit wide SPRs
 301             cmpwi       r3,chud_ppc_srr0
 302             beq         mtspr64_srr0
 303             cmpwi       r3,chud_ppc_srr1
 304             beq         mtspr64_srr1
 305             cmpwi       r3,chud_ppc_dar
 306             beq         mtspr64_dar
 307             cmpwi       r3,chud_ppc_sdr1
 308             beq         mtspr64_sdr1
 309             cmpwi       r3,chud_ppc_sprg0
 310             beq         mtspr64_sprg0
 311             cmpwi       r3,chud_ppc_sprg1
 312             beq         mtspr64_sprg1
 313             cmpwi       r3,chud_ppc_sprg2
 314             beq         mtspr64_sprg2
 315             cmpwi       r3,chud_ppc_sprg3
 316             beq         mtspr64_sprg3
 317             cmpwi       r3,chud_ppc64_asr
 318             beq         mtspr64_asr
 319             cmpwi       r3,chud_ppc_dabr
 320             beq         mtspr64_dabr
 321
 322             ;; GPUL specific 64-bit wide SPRs
 323             cmpwi       r3,chud_970_hid0
 324             beq         mtspr64_hid0
 325             cmpwi       r3,chud_970_hid1
 326             beq         mtspr64_hid1
 327             cmpwi       r3,chud_970_hid4
 328             beq         mtspr64_hid4
 329             cmpwi       r3,chud_970_hid5
 330             beq         mtspr64_hid5
 331             cmpwi       r3,chud_970_mmcr0
 332             beq         mtspr64_mmcr0
 333             cmpwi       r3,chud_970_mmcr1
 334             beq         mtspr64_mmcr1
 335             cmpwi       r3,chud_970_mmcra
 336             beq         mtspr64_mmcra
 337             cmpwi       r3,chud_970_siar
 338             beq         mtspr64_siar
 339             cmpwi       r3,chud_970_sdar
 340             beq         mtspr64_sdar
 341             cmpwi       r3,chud_970_imc
 342             beq         mtspr64_imc
 343             cmpwi       r3,chud_970_rmor
 344             beq         mtspr64_rmor
 345             cmpwi       r3,chud_970_hrmor
 346             beq         mtspr64_hrmor
 347             cmpwi       r3,chud_970_hior
 348             beq         mtspr64_hior
 349             cmpwi       r3,chud_970_lpidr
 350             beq         mtspr64_lpidr
 351             cmpwi       r3,chud_970_lpcr
 352             beq         mtspr64_lpcr
 353             cmpwi       r3,chud_970_dabrx
 354             beq         mtspr64_dabrx
 355             cmpwi       r3,chud_970_hsprg0
 356             beq         mtspr64_hsprg0
 357             cmpwi       r3,chud_970_hsprg1
 358             beq         mtspr64_hsprg1
 359             cmpwi       r3,chud_970_hsrr0
 360             beq         mtspr64_hsrr0
 361             cmpwi       r3,chud_970_hsrr1
 362             beq         mtspr64_hsrr1
 363             cmpwi       r3,chud_970_hdec
 364             beq         mtspr64_hdec
 365             cmpwi       r3,chud_970_trig0
 366             beq         mtspr64_trig0
 367             cmpwi       r3,chud_970_trig1
 368             beq         mtspr64_trig1
 369             cmpwi       r3,chud_970_trig2
 370             beq         mtspr64_trig2
 371             cmpwi       r3,chud_ppc64_accr
 372             beq         mtspr64_accr
 373             cmpwi       r3,chud_970_scomc
 374             beq         mtspr64_scomc
 375             cmpwi       r3,chud_970_scomd
 376             beq         mtspr64_scomd
 377
 378             b           mtspr64_failure
 379
 380 mtspr64_srr0:
 381             ld          r5,0(r4)
 382             mtspr       chud_ppc_srr0,r5
 383             b           mtspr64_success
 384 mtspr64_srr1:
 385             ld          r5,0(r4)
 386             mtspr       chud_ppc_srr1,r5
 387             b           mtspr64_success
 388 mtspr64_dar:
 389             ld          r5,0(r4)
 390             mtspr       chud_ppc_dar,r5
 391             b           mtspr64_success
 392 mtspr64_sdr1:
 393             ld          r5,0(r4)
 394             mtspr       chud_ppc_sdr1,r5
 395             b           mtspr64_success
 396 mtspr64_sprg0:
 397             ld          r5,0(r4)
 398             mtspr       chud_ppc_sprg0,r5
 399             b           mtspr64_success
 400 mtspr64_sprg1:
 401             ld          r5,0(r4)
 402             mtspr       chud_ppc_sprg1,r5
 403             b           mtspr64_success
 404 mtspr64_sprg2:
 405             ld          r5,0(r4)
 406             mtspr       chud_ppc_sprg2,r5
 407             b           mtspr64_success
 408 mtspr64_sprg3:
 409             ld          r5,0(r4)
 410             mtspr       chud_ppc_sprg3,r5
 411             b           mtspr64_success
 412 mtspr64_asr:
 413             ld          r5,0(r4)
 414             mtspr       chud_ppc64_asr,r5
 415             b           mtspr64_success
 416 mtspr64_dabr:
 417             ld          r5,0(r4)
 418             mtspr       chud_ppc_dabr,r5
 419             b           mtspr64_success
 420 mtspr64_hid0:
 421             ld          r5,0(r4)
 422             sync
 423             mtspr       chud_970_hid0,r5
 424             mfspr       r5,chud_970_hid0        /* syncronization requirements */
 425             mfspr       r5,chud_970_hid0
 426             mfspr       r5,chud_970_hid0
 427             mfspr       r5,chud_970_hid0
 428             mfspr       r5,chud_970_hid0
 429             mfspr       r5,chud_970_hid0
 430             b           mtspr64_success
 431 mtspr64_hid1:
 432             ld          r5,0(r4)
 433             mtspr       chud_970_hid1,r5        /* tell you twice */
 434             mtspr       chud_970_hid1,r5
 435             isync
 436             b           mtspr64_success
 437 mtspr64_hid4:
 438             ld          r5,0(r4)
 439             sync                                /* syncronization requirements */
 440             mtspr       chud_970_hid4,r5
 441             isync
 442             b           mtspr64_success
 443 mtspr64_hid5:
 444             ld          r5,0(r4)
 445             mtspr       chud_970_hid5,r5
 446             b           mtspr64_success
 447 mtspr64_mmcr0:
 448             ld          r5,0(r4)
 449             mtspr       chud_970_mmcr0,r5
 450             b           mtspr64_success
 451 mtspr64_mmcr1:
 452             ld          r5,0(r4)
 453             mtspr       chud_970_mmcr1,r5
 454             b           mtspr64_success
 455 mtspr64_mmcra:
 456             ld          r5,0(r4)
 457             mtspr       chud_970_mmcra,r5
 458             b           mtspr64_success
 459 mtspr64_siar:
 460             ld          r5,0(r4)
 461             mtspr       chud_970_siar,r5
 462             b           mtspr64_success
 463 mtspr64_sdar:
 464             ld          r5,0(r4)
 465             mtspr       chud_970_sdar,r5
 466             b           mtspr64_success
 467 mtspr64_imc:
 468             ld          r5,0(r4)
 469             mtspr       chud_970_imc,r5
 470             b           mtspr64_success
 471 mtspr64_rmor:
 472             ld          r5,0(r4)
 473             mtspr       chud_970_rmor,r5
 474             b           mtspr64_success
 475 mtspr64_hrmor:
 476             ld          r5,0(r4)
 477             mtspr       chud_970_hrmor,r5
 478             b           mtspr64_success
 479 mtspr64_hior:
 480             ld          r5,0(r4)
 481             mtspr       chud_970_hior,r5
 482             b           mtspr64_success
 483 mtspr64_lpidr:
 484             ld          r5,0(r4)
 485             mtspr       chud_970_lpidr,r5
 486             b           mtspr64_success
 487 mtspr64_lpcr:
 488             ld          r5,0(r4)
 489             mtspr       chud_970_lpcr,r5
 490             b           mtspr64_success
 491 mtspr64_dabrx:
 492             ld          r5,0(r4)
 493             mtspr       chud_970_dabrx,r5
 494             b           mtspr64_success
 495 mtspr64_hsprg0:
 496             ld          r5,0(r4)
 497             mtspr       chud_970_hsprg0,r5
 498             b           mtspr64_success
 499 mtspr64_hsprg1:
 500             ld          r5,0(r4)
 501             mtspr       chud_970_hsprg1,r5
 502             b           mtspr64_success
 503 mtspr64_hsrr0:
 504             ld          r5,0(r4)
 505             mtspr       chud_970_hsrr0,r5
 506             b           mtspr64_success
 507 mtspr64_hsrr1:
 508             ld          r5,0(r4)
 509             mtspr       chud_970_hsrr1,r5
 510             b           mtspr64_success
 511 mtspr64_hdec:
 512             ld          r5,0(r4)
 513             mtspr       chud_970_hdec,r5
 514             b           mtspr64_success
 515 mtspr64_trig0:
 516             ld          r5,0(r4)
 517             mtspr       chud_970_trig0,r5
 518             b           mtspr64_success
 519 mtspr64_trig1:
 520             ld          r5,0(r4)
 521             mtspr       chud_970_trig1,r5
 522             b           mtspr64_success
 523 mtspr64_trig2:
 524             ld          r5,0(r4)
 525             mtspr       chud_970_trig2,r5
 526             b           mtspr64_success
 527 mtspr64_accr:
 528             ld          r5,0(r4)
 529             mtspr       chud_ppc64_accr,r5
 530             b           mtspr64_success
 531 mtspr64_scomc:
 532             ld          r5,0(r4)
 533             mtspr       chud_970_scomc,r5
 534             b           mtspr64_success
 535 mtspr64_scomd:
 536             ld          r5,0(r4)
 537             mtspr       chud_970_scomd,r5
 538             b           mtspr64_success
 539
 540 mtspr64_failure:
 541             li          r3,KERN_FAILURE
 542             blr
 543
 544 mtspr64_success:
 545             li          r3,KERN_SUCCESS
 546             blr
 547
 548
 549 /*
 550  * kern_return_t mfmsr64(uint64_t *val);
 551  *
 552  * r3: address to store value in
 553  *
 554  */
 555
 556 ;           Force a line boundry here
 557             .align  5
 558             .globl  EXT(mfmsr64)
 559
 560 EXT(mfmsr64):
 561             mfmsr       r5
 562             std         r5,0(r3)
 563 mfmsr64_success:
 564             li          r3,KERN_SUCCESS
 565             blr
 566
 567 mfmsr64_failure:
 568             li          r3,KERN_FAILURE
 569             blr
 570
 571
 572 /*
 573  * kern_return_t mtmsr64(uint64_t *val);
 574  *
 575  * r3: address to load value from
 576  *
 577  */
 578
 579 ;           Force a line boundry here
 580             .align  5
 581             .globl  EXT(mtmsr64)
 582
 583 EXT(mtmsr64):
 584             ld          r5,0(r3)
 585             mtmsrd      r5
 586             b           mtmsr64_success
 587
 588 mtmsr64_success:
 589             li          r3,KERN_SUCCESS
 590             blr
 591
 592 mtmsr64_failure:
 593             li          r3,KERN_FAILURE
 594             blr
 595
 596 .L_end: