EXTERNAL_HEADERS/architecture/ppc/basic_regs.h

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_OSREFERENCE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License.  The rights granted to you under the
  10  * License may not be used to create, or enable the creation or
  11  * redistribution of, unlawful or unlicensed copies of an Apple operating
  12  * system, or to circumvent, violate, or enable the circumvention or
  13  * violation of, any terms of an Apple operating system software license
  14  * agreement.
  15  *
  16  * Please obtain a copy of the License at
  17  * http://www.opensource.apple.com/apsl/ and read it before using this
  18  * file.
  19  *
  20  * The Original Code and all software distributed under the License are
  21  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  22  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  23  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  25  * Please see the License for the specific language governing rights and
  26  * limitations under the License.
  27  *
  28  * @APPLE_LICENSE_OSREFERENCE_HEADER_END@
  29  */
  30 /* Copyright (c) 1996 NeXT Software, Inc.  All rights reserved.
  31  *
  32  *      File:   architecture/ppc/basic_regs.h
  33  *      Author: Doug Mitchell, NeXT Software, Inc.
  34  *
  35  *      Basic ppc registers.
  36  *
  37  * HISTORY
  38  * 22-May-97  Umesh Vaishampayan  (umeshv@apple.com)
  39         Updated to match MPCFPE32B/AD 1/97 REV. 1
  40  * 29-Dec-96  Umesh Vaishampayan  (umeshv@NeXT.com)
  41  *      Ported from m98k.
  42  * 05-Nov-92  Doug Mitchell at NeXT
  43  *      Created.
  44  */
  45
  46 #ifndef _ARCH_PPC_BASIC_REGS_H_
  47 #define _ARCH_PPC_BASIC_REGS_H_
  48
  49 #include <architecture/ppc/reg_help.h>
  50 #include <architecture/ppc/macro_help.h>
  51
  52 #if !defined(__ASSEMBLER__)
  53
  54 /*
  55  * Number of General Purpose registers.
  56  */
  57 #define PPC_NGP_REGS    32
  58
  59 /*
  60  * Common half-word used in Machine State Register and in
  61  * various exception frames. Defined as a macro because the compiler
  62  * will align a struct to a word boundary when used inside another struct.
  63  */
  64 #define MSR_BITS                                                           \
  65         unsigned        ee:BIT_WIDTH(15),       /* external intr enable    */ \
  66                         pr:BIT_WIDTH(14),       /* problem state           */ \
  67                         fp:BIT_WIDTH(13),       /* floating point avail    */ \
  68                         me:BIT_WIDTH(12),       /* machine check enable    */ \
  69                         fe0:BIT_WIDTH(11),      /* fp exception mode 0     */ \
  70                         se:BIT_WIDTH(10),       /* single step enable      */ \
  71                         be:BIT_WIDTH(9),        /* branch trace enable     */ \
  72                         fe1:BIT_WIDTH(8),       /* fp exception mode 0     */ \
  73                         rsvd1:BIT_WIDTH(7),     /* reserved                */ \
  74                         ip:BIT_WIDTH(6),        /* interrupt prefix        */ \
  75                         ir:BIT_WIDTH(5),        /* instruction relocate    */ \
  76                         dr:BIT_WIDTH(4),        /* data relocate           */ \
  77                         rsvd2:BITS_WIDTH(3,2),  /* reserved                */ \
  78                         ri:BIT_WIDTH(1),        /* recoverable exception   */ \
  79                         le:BIT_WIDTH(0)         /* Little-endian mode      */
  80
  81 /*
  82  * Machine state register.
  83  * Read and written via get_msr() and set_msr() inlines, below.
  84  */
  85 typedef struct {
  86         unsigned        rsvd3:BITS_WIDTH(31,19),        // reserved
  87                         pow:BIT_WIDTH(18),      // Power management enable
  88                         rsvd0: BIT_WIDTH(17),   // reserved
  89                         ile: BIT_WIDTH(16);     // exception little endian
  90
  91                         MSR_BITS;                       // see above
  92 } msr_t;
  93
  94 /*
  95  * Data Storage Interrupt Status Register (DSISR)
  96  */
  97 typedef struct {
  98         unsigned        dse:BIT_WIDTH(31);      // direct-store error
  99         unsigned        tnf:BIT_WIDTH(30);      // translation not found
 100         unsigned        :BITS_WIDTH(29,28);
 101         unsigned        pe:BIT_WIDTH(27);       // protection error
 102         unsigned        dsr:BIT_WIDTH(26);      // lwarx/stwcx to direct-store
 103         unsigned        rw:BIT_WIDTH(25);       // 1 => store, 0 => load
 104         unsigned        :BITS_WIDTH(24,23);
 105         unsigned        dab:BIT_WIDTH(22);      // data address bkpt (601)
 106         unsigned        ssf:BIT_WIDTH(21);      // seg table search failed
 107         unsigned        :BITS_WIDTH(20,0);
 108 } dsisr_t;
 109
 110 /*
 111  * Instruction Storage Interrupt Status Register (really SRR1)
 112  */
 113 typedef struct {
 114         unsigned        :BIT_WIDTH(31);
 115         unsigned        tnf:BIT_WIDTH(30);      // translation not found
 116         unsigned        :BIT_WIDTH(29);
 117         unsigned        dse:BIT_WIDTH(28);      // direct-store fetch error
 118         unsigned        pe:BIT_WIDTH(27);       // protection error
 119         unsigned        :BITS_WIDTH(26,22);
 120         unsigned        ssf:BIT_WIDTH(21);      // seg table search failed
 121         unsigned        :BITS_WIDTH(20,16);
 122         MSR_BITS;
 123 } isisr_t;
 124
 125 /*
 126  * Alignment Interrupt Status Register (really DSISR)
 127  * NOTE: bit numbers in field *names* are in IBM'ese (0 is MSB).
 128  * FIXME: Yuck!!! Double Yuck!!!
 129  */
 130 typedef struct {
 131         unsigned        :BITS_WIDTH(31,20);
 132         unsigned        ds3031:BITS_WIDTH(19,18);// bits 30:31 if DS form
 133         unsigned        :BIT_WIDTH(17);
 134         unsigned        x2930:BITS_WIDTH(16,15); // bits 29:30 if X form
 135         unsigned        x25:BIT_WIDTH(14);       // bit 25 if X form or
 136                                                  // bit 5 if D or DS form
 137         unsigned        x2124:BITS_WIDTH(13,10); // bits 21:24 if X form or
 138                                                  // bits 1:4 if D or DS form
 139         unsigned        all615:BITS_WIDTH(9,0);  // bits 6:15 of instr
 140         MSR_BITS;
 141 } aisr_t;
 142
 143 /*
 144  * Program Interrupt Status Register (really SRR1)
 145  */
 146 typedef struct {
 147         unsigned        :BITS_WIDTH(31,21);
 148         unsigned        fpee:BIT_WIDTH(20);     // floating pt enable exception
 149         unsigned        ill:BIT_WIDTH(19);      // illegal instruction
 150         unsigned        priv:BIT_WIDTH(18);     // privileged instruction
 151         unsigned        trap:BIT_WIDTH(17);     // trap program interrupt
 152         unsigned        subseq:BIT_WIDTH(16);   // 1 => SRR0 points to
 153                                                 // subsequent instruction
 154         MSR_BITS;
 155 } pisr_t;
 156
 157 /*
 158  * Condition register. May not be useful in C, let's see...
 159  */
 160 typedef struct {
 161         unsigned        lt:BIT_WIDTH(31),       // negative
 162                         gt:BIT_WIDTH(30),       // positive
 163                         eq:BIT_WIDTH(29),       // equal to zero
 164                         so:BIT_WIDTH(28),       // summary overflow
 165                         fx:BIT_WIDTH(27),       // floating point exception
 166                         fex:BIT_WIDTH(26),      // fp enabled exception
 167                         vx:BIT_WIDTH(25),       // fp invalid operation
 168                                                 //    exception
 169                         ox:BIT_WIDTH(24),       // fp overflow exception
 170                         rsvd:BITS_WIDTH(23,0);  // reserved
 171 } cr_t;
 172
 173 /*
 174  * Abstract values representing fe0:fe1.
 175  * See get_fp_exc_mode(), below.
 176  */
 177 typedef enum {
 178         FEM_IGNORE_EXCEP,       // ignore exceptions
 179         FEM_IMPR_NONREC,        // imprecise nonrecoverable
 180         FEM_IMPR_RECOV,         // imprecise recoverable
 181         FEM_PRECISE
 182 } fp_exc_mode_t;
 183
 184
 185 /*
 186  * Special purpose registers.
 187  */
 188
 189 /*
 190  * Processor version register (special purpose register pvr).
 191  */
 192 typedef struct {
 193         unsigned        version:BITS_WIDTH(31,16),
 194                         revision:BITS_WIDTH(15,0);
 195 } pvr_t;
 196
 197 /*
 198  * Fixed point exception register (special purpose register xer)
 199  */
 200 typedef struct {
 201         unsigned        so:BIT_WIDTH(31),       // summary overflow
 202                         ov:BIT_WIDTH(30),       // overflow
 203                         ca:BIT_WIDTH(29),       // carry
 204                         rsvd1:BITS_WIDTH(28,7), // reserved
 205                         byte_count:BITS_WIDTH(6,0);
 206 } xer_t;
 207
 208 /*
 209  * Inlines and macros to manipulate the above registers.
 210  */
 211
 212 /*
 213  * Get/set machine state register.
 214  */
 215 static __inline__ msr_t
 216 get_msr()
 217 {
 218         msr_t   __msr_tmp;
 219         __asm__ volatile ("mfmsr %0  /* mfmsr */" : "=r" (__msr_tmp));
 220         return __msr_tmp;
 221 }
 222
 223 static __inline__ void
 224 set_msr(msr_t msr)
 225 {
 226         __asm__ volatile ("mtmsr %0 /* mtmsr */ " : : "r" (msr));
 227 }
 228
 229 /*
 230  * Determine current fp_exc_mode_t given prog_mode.
 231  */
 232 static __inline__ fp_exc_mode_t
 233 get_fp_exc_mode(pmr_t pmr)
 234 {
 235         if(pmr.fe0)
 236                 return pmr.fe1 ? FEM_PRECISE : FEM_IMPR_RECOV;
 237         else
 238                 return pmr.fe1 ? FEM_IMPR_NONREC : FEM_IGNORE_EXCEP;
 239 }
 240
 241 /*
 242  * Software definitions for special purpose registers.
 243  * The same register is used as per_cpu data pointer and
 244  * vector base register. This requires that the vector
 245  * table be the first item in the per_cpu table.
 246  */
 247 #define SR_EXCEPTION_TMP_LR     sprg0
 248 #define SR_EXCEPTION_TMP_CR     sprg1
 249 #define SR_EXCEPTION_TMP_AT     sprg2
 250 #define SR_PER_CPU_DATA         sprg3
 251 #define SR_VBR                  sprg3
 252
 253 /*
 254  * Get/set special purpose registers.
 255  *
 256  * GET_SPR - get SPR by name.
 257  *
 258  * Example usage:
 259  *
 260  *   {
 261  *      xer_t   some_xer;
 262  *
 263  *      some_xer = GET_SPR(xer_t, xer);
 264  *      ...
 265  *   }
 266  *
 267  * This is a strange one. We're creating a list of C expressions within
 268  * a set of curlies; the last expression ("__spr_tmp;") is the return value
 269  * of the statement created by the curlies.
 270  *
 271  */
 272
 273 #define GET_SPR(type, spr)                                      \
 274 ({                                                              \
 275         unsigned        __spr_tmp;                              \
 276         __asm__ volatile ("mfspr %0, " STRINGIFY(spr) : "=r" (__spr_tmp));                              \
 277         *(type *)&__spr_tmp;                                    \
 278 })
 279
 280 /*
 281  * Example usage of SET_SPR:
 282  *
 283  *   {
 284  *      xer_t some_xer;
 285  *
 286  *      ...set up some_xer...
 287  *      SET_SPR(xer, some_xer);
 288  *   }
 289  */
 290 #define SET_SPR(spr, val)                                       \
 291 MACRO_BEGIN                                                     \
 292         __typeof__ (val) __spr_tmp = (val);                     \
 293         __asm__ volatile ("mtspr "STRINGIFY(spr) ", %0" : : "r" (__spr_tmp));                                   \
 294 MACRO_END
 295
 296 /*
 297  * Fully synchronize instruction stream.
 298  */
 299 static __inline__ void
 300 ppc_sync()
 301 {
 302         __asm__ volatile ("sync         /* sync */" : : );
 303 }
 304
 305 #endif /* ! __ASSEMBLER__ */
 306
 307 #endif /* _ARCH_PPC_BASIC_REGS_H_ */
 308