pexpert/i386/pe_serial.c

   1 /*
   2  * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28
  29 /*
  30  * file: pe_serial.c
  31  *       Polled-mode 16x50 UART driver.
  32  */
  33
  34 #include <machine/machine_routines.h>
  35 #include <pexpert/protos.h>
  36 #include <pexpert/pexpert.h>
  37
  38 struct pe_serial_functions {
  39     void            (*uart_init) (void);
  40     void            (*uart_set_baud_rate) (int unit, uint32_t baud_rate);
  41     int             (*tr0) (void);
  42     void            (*td0) (int c);
  43     int             (*rr0) (void);
  44     int             (*rd0) (void);
  45 };
  46
  47 static struct pe_serial_functions *gPESF;
  48
  49 static int uart_initted = 0;   /* 1 if init'ed */
  50
  51 #define DEFAULT_UART_BAUD_RATE 115200
  52
  53 static unsigned uart_baud_rate = DEFAULT_UART_BAUD_RATE;
  54
  55 // =============================================================================
  56 // Legacy UART support using IO transactions to COM1 or COM2
  57 // =============================================================================
  58
  59 #define LEGACY_UART_PORT_ADDR   COM1_PORT_ADDR
  60 #define LEGACY_UART_CLOCK       1843200   /* 1.8432 MHz clock */
  61
  62 #define IO_WRITE(r, v)  outb(LEGACY_UART_PORT_ADDR + UART_##r, v)
  63 #define IO_READ(r)      inb(LEGACY_UART_PORT_ADDR + UART_##r)
  64
  65 enum {
  66     COM1_PORT_ADDR = 0x3f8,
  67     COM2_PORT_ADDR = 0x2f8
  68 };
  69
  70 enum {
  71     UART_RBR = 0,  /* receive buffer Register   (R) */
  72     UART_THR = 0,  /* transmit holding register (W) */
  73     UART_DLL = 0,  /* DLAB = 1, divisor latch (LSB) */
  74     UART_IER = 1,  /* interrupt enable register     */
  75     UART_DLM = 1,  /* DLAB = 1, divisor latch (MSB) */
  76     UART_IIR = 2,  /* interrupt ident register (R)  */
  77     UART_FCR = 2,  /* fifo control register (W)     */
  78     UART_LCR = 3,  /* line control register         */
  79     UART_MCR = 4,  /* modem control register        */
  80     UART_LSR = 5,  /* line status register          */
  81     UART_MSR = 6,  /* modem status register         */
  82     UART_SCR = 7   /* scratch register              */
  83 };
  84
  85 enum {
  86     UART_LCR_8BITS = 0x03,
  87     UART_LCR_DLAB  = 0x80
  88 };
  89
  90 enum {
  91     UART_MCR_DTR   = 0x01,
  92     UART_MCR_RTS   = 0x02,
  93     UART_MCR_OUT1  = 0x04,
  94     UART_MCR_OUT2  = 0x08,
  95     UART_MCR_LOOP  = 0x10
  96 };
  97
  98 enum {
  99     UART_LSR_DR    = 0x01,
 100     UART_LSR_OE    = 0x02,
 101     UART_LSR_PE    = 0x04,
 102     UART_LSR_FE    = 0x08,
 103     UART_LSR_THRE  = 0x20
 104 };
 105
 106 static int
 107 legacy_uart_probe( void )
 108 {
 109     /* Verify that the Scratch Register is accessible */
 110
 111     IO_WRITE( SCR, 0x5a );
 112     if (IO_READ(SCR) != 0x5a) return 0;
 113     IO_WRITE( SCR, 0xa5 );
 114     if (IO_READ(SCR) != 0xa5) return 0;
 115     return 1;
 116 }
 117
 118 static void
 119 legacy_uart_set_baud_rate( __unused int unit, uint32_t baud_rate )
 120 {
 121     const unsigned char lcr = IO_READ( LCR );
 122     unsigned long       div;
 123
 124     if (baud_rate == 0) baud_rate = 9600;
 125     div = LEGACY_UART_CLOCK / 16 / baud_rate;
 126     IO_WRITE( LCR, lcr | UART_LCR_DLAB );
 127     IO_WRITE( DLM, (unsigned char)(div >> 8) );
 128     IO_WRITE( DLL, (unsigned char) div );
 129     IO_WRITE( LCR, lcr & ~UART_LCR_DLAB);
 130 }
 131
 132 static int
 133 legacy_uart_tr0( void )
 134 {
 135     return (IO_READ(LSR) & UART_LSR_THRE);
 136 }
 137
 138 static void
 139 legacy_uart_td0( int c )
 140 {
 141     IO_WRITE( THR, c );
 142 }
 143
 144 static void
 145 legacy_uart_init( void )
 146 {
 147     /* Disable hardware interrupts */
 148
 149     IO_WRITE( MCR, 0 );
 150     IO_WRITE( IER, 0 );
 151
 152     /* Disable FIFO's for 16550 devices */
 153
 154     IO_WRITE( FCR, 0 );
 155
 156     /* Set for 8-bit, no parity, DLAB bit cleared */
 157
 158     IO_WRITE( LCR, UART_LCR_8BITS );
 159
 160     /* Set baud rate */
 161
 162     gPESF->uart_set_baud_rate ( 0, uart_baud_rate );
 163
 164     /* Assert DTR# and RTS# lines (OUT2?) */
 165
 166     IO_WRITE( MCR, UART_MCR_DTR | UART_MCR_RTS );
 167
 168     /* Clear any garbage in the input buffer */
 169
 170     IO_READ( RBR );
 171
 172     uart_initted = 1;
 173 }
 174
 175 static int
 176 legacy_uart_rr0( void )
 177 {
 178     unsigned char lsr;
 179
 180     lsr = IO_READ( LSR );
 181
 182     if ( lsr & (UART_LSR_FE | UART_LSR_PE | UART_LSR_OE) )
 183     {
 184         IO_READ( RBR ); /* discard */
 185         return 0;
 186     }
 187
 188     return (lsr & UART_LSR_DR);
 189 }
 190
 191 static int
 192 legacy_uart_rd0( void )
 193 {
 194     return IO_READ( RBR );
 195 }
 196
 197 static struct pe_serial_functions legacy_uart_serial_functions = {
 198     .uart_init = legacy_uart_init,
 199     .uart_set_baud_rate = legacy_uart_set_baud_rate,
 200     .tr0 = legacy_uart_tr0,
 201     .td0 = legacy_uart_td0,
 202     .rr0 = legacy_uart_rr0,
 203     .rd0 = legacy_uart_rd0
 204 };
 205
 206 // =============================================================================
 207 // MMIO UART (using PCH LPSS UART2)
 208 // =============================================================================
 209
 210 #define MMIO_UART2_BASE_LEGACY  0xFE034000
 211 #define MMIO_UART2_BASE         0xFE036000
 212
 213 #define MMIO_WRITE(r, v)  ml_phys_write_word(mmio_uart_base + MMIO_UART_##r, v)
 214 #define MMIO_READ(r)      ml_phys_read_word(mmio_uart_base + MMIO_UART_##r)
 215
 216 enum {
 217     MMIO_UART_RBR = 0x0,   /* receive buffer Register   (R) */
 218     MMIO_UART_THR = 0x0,   /* transmit holding register (W) */
 219     MMIO_UART_DLL = 0x0,   /* DLAB = 1, divisor latch (LSB) */
 220     MMIO_UART_IER = 0x4,   /* interrupt enable register     */
 221     MMIO_UART_DLM = 0x4,   /* DLAB = 1, divisor latch (MSB) */
 222     MMIO_UART_FCR = 0x8,   /* fifo control register (W)     */
 223     MMIO_UART_LCR = 0xc,   /* line control register         */
 224     MMIO_UART_MCR = 0x10,  /* modem control register        */
 225     MMIO_UART_LSR = 0x14,  /* line status register          */
 226     MMIO_UART_SCR = 0x1c   /* scratch register              */
 227 };
 228
 229 static vm_offset_t mmio_uart_base = 0;
 230
 231 static int
 232 mmio_uart_present( void )
 233 {
 234     MMIO_WRITE( SCR, 0x5a );
 235     if (MMIO_READ(SCR) != 0x5a) return 0;
 236     MMIO_WRITE( SCR, 0xa5 );
 237     if (MMIO_READ(SCR) != 0xa5) return 0;
 238
 239     return 1;
 240 }
 241
 242 static int
 243 mmio_uart_probe( void )
 244 {
 245     unsigned new_mmio_uart_base = 0;
 246
 247     // if specified, mmio_uart overrides all probing
 248     if (PE_parse_boot_argn("mmio_uart", &new_mmio_uart_base, sizeof (new_mmio_uart_base)))
 249     {
 250         // mmio_uart=0 will disable mmio_uart support
 251         if (new_mmio_uart_base == 0) {
 252             return 0;
 253         }
 254
 255         mmio_uart_base = new_mmio_uart_base;
 256         return 1;
 257     }
 258
 259     // probe the two possible MMIO_UART2 addresses
 260     mmio_uart_base = MMIO_UART2_BASE;
 261     if (mmio_uart_present()) {
 262       return 1;
 263     }
 264
 265     mmio_uart_base = MMIO_UART2_BASE_LEGACY;
 266     if (mmio_uart_present()) {
 267       return 1;
 268     }
 269
 270     // no mmio uart found
 271     return 0;
 272 }
 273
 274 static void
 275 mmio_uart_set_baud_rate( __unused int unit, __unused uint32_t baud_rate )
 276 {
 277     const unsigned char lcr = MMIO_READ( LCR );
 278     unsigned long       div;
 279
 280     if (baud_rate == 0) baud_rate = 9600;
 281     div = LEGACY_UART_CLOCK / 16 / baud_rate;
 282
 283     MMIO_WRITE( LCR, lcr | UART_LCR_DLAB );
 284     MMIO_WRITE( DLM, (unsigned char)(div >> 8) );
 285     MMIO_WRITE( DLL, (unsigned char) div );
 286     MMIO_WRITE( LCR, lcr & ~UART_LCR_DLAB);
 287 }
 288
 289 static int
 290 mmio_uart_tr0( void )
 291 {
 292     return (MMIO_READ(LSR) & UART_LSR_THRE);
 293 }
 294
 295 static void
 296 mmio_uart_td0( int c )
 297 {
 298     MMIO_WRITE( THR, c );
 299 }
 300
 301 static void
 302 mmio_uart_init( void )
 303 {
 304     /* Disable hardware interrupts */
 305
 306     MMIO_WRITE( MCR, 0 );
 307     MMIO_WRITE( IER, 0 );
 308
 309     /* Disable FIFO's for 16550 devices */
 310
 311     MMIO_WRITE( FCR, 0 );
 312
 313     /* Set for 8-bit, no parity, DLAB bit cleared */
 314
 315     MMIO_WRITE( LCR, UART_LCR_8BITS );
 316
 317     /* Leave baud rate as set by firmware unless serialbaud boot-arg overrides */
 318
 319     if (uart_baud_rate != DEFAULT_UART_BAUD_RATE)
 320     {
 321         gPESF->uart_set_baud_rate ( 0, uart_baud_rate );
 322     }
 323
 324     /* Assert DTR# and RTS# lines (OUT2?) */
 325
 326     MMIO_WRITE( MCR, UART_MCR_DTR | UART_MCR_RTS );
 327
 328     /* Clear any garbage in the input buffer */
 329
 330     MMIO_READ( RBR );
 331
 332     uart_initted = 1;
 333 }
 334
 335 static int
 336 mmio_uart_rr0( void )
 337 {
 338     unsigned char lsr;
 339
 340     lsr = MMIO_READ( LSR );
 341
 342     if ( lsr & (UART_LSR_FE | UART_LSR_PE | UART_LSR_OE) )
 343     {
 344         MMIO_READ( RBR ); /* discard */
 345         return 0;
 346     }
 347
 348     return (lsr & UART_LSR_DR);
 349 }
 350
 351 static int
 352 mmio_uart_rd0( void )
 353 {
 354     return MMIO_READ( RBR );
 355 }
 356
 357 static struct pe_serial_functions mmio_uart_serial_functions = {
 358     .uart_init = mmio_uart_init,
 359     .uart_set_baud_rate = mmio_uart_set_baud_rate,
 360     .tr0 = mmio_uart_tr0,
 361     .td0 = mmio_uart_td0,
 362     .rr0 = mmio_uart_rr0,
 363     .rd0 = mmio_uart_rd0
 364 };
 365
 366 // =============================================================================
 367 // Generic serial support below
 368 // =============================================================================
 369
 370 int
 371 serial_init( void )
 372 {
 373     unsigned new_uart_baud_rate = 0;
 374
 375     if (PE_parse_boot_argn("serialbaud", &new_uart_baud_rate, sizeof (new_uart_baud_rate)))
 376     {
 377         /* Valid divisor? */
 378         if (!((LEGACY_UART_CLOCK / 16) % new_uart_baud_rate)) {
 379             uart_baud_rate = new_uart_baud_rate;
 380         }
 381     }
 382
 383     if ( mmio_uart_probe() )
 384     {
 385         gPESF = &mmio_uart_serial_functions;
 386         gPESF->uart_init();
 387         return 1;
 388     }
 389     else if ( legacy_uart_probe() )
 390     {
 391         gPESF = &legacy_uart_serial_functions;
 392         gPESF->uart_init();
 393         return 1;
 394     }
 395     else
 396     {
 397         return 0;
 398     }
 399
 400 }
 401
 402 static void
 403 uart_putc(char c)
 404 {
 405     if (uart_initted) {
 406         while (!gPESF->tr0());  /* Wait until THR is empty. */
 407         gPESF->td0(c);
 408     }
 409 }
 410
 411 static int
 412 uart_getc(void)
 413 {
 414     if (uart_initted) {
 415         if (!gPESF->rr0())
 416             return -1;
 417         return gPESF->rd0();
 418     }
 419     return -1;
 420 }
 421
 422 void
 423 serial_putc( char c )
 424 {
 425     uart_putc(c);
 426 }
 427
 428 int
 429 serial_getc( void )
 430 {
 431     return uart_getc();
 432 }