osfmk/x86_64/kpc_x86.c

   1 /*
   2  * Copyright (c) 2012 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28
  29 #include <mach/mach_types.h>
  30 #include <machine/machine_routines.h>
  31 #include <kern/processor.h>
  32 #include <kern/kalloc.h>
  33 #include <i386/cpuid.h>
  34 #include <i386/proc_reg.h>
  35 #include <i386/mp.h>
  36 #include <sys/errno.h>
  37 #include <kperf/buffer.h>
  38
  39 #include <kern/kpc.h>
  40
  41 #include <kperf/kperf.h>
  42 #include <kperf/sample.h>
  43 #include <kperf/context.h>
  44 #include <kperf/action.h>
  45
  46 #include <chud/chud_xnu.h>
  47
  48
  49
  50 /* Fixed counter mask -- three counters, each with OS and USER */
  51 #define IA32_FIXED_CTR_ENABLE_ALL_CTRS_ALL_RINGS (0x333)
  52 #define IA32_FIXED_CTR_ENABLE_ALL_PMI (0x888)
  53
  54 #define IA32_PERFEVTSEL_PMI (1ull << 20)
  55 #define IA32_PERFEVTSEL_EN (1ull << 22)
  56
  57 /* Non-serialising */
  58 #define USE_RDPMC
  59
  60 #define RDPMC_FIXED_COUNTER_SELECTOR (1ULL<<30)
  61
  62 /* track the last config we enabled */
  63 static uint64_t kpc_running_cfg_pmc_mask = 0;
  64 static uint32_t kpc_running_classes = 0;
  65
  66 /* PMC / MSR accesses */
  67
  68 static uint64_t
  69 IA32_FIXED_CTR_CTRL(void)
  70 {
  71         return rdmsr64( MSR_IA32_PERF_FIXED_CTR_CTRL );
  72 }
  73
  74 static uint64_t
  75 IA32_FIXED_CTRx(uint32_t ctr)
  76 {
  77 #ifdef USE_RDPMC
  78         return rdpmc64(RDPMC_FIXED_COUNTER_SELECTOR | ctr);
  79 #else /* !USE_RDPMC */
  80         return rdmsr64(MSR_IA32_PERF_FIXED_CTR0 + ctr);
  81 #endif /* !USE_RDPMC */
  82 }
  83
  84 #ifdef FIXED_COUNTER_RELOAD
  85 static void
  86 wrIA32_FIXED_CTRx(uint32_t ctr, uint64_t value)
  87 {
  88         return wrmsr64(MSR_IA32_PERF_FIXED_CTR0 + ctr, value);
  89 }
  90 #endif
  91
  92 static uint64_t
  93 IA32_PMCx(uint32_t ctr)
  94 {
  95 #ifdef USE_RDPMC
  96         return rdpmc64(ctr);
  97 #else /* !USE_RDPMC */
  98         return rdmsr64(MSR_IA32_PERFCTR0 + ctr);
  99 #endif /* !USE_RDPMC */
 100 }
 101
 102 static void
 103 wrIA32_PMCx(uint32_t ctr, uint64_t value)
 104 {
 105         return wrmsr64(MSR_IA32_PERFCTR0 + ctr, value);
 106 }
 107
 108 static uint64_t
 109 IA32_PERFEVTSELx(uint32_t ctr)
 110 {
 111         return rdmsr64(MSR_IA32_EVNTSEL0 + ctr);
 112 }
 113
 114 static void
 115 wrIA32_PERFEVTSELx(uint32_t ctr, uint64_t value)
 116 {
 117         wrmsr64(MSR_IA32_EVNTSEL0 + ctr, value);
 118 }
 119
 120
 121 /* internal functions */
 122
 123 boolean_t
 124 kpc_is_running_fixed(void)
 125 {
 126         return (kpc_running_classes & KPC_CLASS_FIXED_MASK) == KPC_CLASS_FIXED_MASK;
 127 }
 128
 129 boolean_t
 130 kpc_is_running_configurable(uint64_t pmc_mask)
 131 {
 132         assert(kpc_popcount(pmc_mask) <= kpc_configurable_count());
 133         return ((kpc_running_classes & KPC_CLASS_CONFIGURABLE_MASK) == KPC_CLASS_CONFIGURABLE_MASK) &&
 134                ((kpc_running_cfg_pmc_mask & pmc_mask) == pmc_mask);
 135 }
 136
 137 uint32_t
 138 kpc_fixed_count(void)
 139 {
 140         i386_cpu_info_t *info = NULL;
 141         info = cpuid_info();
 142         return info->cpuid_arch_perf_leaf.fixed_number;
 143 }
 144
 145 uint32_t
 146 kpc_configurable_count(void)
 147 {
 148         i386_cpu_info_t *info = NULL;
 149         info = cpuid_info();
 150         return info->cpuid_arch_perf_leaf.number;
 151 }
 152
 153 uint32_t
 154 kpc_fixed_config_count(void)
 155 {
 156         return KPC_X86_64_FIXED_CONFIGS;
 157 }
 158
 159 uint32_t
 160 kpc_configurable_config_count(uint64_t pmc_mask)
 161 {
 162         assert(kpc_popcount(pmc_mask) <= kpc_configurable_count());
 163         return kpc_popcount(pmc_mask);
 164 }
 165
 166 uint32_t
 167 kpc_rawpmu_config_count(void)
 168 {
 169         // RAW PMU access not implemented.
 170         return 0;
 171 }
 172
 173 int
 174 kpc_get_rawpmu_config(__unused kpc_config_t *configv)
 175 {
 176         return 0;
 177 }
 178
 179 static uint8_t
 180 kpc_fixed_width(void)
 181 {
 182         i386_cpu_info_t *info = NULL;
 183
 184         info = cpuid_info();
 185
 186         return info->cpuid_arch_perf_leaf.fixed_width;
 187 }
 188
 189 static uint8_t
 190 kpc_configurable_width(void)
 191 {
 192         i386_cpu_info_t *info = NULL;
 193
 194         info = cpuid_info();
 195
 196         return info->cpuid_arch_perf_leaf.width;
 197 }
 198
 199 uint64_t
 200 kpc_fixed_max(void)
 201 {
 202         return (1ULL << kpc_fixed_width()) - 1;
 203 }
 204
 205 uint64_t
 206 kpc_configurable_max(void)
 207 {
 208         return (1ULL << kpc_configurable_width()) - 1;
 209 }
 210
 211 #ifdef FIXED_COUNTER_SHADOW
 212 static uint64_t
 213 kpc_reload_fixed(int ctr)
 214 {
 215         uint64_t old = IA32_FIXED_CTRx(ctr);
 216         wrIA32_FIXED_CTRx(ctr, FIXED_RELOAD(ctr));
 217         return old;
 218 }
 219 #endif
 220
 221 static uint64_t
 222 kpc_reload_configurable(int ctr)
 223 {
 224         uint64_t cfg = IA32_PERFEVTSELx(ctr);
 225
 226         /* counters must be disabled before they can be written to */
 227         uint64_t old = IA32_PMCx(ctr);
 228         wrIA32_PERFEVTSELx(ctr, cfg & ~IA32_PERFEVTSEL_EN);
 229         wrIA32_PMCx(ctr, CONFIGURABLE_RELOAD(ctr));
 230         wrIA32_PERFEVTSELx(ctr, cfg);
 231         return old;
 232 }
 233
 234 void kpc_pmi_handler(x86_saved_state_t *state);
 235
 236 static void
 237 set_running_fixed(boolean_t on)
 238 {
 239         uint64_t global = 0, mask = 0, fixed_ctrl = 0;
 240         int i;
 241         boolean_t enabled;
 242
 243         if( on )
 244                 /* these are per-thread in SMT */
 245                 fixed_ctrl = IA32_FIXED_CTR_ENABLE_ALL_CTRS_ALL_RINGS | IA32_FIXED_CTR_ENABLE_ALL_PMI;
 246         else
 247                 /* don't allow disabling fixed counters */
 248                 return;
 249
 250         wrmsr64( MSR_IA32_PERF_FIXED_CTR_CTRL, fixed_ctrl );
 251
 252         enabled = ml_set_interrupts_enabled(FALSE);
 253
 254         /* rmw the global control */
 255         global = rdmsr64(MSR_IA32_PERF_GLOBAL_CTRL);
 256         for( i = 0; i < (int) kpc_fixed_count(); i++ )
 257                 mask |= (1ULL<<(32+i));
 258
 259         if( on )
 260                 global |= mask;
 261         else
 262                 global &= ~mask;
 263
 264         wrmsr64(MSR_IA32_PERF_GLOBAL_CTRL, global);
 265
 266         ml_set_interrupts_enabled(enabled);
 267 }
 268
 269 static void
 270 set_running_configurable(uint64_t target_mask, uint64_t state_mask)
 271 {
 272         uint32_t cfg_count = kpc_configurable_count();
 273         uint64_t global = 0ULL, cfg = 0ULL, save = 0ULL;
 274         boolean_t enabled;
 275
 276         enabled = ml_set_interrupts_enabled(FALSE);
 277
 278         /* rmw the global control */
 279         global = rdmsr64(MSR_IA32_PERF_GLOBAL_CTRL);
 280
 281         /* need to save and restore counter since it resets when reconfigured */
 282         for (uint32_t i = 0; i < cfg_count; ++i) {
 283                 cfg = IA32_PERFEVTSELx(i);
 284                 save = IA32_PMCx(i);
 285                 wrIA32_PERFEVTSELx(i, cfg | IA32_PERFEVTSEL_PMI | IA32_PERFEVTSEL_EN);
 286                 wrIA32_PMCx(i, save);
 287         }
 288
 289         /* update the global control value */
 290         global &= ~target_mask; /* clear the targeted PMCs bits */
 291         global |= state_mask;   /* update the targeted PMCs bits with their new states */
 292         wrmsr64(MSR_IA32_PERF_GLOBAL_CTRL, global);
 293
 294         ml_set_interrupts_enabled(enabled);
 295 }
 296
 297 static void
 298 kpc_set_running_mp_call( void *vstate )
 299 {
 300         struct kpc_running_remote *mp_config = (struct kpc_running_remote*) vstate;
 301         assert(mp_config);
 302
 303         if (kpc_controls_fixed_counters())
 304                 set_running_fixed(mp_config->classes & KPC_CLASS_FIXED_MASK);
 305
 306         set_running_configurable(mp_config->cfg_target_mask,
 307                                  mp_config->cfg_state_mask);
 308 }
 309
 310 int
 311 kpc_get_fixed_config(kpc_config_t *configv)
 312 {
 313         configv[0] = IA32_FIXED_CTR_CTRL();
 314         return 0;
 315 }
 316
 317 static int
 318 kpc_set_fixed_config(kpc_config_t *configv)
 319 {
 320         (void) configv;
 321
 322         /* NYI */
 323         return -1;
 324 }
 325
 326 int
 327 kpc_get_fixed_counters(uint64_t *counterv)
 328 {
 329         int i, n = kpc_fixed_count();
 330
 331 #ifdef FIXED_COUNTER_SHADOW
 332         uint64_t status;
 333
 334         /* snap the counters */
 335         for( i = 0; i < n; i++ ) {
 336                 counterv[i] = FIXED_SHADOW(ctr) +
 337                         (IA32_FIXED_CTRx(i) - FIXED_RELOAD(ctr));
 338         }
 339
 340         /* Grab the overflow bits */
 341         status = rdmsr64(MSR_IA32_PERF_GLOBAL_STATUS);
 342
 343         /* If the overflow bit is set for a counter, our previous read may or may not have been
 344          * before the counter overflowed. Re-read any counter with it's overflow bit set so
 345          * we know for sure that it has overflowed. The reason this matters is that the math
 346          * is different for a counter that has overflowed. */
 347         for( i = 0; i < n; i++ ) {
 348                 if ((1ull << (i + 32)) & status)
 349                         counterv[i] = FIXED_SHADOW(ctr) +
 350                                 (kpc_fixed_max() - FIXED_RELOAD(ctr) + 1 /* Wrap */) + IA32_FIXED_CTRx(i);
 351         }
 352 #else
 353         for( i = 0; i < n; i++ )
 354                 counterv[i] = IA32_FIXED_CTRx(i);
 355 #endif
 356
 357         return 0;
 358 }
 359
 360 int
 361 kpc_get_configurable_config(kpc_config_t *configv, uint64_t pmc_mask)
 362 {
 363         uint32_t cfg_count = kpc_configurable_count();
 364
 365         assert(configv);
 366
 367         for (uint32_t i = 0; i < cfg_count; ++i)
 368                 if ((1ULL << i) & pmc_mask)
 369                         *configv++  = IA32_PERFEVTSELx(i);
 370         return 0;
 371 }
 372
 373 static int
 374 kpc_set_configurable_config(kpc_config_t *configv, uint64_t pmc_mask)
 375 {
 376         uint32_t cfg_count = kpc_configurable_count();
 377         uint64_t save;
 378
 379         for (uint32_t i = 0; i < cfg_count; i++ ) {
 380                 if (((1ULL << i) & pmc_mask) == 0)
 381                         continue;
 382
 383                 /* need to save and restore counter since it resets when reconfigured */
 384                 save = IA32_PMCx(i);
 385
 386                 /*
 387                  * Some bits are not safe to set from user space.
 388                  * Allow these bits to be set:
 389                  *
 390                  *   0-7    Event select
 391                  *   8-15   UMASK
 392                  *   16     USR
 393                  *   17     OS
 394                  *   18     E
 395                  *   22     EN
 396                  *   23     INV
 397                  *   24-31  CMASK
 398                  *
 399                  * Excluding:
 400                  *
 401                  *   19     PC
 402                  *   20     INT
 403                  *   21     AnyThread
 404                  *   32     IN_TX
 405                  *   33     IN_TXCP
 406                  *   34-63  Reserved
 407                  */
 408                 wrIA32_PERFEVTSELx(i, *configv & 0xffc7ffffull);
 409                 wrIA32_PMCx(i, save);
 410
 411                 /* next configuration word */
 412                 configv++;
 413         }
 414
 415         return 0;
 416 }
 417
 418 int
 419 kpc_get_configurable_counters(uint64_t *counterv, uint64_t pmc_mask)
 420 {
 421         uint32_t cfg_count = kpc_configurable_count();
 422         uint64_t status, *it_counterv = counterv;
 423
 424         /* snap the counters */
 425         for (uint32_t i = 0; i < cfg_count; ++i) {
 426                 if ((1ULL << i) & pmc_mask) {
 427                         *it_counterv++ = CONFIGURABLE_SHADOW(i) +
 428                                          (IA32_PMCx(i) - CONFIGURABLE_RELOAD(i));
 429                 }
 430         }
 431
 432         /* Grab the overflow bits */
 433         status = rdmsr64(MSR_IA32_PERF_GLOBAL_STATUS);
 434
 435         /* reset the iterator */
 436         it_counterv = counterv;
 437
 438         /*
 439          * If the overflow bit is set for a counter, our previous read may or may not have been
 440          * before the counter overflowed. Re-read any counter with it's overflow bit set so
 441          * we know for sure that it has overflowed. The reason this matters is that the math
 442          * is different for a counter that has overflowed.
 443          */
 444         for (uint32_t i = 0; i < cfg_count; ++i) {
 445                 if (((1ULL << i) & pmc_mask) &&
 446                     ((1ULL << i) & status))
 447                 {
 448                         *it_counterv++ = CONFIGURABLE_SHADOW(i) +
 449                                          (kpc_configurable_max() - CONFIGURABLE_RELOAD(i)) + IA32_PMCx(i);
 450                 }
 451         }
 452
 453         return 0;
 454 }
 455
 456 static void
 457 kpc_get_curcpu_counters_mp_call(void *args)
 458 {
 459         struct kpc_get_counters_remote *handler = args;
 460         int offset=0, r=0;
 461
 462         assert(handler);
 463         assert(handler->buf);
 464
 465         offset = cpu_number() * handler->buf_stride;
 466         r = kpc_get_curcpu_counters(handler->classes, NULL, &handler->buf[offset]);
 467
 468         /* number of counters added by this CPU, needs to be atomic  */
 469         hw_atomic_add(&(handler->nb_counters), r);
 470 }
 471
 472 int
 473 kpc_get_all_cpus_counters(uint32_t classes, int *curcpu, uint64_t *buf)
 474 {
 475         int enabled = 0;
 476
 477         struct kpc_get_counters_remote hdl = {
 478                 .classes = classes, .nb_counters = 0,
 479                 .buf_stride = kpc_get_counter_count(classes), .buf = buf
 480         };
 481
 482         assert(buf);
 483
 484         enabled = ml_set_interrupts_enabled(FALSE);
 485
 486         if (curcpu)
 487                 *curcpu = current_processor()->cpu_id;
 488         mp_cpus_call(CPUMASK_ALL, ASYNC, kpc_get_curcpu_counters_mp_call, &hdl);
 489
 490         ml_set_interrupts_enabled(enabled);
 491
 492         return hdl.nb_counters;
 493 }
 494
 495 static void
 496 kpc_set_config_mp_call(void *vmp_config)
 497 {
 498
 499         struct kpc_config_remote *mp_config = vmp_config;
 500         kpc_config_t *new_config = NULL;
 501         uint32_t classes = 0, count = 0;
 502         boolean_t enabled;
 503
 504         assert(mp_config);
 505         assert(mp_config->configv);
 506         classes = mp_config->classes;
 507         new_config = mp_config->configv;
 508
 509         enabled = ml_set_interrupts_enabled(FALSE);
 510
 511         if (classes & KPC_CLASS_FIXED_MASK)
 512         {
 513                 kpc_set_fixed_config(&new_config[count]);
 514                 count += kpc_get_config_count(KPC_CLASS_FIXED_MASK);
 515         }
 516
 517         if (classes & KPC_CLASS_CONFIGURABLE_MASK) {
 518                 kpc_set_configurable_config(&new_config[count], mp_config->pmc_mask);
 519                 count += kpc_popcount(mp_config->pmc_mask);
 520         }
 521
 522         ml_set_interrupts_enabled(enabled);
 523 }
 524
 525 static void
 526 kpc_set_reload_mp_call(void *vmp_config)
 527 {
 528         struct kpc_config_remote *mp_config = vmp_config;
 529         uint64_t *new_period = NULL, max = kpc_configurable_max();
 530         uint32_t classes = 0, count = 0;
 531         boolean_t enabled;
 532
 533         assert(mp_config);
 534         assert(mp_config->configv);
 535         classes = mp_config->classes;
 536         new_period = mp_config->configv;
 537
 538         enabled = ml_set_interrupts_enabled(FALSE);
 539
 540         if (classes & KPC_CLASS_CONFIGURABLE_MASK) {
 541                 /*
 542                  * Update _all_ shadow counters, this cannot be done for only
 543                  * selected PMCs. Otherwise, we would corrupt the configurable
 544                  * shadow buffer since the PMCs are muxed according to the pmc
 545                  * mask.
 546                  */
 547                 uint64_t all_cfg_mask = (1ULL << kpc_configurable_count()) - 1;
 548                 kpc_get_configurable_counters(&CONFIGURABLE_SHADOW(0), all_cfg_mask);
 549
 550                 /* set the new period */
 551                 count = kpc_configurable_count();
 552                 for (uint32_t i = 0; i < count; ++i) {
 553                         /* ignore the counter */
 554                         if (((1ULL << i) & mp_config->pmc_mask) == 0)
 555                                 continue;
 556
 557                         if (*new_period == 0)
 558                                 *new_period = kpc_configurable_max();
 559
 560                         CONFIGURABLE_RELOAD(i) = max - *new_period;
 561
 562                         /* reload the counter */
 563                         kpc_reload_configurable(i);
 564
 565                         /* clear overflow bit just in case */
 566                         wrmsr64(MSR_IA32_PERF_GLOBAL_OVF_CTRL, 1ull << i);
 567
 568                         /* next period value */
 569                         new_period++;
 570                 }
 571         }
 572
 573         ml_set_interrupts_enabled(enabled);
 574 }
 575
 576 int
 577 kpc_set_period_arch( struct kpc_config_remote *mp_config )
 578 {
 579         mp_cpus_call( CPUMASK_ALL, ASYNC, kpc_set_reload_mp_call, mp_config );
 580
 581         return 0;
 582 }
 583
 584
 585 /* interface functions */
 586
 587 void
 588 kpc_arch_init(void)
 589 {
 590         /* No-op */
 591 }
 592
 593 uint32_t
 594 kpc_get_classes(void)
 595 {
 596         return KPC_CLASS_FIXED_MASK | KPC_CLASS_CONFIGURABLE_MASK;
 597 }
 598
 599 int
 600 kpc_set_running_arch(struct kpc_running_remote *mp_config)
 601 {
 602         assert(mp_config);
 603
 604         /* dispatch to all CPUs */
 605         mp_cpus_call(CPUMASK_ALL, ASYNC, kpc_set_running_mp_call, mp_config);
 606
 607         kpc_running_cfg_pmc_mask = mp_config->cfg_state_mask;
 608         kpc_running_classes = mp_config->classes;
 609
 610         return 0;
 611 }
 612
 613 int
 614 kpc_set_config_arch(struct kpc_config_remote *mp_config)
 615 {
 616         mp_cpus_call( CPUMASK_ALL, ASYNC, kpc_set_config_mp_call, mp_config );
 617
 618         return 0;
 619 }
 620
 621 /* PMI stuff */
 622 void kpc_pmi_handler(__unused x86_saved_state_t *state)
 623 {
 624         uint64_t status, extra;
 625         uint32_t ctr;
 626         int enabled;
 627
 628         enabled = ml_set_interrupts_enabled(FALSE);
 629
 630         status = rdmsr64(MSR_IA32_PERF_GLOBAL_STATUS);
 631
 632 #ifdef FIXED_COUNTER_SHADOW
 633         for (ctr = 0; ctr < kpc_fixed_count(); ctr++) {
 634                 if ((1ULL << (ctr + 32)) & status) {
 635                         extra = kpc_reload_fixed(ctr);
 636
 637                         FIXED_SHADOW(ctr)
 638                                 += (kpc_fixed_max() - FIXED_RELOAD(ctr) + 1 /* Wrap */) + extra;
 639
 640                         BUF_INFO(PERF_KPC_FCOUNTER, ctr, FIXED_SHADOW(ctr), extra, FIXED_ACTIONID(ctr));
 641
 642                         if (FIXED_ACTIONID(ctr))
 643                                 kpc_sample_kperf(FIXED_ACTIONID(ctr));
 644                 }
 645         }
 646 #endif
 647
 648         for (ctr = 0; ctr < kpc_configurable_count(); ctr++) {
 649                 if ((1ULL << ctr) & status) {
 650                         extra = kpc_reload_configurable(ctr);
 651
 652                         CONFIGURABLE_SHADOW(ctr)
 653                                 += kpc_configurable_max() - CONFIGURABLE_RELOAD(ctr) + extra;
 654
 655                         /* kperf can grab the PMCs when it samples so we need to make sure the overflow
 656                          * bits are in the correct state before the call to kperf_sample */
 657                         wrmsr64(MSR_IA32_PERF_GLOBAL_OVF_CTRL, 1ull << ctr);
 658
 659                         BUF_INFO(PERF_KPC_COUNTER, ctr, CONFIGURABLE_SHADOW(ctr), extra, CONFIGURABLE_ACTIONID(ctr));
 660
 661                         if (CONFIGURABLE_ACTIONID(ctr))
 662                                 kpc_sample_kperf(CONFIGURABLE_ACTIONID(ctr));
 663                 }
 664         }
 665
 666         ml_set_interrupts_enabled(enabled);
 667 }
 668
 669 int
 670 kpc_set_sw_inc( uint32_t mask __unused )
 671 {
 672         return ENOTSUP;
 673 }
 674
 675 int
 676 kpc_get_pmu_version(void)
 677 {
 678         i386_cpu_info_t *info = cpuid_info();
 679
 680         uint8_t version_id = info->cpuid_arch_perf_leaf.version;
 681
 682         if (version_id == 3) {
 683                 return KPC_PMU_INTEL_V3;
 684         } else if (version_id == 2) {
 685                 return KPC_PMU_INTEL_V2;
 686         }
 687
 688         return KPC_PMU_ERROR;
 689 }
 690