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1 /*
2 * Copyright (c) 2007-2013 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * Processor registers for ARM64
30 */
31 #ifndef _ARM64_PROC_REG_H_
32 #define _ARM64_PROC_REG_H_
33
34 #include <arm/proc_reg.h>
35
36 /*
37 * 64-bit Program Status Register (PSR64)
38 *
39 * 31 27 23 22 21 20 19 10 9 5 4 0
40 * +-+-+-+-+-----+---+--+--+----------+-+-+-+-+-+-----+
41 * |N|Z|C|V|00000|PAN|SS|IL|0000000000|D|A|I|F|0| M |
42 * +-+-+-+-+-+---+---+--+--+----------+-+-+-+-+-+-----+
43 *
44 * where:
45 * NZCV Comparison flags
46 * PAN Privileged Access Never
47 * SS Single step
48 * IL Illegal state
49 * DAIF Interrupt masks
50 * M Mode field
51 */
52
53 #define PSR64_NZCV_SHIFT 28
54 #define PSR64_NZCV_MASK (1 << PSR64_NZCV_SHIFT)
55
56 #define PSR64_N_SHIFT 31
57 #define PSR64_N (1 << PSR64_N_SHIFT)
58
59 #define PSR64_Z_SHIFT 30
60 #define PSR64_Z (1 << PSR64_Z_SHIFT)
61
62 #define PSR64_C_SHIFT 29
63 #define PSR64_C (1 << PSR64_C_SHIFT)
64
65 #define PSR64_V_SHIFT 28
66 #define PSR64_V (1 << PSR64_V_SHIFT)
67
68 #define PSR64_PAN_SHIFT 22
69 #define PSR64_PAN (1 << PSR64_PAN_SHIFT)
70
71 #define PSR64_SS_SHIFT 21
72 #define PSR64_SS (1 << PSR64_SS_SHIFT)
73
74 #define PSR64_IL_SHIFT 20
75 #define PSR64_IL (1 << PSR64_IL_SHIFT)
76
77 /*
78 * msr DAIF, Xn and mrs Xn, DAIF transfer into
79 * and out of bits 9:6
80 */
81 #define DAIF_DEBUG_SHIFT 9
82 #define DAIF_DEBUGF (1 << DAIF_DEBUG_SHIFT)
83
84 #define DAIF_ASYNC_SHIFT 8
85 #define DAIF_ASYNCF (1 << DAIF_ASYNC_SHIFT)
86
87 #define DAIF_IRQF_SHIFT 7
88 #define DAIF_IRQF (1 << DAIF_IRQF_SHIFT)
89
90 #define DAIF_FIQF_SHIFT 6
91 #define DAIF_FIQF (1 << DAIF_FIQF_SHIFT)
92
93 #define DAIF_ALL (DAIF_DEBUGF | DAIF_ASYNCF | DAIF_IRQF | DAIF_FIQF)
94 #define DAIF_STANDARD_DISABLE (DAIF_ASYNCF | DAIF_IRQF | DAIF_FIQF)
95
96 #define SPSR_INTERRUPTS_ENABLED(x) (!(x & DAIF_FIQF))
97
98 /*
99 * msr DAIFSet, Xn, and msr DAIFClr, Xn transfer
100 * from bits 3:0.
101 */
102 #define DAIFSC_DEBUGF (1 << 3)
103 #define DAIFSC_ASYNCF (1 << 2)
104 #define DAIFSC_IRQF (1 << 1)
105 #define DAIFSC_FIQF (1 << 0)
106 #define DAIFSC_ALL (DAIFSC_DEBUGF | DAIFSC_ASYNCF | DAIFSC_IRQF | DAIFSC_FIQF)
107 #define DAIFSC_STANDARD_DISABLE (DAIFSC_ASYNCF | DAIFSC_IRQF | DAIFSC_FIQF)
108
109 /*
110 * ARM64_TODO: unify with ARM?
111 */
112 #define PSR64_CF 0x20000000 /* Carry/Borrow/Extend */
113
114 #define PSR64_MODE_MASK 0x1F
115
116 #define PSR64_MODE_USER32_THUMB 0x20
117
118 #define PSR64_MODE_RW_SHIFT 4
119 #define PSR64_MODE_RW_64 0
120 #define PSR64_MODE_RW_32 (0x1 << PSR64_MODE_RW_SHIFT)
121
122 #define PSR64_MODE_EL_SHIFT 2
123 #define PSR64_MODE_EL_MASK (0x3 << PSR64_MODE_EL_SHIFT)
124 #define PSR64_MODE_EL3 (0x3 << PSR64_MODE_EL_SHIFT)
125 #define PSR64_MODE_EL1 (0x1 << PSR64_MODE_EL_SHIFT)
126 #define PSR64_MODE_EL0 0
127
128 #define PSR64_MODE_SPX 0x1
129 #define PSR64_MODE_SP0 0
130
131 #define PSR64_USER32_DEFAULT (PSR64_MODE_RW_32 | PSR64_MODE_EL0 | PSR64_MODE_SP0)
132 #define PSR64_USER64_DEFAULT (PSR64_MODE_RW_64 | PSR64_MODE_EL0 | PSR64_MODE_SP0)
133 #define PSR64_KERNEL_DEFAULT (DAIF_STANDARD_DISABLE | PSR64_MODE_RW_64 | PSR64_MODE_EL1 | PSR64_MODE_SP0)
134
135 #define PSR64_IS_KERNEL(x) ((x & PSR64_MODE_EL_MASK) == PSR64_MODE_EL1)
136 #define PSR64_IS_USER(x) ((x & PSR64_MODE_EL_MASK) == PSR64_MODE_EL0)
137
138 #define PSR64_IS_USER32(x) (PSR64_IS_USER(x) && (x & PSR64_MODE_RW_32))
139 #define PSR64_IS_USER64(x) (PSR64_IS_USER(x) && !(x & PSR64_MODE_RW_32))
140
141
142
143 /*
144 * System Control Register (SCTLR)
145 */
146
147 #define SCTLR_RESERVED ((3 << 28) | (1 << 22) | (1 << 20) | (1 << 11))
148
149 // 31 PACIA_ENABLED AddPACIA and AuthIA functions enabled
150 #define SCTLR_PACIA_ENABLED (1 << 31)
151 // 30 PACIB_ENABLED AddPACIB and AuthIB functions enabled
152 #define SCTLR_PACIB_ENABLED (1 << 30)
153 // 29:28 RES1 11
154 // 27 PACDA_ENABLED AddPACDA and AuthDA functions enabled
155 #define SCTLR_PACDA_ENABLED (1 << 27)
156
157 // 26 UCI User Cache Instructions
158 #define SCTLR_UCI_ENABLED (1 << 26)
159
160 // 25 EE Exception Endianness
161 #define SCTLR_EE_BIG_ENDIAN (1 << 25)
162
163 // 24 E0E EL0 Endianness
164 #define SCTLR_E0E_BIG_ENDIAN (1 << 24)
165
166 // 23 SPAN Set PAN
167 #define SCTLR_PAN_UNCHANGED (1 << 23)
168
169 // 22 RES1 1
170 // 21 RES0 0
171 // 20 RES1 1
172
173 // 19 WXN Writeable implies eXecute Never
174 #define SCTLR_WXN_ENABLED (1 << 19)
175
176 // 18 nTWE Not trap WFE from EL0
177 #define SCTLR_nTWE_WFE_ENABLED (1 << 18)
178
179 // 17 RES0 0
180
181 // 16 nTWI Not trap WFI from EL0
182 #define SCTRL_nTWI_WFI_ENABLED (1 << 16)
183
184 // 15 UCT User Cache Type register (CTR_EL0)
185 #define SCTLR_UCT_ENABLED (1 << 15)
186
187 // 14 DZE User Data Cache Zero (DC ZVA)
188 #define SCTLR_DZE_ENABLED (1 << 14)
189
190 // 13 RES0 0
191
192 // 12 I Instruction cache enable
193 #define SCTLR_I_ENABLED (1 << 12)
194
195 // 11 RES1 1
196 // 10 RES0 0
197
198 // 9 UMA User Mask Access
199 #define SCTLR_UMA_ENABLED (1 << 9)
200
201 // 8 SED SETEND Disable
202 #define SCTLR_SED_DISABLED (1 << 8)
203
204 // 7 ITD IT Disable
205 #define SCTLR_ITD_DISABLED (1 << 7)
206
207 // 6 RES0 0
208
209 // 5 CP15BEN CP15 Barrier ENable
210 #define SCTLR_CP15BEN_ENABLED (1 << 5)
211
212 // 4 SA0 Stack Alignment check for EL0
213 #define SCTLR_SA0_ENABLED (1 << 4)
214
215 // 3 SA Stack Alignment check
216 #define SCTLR_SA_ENABLED (1 << 3)
217
218 // 2 C Cache enable
219 #define SCTLR_C_ENABLED (1 << 2)
220
221 // 1 A Alignment check
222 #define SCTLR_A_ENABLED (1 << 1)
223
224 // 0 M MMU enable
225 #define SCTLR_M_ENABLED (1 << 0)
226
227 #define SCTLR_PAC_DEFAULT 0
228
229 #define SCTLR_EL1_DEFAULT (SCTLR_PAC_DEFAULT | SCTLR_RESERVED | SCTLR_UCI_ENABLED | SCTLR_nTWE_WFE_ENABLED | SCTLR_DZE_ENABLED | \
230 SCTLR_I_ENABLED | SCTLR_SED_DISABLED | SCTLR_CP15BEN_ENABLED | \
231 SCTLR_SA0_ENABLED | SCTLR_SA_ENABLED | SCTLR_PAN_UNCHANGED | \
232 SCTLR_C_ENABLED | SCTLR_M_ENABLED)
233
234
235
236 /*
237 * Coprocessor Access Control Register (CPACR)
238 *
239 * 31 28 27 22 21 20 19 0
240 * +---+---+------+------+--------------------+
241 * |000|TTA|000000| FPEN |00000000000000000000|
242 * +---+---+------+------+--------------------+
243 *
244 * where:
245 * TTA Trace trap
246 * FPEN Floating point enable
247 */
248 #define CPACR_TTA_SHIFT 28
249 #define CPACR_TTA (1 << CPACR_TTA_SHIFT)
250
251 #define CPACR_FPEN_SHIFT 20
252 #define CPACR_FPEN_EL0_TRAP (0x1 << CPACR_FPEN_SHIFT)
253 #define CPACR_FPEN_ENABLE (0x3 << CPACR_FPEN_SHIFT)
254
255 /*
256 * FPSR: Floating Point Status Register
257 *
258 * 31 30 29 28 27 26 7 6 4 3 2 1 0
259 * +--+--+--+--+--+-------------------+---+--+---+---+---+---+---+
260 * | N| Z| C| V|QC|0000000000000000000|IDC|00|IXC|UFC|OFC|DZC|IOC|
261 * +--+--+--+--+--+-------------------+---+--+---+---+---+---+---+
262 */
263
264 #define FPSR_N_SHIFT 31
265 #define FPSR_Z_SHIFT 30
266 #define FPSR_C_SHIFT 29
267 #define FPSR_V_SHIFT 28
268 #define FPSR_QC_SHIFT 27
269 #define FPSR_IDC_SHIFT 7
270 #define FPSR_IXC_SHIFT 4
271 #define FPSR_UFC_SHIFT 3
272 #define FPSR_OFC_SHIFT 2
273 #define FPSR_DZC_SHIFT 1
274 #define FPSR_IOC_SHIFT 0
275 #define FPSR_N (1 << FPSR_N_SHIFT)
276 #define FPSR_Z (1 << FPSR_Z_SHIFT)
277 #define FPSR_C (1 << FPSR_C_SHIFT)
278 #define FPSR_V (1 << FPSR_V_SHIFT)
279 #define FPSR_QC (1 << FPSR_QC_SHIFT)
280 #define FPSR_IDC (1 << FPSR_IDC_SHIFT)
281 #define FPSR_IXC (1 << FPSR_IXC_SHIFT)
282 #define FPSR_UFC (1 << FPSR_UFC_SHIFT)
283 #define FPSR_OFC (1 << FPSR_OFC_SHIFT)
284 #define FPSR_DZC (1 << FPSR_DZC_SHIFT)
285 #define FPSR_IOC (1 << FPSR_IOC_SHIFT)
286
287 /*
288 * A mask for all for all of the bits that are not RAZ for FPSR; this
289 * is primarily for converting between a 32-bit view of NEON state
290 * (FPSCR) and a 64-bit view of NEON state (FPSR, FPCR).
291 */
292 #define FPSR_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V | FPSR_QC | \
293 FPSR_IDC | FPSR_IXC | FPSR_UFC | FPSR_OFC | \
294 FPSR_DZC | FPSR_IOC)
295
296 /*
297 * FPCR: Floating Point Control Register
298 *
299 * 31 26 25 24 23 21 19 18 15 14 12 11 10 9 8 7 0
300 * +-----+---+--+--+-----+------+--+---+---+--+---+---+---+---+---+--------+
301 * |00000|AHP|DN|FZ|RMODE|STRIDE| 0|LEN|IDE|00|IXE|UFE|OFE|DZE|IOE|00000000|
302 * +-----+---+--+--+-----+------+--+---+---+--+---+---+---+---+---+--------+
303 */
304
305 #define FPCR_AHP_SHIFT 26
306 #define FPCR_DN_SHIFT 25
307 #define FPCR_FZ_SHIFT 24
308 #define FPCR_RMODE_SHIFT 22
309 #define FPCR_STRIDE_SHIFT 20
310 #define FPCR_LEN_SHIFT 16
311 #define FPCR_IDE_SHIFT 15
312 #define FPCR_IXE_SHIFT 12
313 #define FPCR_UFE_SHIFT 11
314 #define FPCR_OFE_SHIFT 10
315 #define FPCR_DZE_SHIFT 9
316 #define FPCR_IOE_SHIFT 8
317 #define FPCR_AHP (1 << FPCR_AHP_SHIFT)
318 #define FPCR_DN (1 << FPCR_DN_SHIFT)
319 #define FPCR_FZ (1 << FPCR_FZ_SHIFT)
320 #define FPCR_RMODE (0x3 << FPCR_RMODE_SHIFT)
321 #define FPCR_STRIDE (0x3 << FPCR_STRIDE_SHIFT)
322 #define FPCR_LEN (0x7 << FPCR_LEN_SHIFT)
323 #define FPCR_IDE (1 << FPCR_IDE_SHIFT)
324 #define FPCR_IXE (1 << FPCR_IXE_SHIFT)
325 #define FPCR_UFE (1 << FPCR_UFE_SHIFT)
326 #define FPCR_OFE (1 << FPCR_OFE_SHIFT)
327 #define FPCR_DZE (1 << FPCR_DZE_SHIFT)
328 #define FPCR_IOE (1 << FPCR_IOE_SHIFT)
329 #define FPCR_DEFAULT (FPCR_DN)
330 #define FPCR_DEFAULT_32 (FPCR_DN|FPCR_FZ)
331
332 /*
333 * A mask for all for all of the bits that are not RAZ for FPCR; this
334 * is primarily for converting between a 32-bit view of NEON state
335 * (FPSCR) and a 64-bit view of NEON state (FPSR, FPCR).
336 */
337 #define FPCR_MASK (FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE | \
338 FPCR_STRIDE | FPCR_LEN | FPCR_IDE | FPCR_IXE | \
339 FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR_IOE)
340
341 /*
342 * Translation Control Register (TCR)
343 *
344 * Legacy:
345 *
346 * 63 39 38 37 36 34 32 30 29 28 27 26 25 24 23 22 21 16 14 13 12 11 10 9 8 7 5 0
347 * +------+----+----+--+-+-----+-+---+-----+-----+-----+----+--+------+-+---+-----+-----+-----+----+-+----+
348 * | zero |TBI1|TBI0|AS|z| IPS |z|TG1| SH1 |ORGN1|IRGN1|EPD1|A1| T1SZ |z|TG0| SH0 |ORGN0|IRGN0|EPD0|z|T0SZ|
349 * +------+----+----+--+-+-----+-+---+-----+-----+-----+----+--+------+-+---+-----+-----+-----+----+-+----+
350 *
351 * Current (with 16KB granule support):
352 *
353 * 63 39 38 37 36 34 32 30 29 28 27 26 25 24 23 22 21 16 14 13 12 11 10 9 8 7 5 0
354 * +------+----+----+--+-+-----+-----+-----+-----+-----+----+--+------+-----+-----+-----+-----+----+-+----+
355 * | zero |TBI1|TBI0|AS|z| IPS | TG1 | SH1 |ORGN1|IRGN1|EPD1|A1| T1SZ | TG0 | SH0 |ORGN0|IRGN0|EPD0|z|T0SZ|
356 * +------+----+----+--+-+-----+-----+-----+-----+-----+----+--+------+-----+-----+-----+-----+----+-+----+
357 *
358 * TBI1 Top Byte Ignored for TTBR1 region
359 * TBI0 Top Byte Ignored for TTBR0 region
360 * AS ASID Size
361 * IPS Physical Address Size limit
362 * TG1 Granule Size for TTBR1 region
363 * SH1 Shareability for TTBR1 region
364 * ORGN1 Outer Cacheability for TTBR1 region
365 * IRGN1 Inner Cacheability for TTBR1 region
366 * EPD1 Translation table walk disable for TTBR1
367 * A1 ASID selection from TTBR1 enable
368 * T1SZ Virtual address size for TTBR1
369 * TG0 Granule Size for TTBR0 region
370 * SH0 Shareability for TTBR0 region
371 * ORGN0 Outer Cacheability for TTBR0 region
372 * IRGN0 Inner Cacheability for TTBR0 region
373 * T0SZ Virtual address size for TTBR0
374 */
375
376 #define TCR_T0SZ_SHIFT 0ULL
377 #define TCR_TSZ_BITS 6ULL
378 #define TCR_TSZ_MASK ((1ULL << TCR_TSZ_BITS) - 1ULL)
379
380 #define TCR_IRGN0_SHIFT 8ULL
381 #define TCR_IRGN0_DISABLED (0ULL << TCR_IRGN0_SHIFT)
382 #define TCR_IRGN0_WRITEBACK (1ULL << TCR_IRGN0_SHIFT)
383 #define TCR_IRGN0_WRITETHRU (2ULL << TCR_IRGN0_SHIFT)
384 #define TCR_IRGN0_WRITEBACKNO (3ULL << TCR_IRGN0_SHIFT)
385
386 #define TCR_ORGN0_SHIFT 10ULL
387 #define TCR_ORGN0_DISABLED (0ULL << TCR_ORGN0_SHIFT)
388 #define TCR_ORGN0_WRITEBACK (1ULL << TCR_ORGN0_SHIFT)
389 #define TCR_ORGN0_WRITETHRU (2ULL << TCR_ORGN0_SHIFT)
390 #define TCR_ORGN0_WRITEBACKNO (3ULL << TCR_ORGN0_SHIFT)
391
392 #define TCR_SH0_SHIFT 12ULL
393 #define TCR_SH0_NONE (0ULL << TCR_SH0_SHIFT)
394 #define TCR_SH0_OUTER (2ULL << TCR_SH0_SHIFT)
395 #define TCR_SH0_INNER (3ULL << TCR_SH0_SHIFT)
396
397 #define TCR_TG0_GRANULE_SHIFT (14ULL)
398
399 #define TCR_TG0_GRANULE_4KB (0ULL << TCR_TG0_GRANULE_SHIFT)
400 #define TCR_TG0_GRANULE_64KB (1ULL << TCR_TG0_GRANULE_SHIFT)
401 #define TCR_TG0_GRANULE_16KB (2ULL << TCR_TG0_GRANULE_SHIFT)
402
403 #if __ARM_16K_PG__
404 #define TCR_TG0_GRANULE_SIZE (TCR_TG0_GRANULE_16KB)
405 #else
406 #define TCR_TG0_GRANULE_SIZE (TCR_TG0_GRANULE_4KB)
407 #endif
408
409 #define TCR_T1SZ_SHIFT 16ULL
410
411 #define TCR_A1_ASID1 (1ULL << 22ULL)
412 #define TCR_EPD1_TTBR1_DISABLED (1ULL << 23ULL)
413
414 #define TCR_IRGN1_SHIFT 24ULL
415 #define TCR_IRGN1_DISABLED (0ULL << TCR_IRGN1_SHIFT)
416 #define TCR_IRGN1_WRITEBACK (1ULL << TCR_IRGN1_SHIFT)
417 #define TCR_IRGN1_WRITETHRU (2ULL << TCR_IRGN1_SHIFT)
418 #define TCR_IRGN1_WRITEBACKNO (3ULL << TCR_IRGN1_SHIFT)
419
420 #define TCR_ORGN1_SHIFT 26ULL
421 #define TCR_ORGN1_DISABLED (0ULL << TCR_ORGN1_SHIFT)
422 #define TCR_ORGN1_WRITEBACK (1ULL << TCR_ORGN1_SHIFT)
423 #define TCR_ORGN1_WRITETHRU (2ULL << TCR_ORGN1_SHIFT)
424 #define TCR_ORGN1_WRITEBACKNO (3ULL << TCR_ORGN1_SHIFT)
425
426 #define TCR_SH1_SHIFT 28ULL
427 #define TCR_SH1_NONE (0ULL << TCR_SH1_SHIFT)
428 #define TCR_SH1_OUTER (2ULL << TCR_SH1_SHIFT)
429 #define TCR_SH1_INNER (3ULL << TCR_SH1_SHIFT)
430
431 #define TCR_TG1_GRANULE_SHIFT 30ULL
432
433 #define TCR_TG1_GRANULE_16KB (1ULL << TCR_TG1_GRANULE_SHIFT)
434 #define TCR_TG1_GRANULE_4KB (2ULL << TCR_TG1_GRANULE_SHIFT)
435 #define TCR_TG1_GRANULE_64KB (3ULL << TCR_TG1_GRANULE_SHIFT)
436
437 #if __ARM_16K_PG__
438 #define TCR_TG1_GRANULE_SIZE (TCR_TG1_GRANULE_16KB)
439 #else
440 #define TCR_TG1_GRANULE_SIZE (TCR_TG1_GRANULE_4KB)
441 #endif
442
443 #define TCR_IPS_SHIFT 32ULL
444 #define TCR_IPS_32BITS (0ULL << TCR_IPS_SHIFT)
445 #define TCR_IPS_36BITS (1ULL << TCR_IPS_SHIFT)
446 #define TCR_IPS_40BITS (2ULL << TCR_IPS_SHIFT)
447 #define TCR_IPS_42BITS (3ULL << TCR_IPS_SHIFT)
448 #define TCR_IPS_44BITS (4ULL << TCR_IPS_SHIFT)
449 #define TCR_IPS_48BITS (5ULL << TCR_IPS_SHIFT)
450
451 #define TCR_AS_16BIT_ASID (1ULL << 36)
452 #define TCR_TBI0_TOPBYTE_IGNORED (1ULL << 37)
453 #define TCR_TBI1_TOPBYTE_IGNORED (1ULL << 38)
454
455 /*
456 * Multiprocessor Affinity Register (MPIDR_EL1)
457 *
458 * +64-----------------------------31+30+29-25+24+23-16+15-8+7--0+
459 * |000000000000000000000000000000001| U|00000|MT| Aff2|Aff1|Aff0|
460 * +---------------------------------+--+-----+--+-----+----+----+
461 *
462 * where
463 * U Uniprocessor
464 * MT Multi-threading at lowest affinity level
465 * Aff2 "1" - PCORE, "0" - ECORE
466 * Aff1 Cluster ID
467 * Aff0 CPU ID
468 */
469 #define MPIDR_PNE_SHIFT 16 // pcore not ecore
470 #define MPIDR_PNE (1 << MPIDR_PNE_SHIFT)
471 #define MPIDR_AFF0_MASK 0xFF
472 #define MPIDR_AFF1_MASK 0xFF00
473 #define MPIDR_AFF2_MASK 0xFF0000
474
475 /*
476 * We currently use a 3 level page table (rather than the full 4
477 * level page table). As a result, we do not have the full 48-bits
478 * of address space per TTBR (although the 16KB granule size lets us
479 * get very close).
480 */
481 #if __ARM64_TWO_LEVEL_PMAP__ && !__ARM_16K_PG__
482 #error ARM64 does not currently support a 2 level page table with 4KB pages
483 #endif /* __ARM64_TWO_LEVEL_PMAP__ */
484
485 /*
486 * TXSZ indicates the size of the range a TTBR covers. Currently,
487 * we support the following:
488 *
489 * 4KB pages, full page L1: 39 bit range.
490 * 4KB pages, sub-page L1: 36 bit range.
491 * 16KB pages, full page L1: 47 bit range.
492 * 16KB pages, sub-page L1: 37 bit range.
493 * 16KB pages, two level page tables: 36 bit range.
494 */
495 #ifdef __ARM_16K_PG__
496 #if __ARM64_TWO_LEVEL_PMAP__
497 #define T0SZ_BOOT 28ULL
498 #elif __ARM64_PMAP_SUBPAGE_L1__
499 #define T0SZ_BOOT 27ULL
500 #else /* __ARM64_TWO_LEVEL_PMAP__ */
501 #define T0SZ_BOOT 17ULL
502 #endif /* __ARM64_TWO_LEVEL_PMAP__ */
503 #else /* __ARM_16K_PG__ */
504 #if __ARM64_PMAP_SUBPAGE_L1__
505 #define T0SZ_BOOT 28ULL
506 #else /* __ARM64_PMAP_SUBPAGE_L1__ */
507 #define T0SZ_BOOT 25ULL
508 #endif /* __ARM64_PMAP_SUBPAGE_L1__ */
509 #endif /* __ARM_16K_PG__ */
510
511 #if defined(APPLE_ARM64_ARCH_FAMILY)
512 /* T0SZ must be the same as T1SZ */
513 #define T1SZ_BOOT T0SZ_BOOT
514 #else /* defined(APPLE_ARM64_ARCH_FAMILY) */
515 #ifdef __ARM_16K_PG__
516 #if __ARM64_TWO_LEVEL_PMAP__
517 #define T1SZ_BOOT 28ULL
518 #elif __ARM64_PMAP_SUBPAGE_L1__
519 #define T1SZ_BOOT 27ULL
520 #else /* __ARM64_TWO_LEVEL_PMAP__ */
521 #define T1SZ_BOOT 17ULL
522 #endif /* __ARM64_TWO_LEVEL_PMAP__ */
523 #else /* __ARM_16K_PG__ */
524 #if __ARM64_PMAP_SUBPAGE_L1__
525 #define T1SZ_BOOT 28ULL
526 #else /* __ARM64_PMAP_SUBPAGE_L1__ */
527 #define T1SZ_BOOT 25ULL
528 #endif /*__ARM64_PMAP_SUBPAGE_L1__*/
529 #endif /* __ARM_16K_PG__ */
530 #endif /* defined(APPLE_ARM64_ARCH_FAMILY) */
531
532 #define TCR_EL1_BOOT (TCR_IPS_40BITS | \
533 TCR_SH0_OUTER | TCR_ORGN0_WRITEBACK | TCR_IRGN0_WRITEBACK | (T0SZ_BOOT << TCR_T0SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE) |\
534 TCR_SH1_OUTER | TCR_ORGN1_WRITEBACK | TCR_IRGN1_WRITEBACK | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG1_GRANULE_SIZE))
535
536 /*
537 * Translation Table Base Register (TTBR)
538 *
539 * 63 48 47 x x-1 0
540 * +--------+------------------+------+
541 * | ASID | Base Address | zero |
542 * +--------+------------------+------+
543 *
544 */
545 #define TTBR_ASID_SHIFT 48
546 #define TTBR_ASID_MASK 0xffff000000000000
547
548 #define TTBR_BADDR_MASK 0x0000ffffffffffff
549
550 /*
551 * Memory Attribute Indirection Register
552 *
553 * 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
554 * +-------+-------+-------+-------+-------+-------+-------+-------+
555 * | Attr7 | Attr6 | Attr5 | Attr4 | Attr3 | Attr2 | Attr1 | Attr0 |
556 * +-------+-------+-------+-------+-------+-------+-------+-------+
557 *
558 */
559
560 #define MAIR_ATTR_SHIFT(x) (8*(x))
561
562 /* Strongly ordered or device memory attributes */
563 #define MAIR_OUTER_STRONGLY_ORDERED 0x0
564 #define MAIR_OUTER_DEVICE 0x0
565
566 #define MAIR_INNER_STRONGLY_ORDERED 0x0
567 #define MAIR_INNER_DEVICE 0x4
568
569 /* Normal memory attributes */
570 #define MAIR_OUTER_NON_CACHEABLE 0x40
571 #define MAIR_OUTER_WRITE_THROUGH 0x80
572 #define MAIR_OUTER_WRITE_BACK 0xc0
573
574 #define MAIR_INNER_NON_CACHEABLE 0x4
575 #define MAIR_INNER_WRITE_THROUGH 0x8
576 #define MAIR_INNER_WRITE_BACK 0xc
577
578 /* Allocate policy for cacheable memory */
579 #define MAIR_OUTER_WRITE_ALLOCATE 0x10
580 #define MAIR_OUTER_READ_ALLOCATE 0x20
581
582 #define MAIR_INNER_WRITE_ALLOCATE 0x1
583 #define MAIR_INNER_READ_ALLOCATE 0x2
584
585 /* Memory Atribute Encoding */
586
587 /* Device memory types:
588 G (gathering): multiple reads/writes can be combined
589 R (reordering): reads or writes may reach device out of program order
590 E (early-acknowledge): writes may return immediately (e.g. PCIe posted writes)
591 */
592 #define MAIR_DISABLE 0x00 /* Device Memory, nGnRnE (strongly ordered) */
593 #define MAIR_POSTED 0x04 /* Device Memory, nGnRE (strongly ordered, posted writes) */
594 #define MAIR_WRITECOMB 0x44 /* Normal Memory, Outer Non-Cacheable, Inner Non-Cacheable */
595 #define MAIR_WRITETHRU 0xBB /* Normal Memory, Outer Write-through, Inner Write-through */
596 #define MAIR_WRITEBACK 0xFF /* Normal Memory, Outer Write-back, Inner Write-back */
597 #define MAIR_INNERWRITEBACK 0x4F /* Normal Memory, Outer Non-Cacheable, Inner Write-back */
598
599
600 /*
601 * ARM 4-level Page Table support - 2*1024TB (2^48) of address space
602 */
603
604
605 /*
606 * Memory Attribute Index
607 */
608 #define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled */
609 #define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes */
610 #define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled */
611 #define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer */
612 #define CACHE_ATTRINDX_INNERWRITEBACK 0x4 /* inner cache enabled, buffer enabled, write allocate */
613 #define CACHE_ATTRINDX_POSTED 0x5 /* no cache, no buffer, posted writes */
614 #define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK
615
616 /*
617 * Access protection bit values (TTEs and PTEs)
618 */
619 #define AP_RWNA 0x0 /* priv=read-write, user=no-access */
620 #define AP_RWRW 0x1 /* priv=read-write, user=read-write */
621 #define AP_RONA 0x2 /* priv=read-only, user=no-access */
622 #define AP_RORO 0x3 /* priv=read-only, user=read-only */
623 #define AP_MASK 0x3 /* mask to find ap bits */
624
625 /*
626 * Shareability attributes
627 */
628 #define SH_NONE 0x0 /* Non shareable */
629 #define SH_NONE 0x0 /* Device shareable */
630 #define SH_DEVICE 0x2 /* Normal memory Inner non shareable - Outer non shareable */
631 #define SH_OUTER_MEMORY 0x2 /* Normal memory Inner shareable - Outer shareable */
632 #define SH_INNER_MEMORY 0x3 /* Normal memory Inner shareable - Outer non shareable */
633
634
635 /*
636 * ARM Page Granule
637 */
638 #ifdef __ARM_16K_PG__
639 #define ARM_PGSHIFT 14
640 #else
641 #define ARM_PGSHIFT 12
642 #endif
643 #define ARM_PGBYTES (1 << ARM_PGSHIFT)
644 #define ARM_PGMASK (ARM_PGBYTES-1)
645
646
647 /*
648 * L0 Translation table
649 *
650 * 4KB granule size:
651 * Each translation table is 4KB
652 * 512 64-bit entries of 512GB (2^39) of address space.
653 * Covers 256TB (2^48) of address space.
654 *
655 * 16KB granule size:
656 * Each translation table is 16KB
657 * 2 64-bit entries of 128TB (2^47) of address space.
658 * Covers 256TB (2^48) of address space.
659 */
660
661 #ifdef __ARM_16K_PG__
662 #define ARM_TT_L0_SIZE 0x0000800000000000ULL /* size of area covered by a tte */
663 #define ARM_TT_L0_OFFMASK 0x00007fffffffffffULL /* offset within an L0 entry */
664 #define ARM_TT_L0_SHIFT 47 /* page descriptor shift */
665 #define ARM_TT_L0_INDEX_MASK 0x0000800000000000ULL /* mask for getting index in L0 table from virtual address */
666 #else
667 #define ARM_TT_L0_SIZE 0x0000008000000000ULL /* size of area covered by a tte */
668 #define ARM_TT_L0_OFFMASK 0x0000007fffffffffULL /* offset within an L0 entry */
669 #define ARM_TT_L0_SHIFT 39 /* page descriptor shift */
670 #define ARM_TT_L0_INDEX_MASK 0x0000ff8000000000ULL /* mask for getting index in L0 table from virtual address */
671 #endif
672
673 /*
674 * L1 Translation table
675 *
676 * 4KB granule size:
677 * Each translation table is 4KB
678 * 512 64-bit entries of 1GB (2^30) of address space.
679 * Covers 512GB (2^39) of address space.
680 *
681 * 16KB granule size:
682 * Each translation table is 16KB
683 * 2048 64-bit entries of 64GB (2^36) of address space.
684 * Covers 128TB (2^47) of address space.
685 */
686
687 #ifdef __ARM_16K_PG__
688 #define ARM_TT_L1_SIZE 0x0000001000000000ULL /* size of area covered by a tte */
689 #define ARM_TT_L1_OFFMASK 0x0000000fffffffffULL /* offset within an L1 entry */
690 #define ARM_TT_L1_SHIFT 36 /* page descriptor shift */
691 #ifdef __ARM64_PMAP_SUBPAGE_L1__
692 /* This config supports 128GB per TTBR. */
693 #define ARM_TT_L1_INDEX_MASK 0x0000001000000000ULL /* mask for getting index into L1 table from virtual address */
694 #else
695 #define ARM_TT_L1_INDEX_MASK 0x00007ff000000000ULL /* mask for getting index into L1 table from virtual address */
696 #endif
697 #else
698 #define ARM_TT_L1_SIZE 0x0000000040000000ULL /* size of area covered by a tte */
699 #define ARM_TT_L1_OFFMASK 0x000000003fffffffULL /* offset within an L1 entry */
700 #define ARM_TT_L1_SHIFT 30 /* page descriptor shift */
701 #ifdef __ARM64_PMAP_SUBPAGE_L1__
702 /* This config supports 64GB per TTBR. */
703 #define ARM_TT_L1_INDEX_MASK 0x0000000fc0000000ULL /* mask for getting index into L1 table from virtual address */
704 #else
705 #define ARM_TT_L1_INDEX_MASK 0x0000007fc0000000ULL /* mask for getting index into L1 table from virtual address */
706 #endif
707 #endif
708
709 /*
710 * L2 Translation table
711 *
712 * 4KB granule size:
713 * Each translation table is 4KB
714 * 512 64-bit entries of 2MB (2^21) of address space.
715 * Covers 1GB (2^30) of address space.
716 *
717 * 16KB granule size:
718 * Each translation table is 16KB
719 * 2048 64-bit entries of 32MB (2^25) of address space.
720 * Covers 64GB (2^36) of address space.
721 */
722
723 #ifdef __ARM_16K_PG__
724 #define ARM_TT_L2_SIZE 0x0000000002000000ULL /* size of area covered by a tte */
725 #define ARM_TT_L2_OFFMASK 0x0000000001ffffffULL /* offset within an L2 entry */
726 #define ARM_TT_L2_SHIFT 25 /* page descriptor shift */
727 #define ARM_TT_L2_INDEX_MASK 0x0000000ffe000000ULL /* mask for getting index in L2 table from virtual address */
728 #else
729 #define ARM_TT_L2_SIZE 0x0000000000200000ULL /* size of area covered by a tte */
730 #define ARM_TT_L2_OFFMASK 0x00000000001fffffULL /* offset within an L2 entry */
731 #define ARM_TT_L2_SHIFT 21 /* page descriptor shift */
732 #define ARM_TT_L2_INDEX_MASK 0x000000003fe00000ULL /* mask for getting index in L2 table from virtual address */
733 #endif
734
735 /*
736 * L3 Translation table
737 *
738 * 4KB granule size:
739 * Each translation table is 4KB
740 * 512 64-bit entries of 4KB (2^12) of address space.
741 * Covers 2MB (2^21) of address space.
742 *
743 * 16KB granule size:
744 * Each translation table is 16KB
745 * 2048 64-bit entries of 16KB (2^14) of address space.
746 * Covers 32MB (2^25) of address space.
747 */
748
749 #ifdef __ARM_16K_PG__
750 #define ARM_TT_L3_SIZE 0x0000000000004000ULL /* size of area covered by a tte */
751 #define ARM_TT_L3_OFFMASK 0x0000000000003fffULL /* offset within L3 PTE */
752 #define ARM_TT_L3_SHIFT 14 /* page descriptor shift */
753 #define ARM_TT_L3_INDEX_MASK 0x0000000001ffc000ULL /* mask for page descriptor index */
754 #else
755 #define ARM_TT_L3_SIZE 0x0000000000001000ULL /* size of area covered by a tte */
756 #define ARM_TT_L3_OFFMASK 0x0000000000000fffULL /* offset within L3 PTE */
757 #define ARM_TT_L3_SHIFT 12 /* page descriptor shift */
758 #define ARM_TT_L3_INDEX_MASK 0x00000000001ff000ULL /* mask for page descriptor index */
759 #endif
760
761 /*
762 * Convenience definitions for:
763 * ARM_TT_LEAF: The last level of the configured page table format.
764 * ARM_TT_TWIG: The second to last level of the configured page table format.
765 *
766 * My apologies to any botanists who may be reading this.
767 */
768 #define ARM_TT_LEAF_SIZE ARM_TT_L3_SIZE
769 #define ARM_TT_LEAF_OFFMASK ARM_TT_L3_OFFMASK
770 #define ARM_TT_LEAF_SHIFT ARM_TT_L3_SHIFT
771 #define ARM_TT_LEAF_INDEX_MASK ARM_TT_L3_INDEX_MASK
772
773 #define ARM_TT_TWIG_SIZE ARM_TT_L2_SIZE
774 #define ARM_TT_TWIG_OFFMASK ARM_TT_L2_OFFMASK
775 #define ARM_TT_TWIG_SHIFT ARM_TT_L2_SHIFT
776 #define ARM_TT_TWIG_INDEX_MASK ARM_TT_L2_INDEX_MASK
777
778 /*
779 * 4KB granule size:
780 *
781 * Level 0 Translation Table Entry
782 *
783 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0
784 * +--+-----+--+---+-------+------+----------------------+-------+-+-+
785 * |NS| AP |XN|PXN|ignored| zero | L1TableOutputAddress |ignored|1|V|
786 * +--+-----+--+---+-------+------+----------------------+-------+-+-+
787 *
788 * Level 1 Translation Table Entry
789 *
790 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0
791 * +--+-----+--+---+-------+------+----------------------+-------+-+-+
792 * |NS| AP |XN|PXN|ignored| zero | L2TableOutputAddress |ignored|1|V|
793 * +--+-----+--+---+-------+------+----------------------+-------+-+-+
794 *
795 * Level 1 Translation Block Entry
796 *
797 * 63 59 58 55 54 53 52 51 48 47 30 29 12 11 10 9 8 7 6 5 4 2 1 0
798 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+
799 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:30] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V|
800 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+
801 *
802 * Level 2 Translation Table Entry
803 *
804 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0
805 * +--+-----+--+---+-------+------+----------------------+-------+-+-+
806 * |NS| AP |XN|PXN|ignored| zero | L3TableOutputAddress |ignored|1|V|
807 * +--+-----+--+---+-------+------+----------------------+-------+-+-+
808 *
809 * Level 2 Translation Block Entry
810 *
811 * 63 59 58 55 54 53 52 51 48 47 21 20 12 11 10 9 8 7 6 5 4 2 1 0
812 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+
813 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:21] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V|
814 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+
815 *
816 * 16KB granule size:
817 *
818 * Level 0 Translation Table Entry
819 *
820 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0
821 * +--+-----+--+---+-------+------+----------------------+-------+-+-+
822 * |NS| AP |XN|PXN|ignored| zero | L1TableOutputAddress |ignored|1|V|
823 * +--+-----+--+---+-------+------+----------------------+-------+-+-+
824 *
825 * Level 1 Translation Table Entry
826 *
827 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0
828 * +--+-----+--+---+-------+------+----------------------+-------+-+-+
829 * |NS| AP |XN|PXN|ignored| zero | L2TableOutputAddress |ignored|1|V|
830 * +--+-----+--+---+-------+------+----------------------+-------+-+-+
831 *
832 * Level 2 Translation Table Entry
833 *
834 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0
835 * +--+-----+--+---+-------+------+----------------------+-------+-+-+
836 * |NS| AP |XN|PXN|ignored| zero | L3TableOutputAddress |ignored|1|V|
837 * +--+-----+--+---+-------+------+----------------------+-------+-+-+
838 *
839 * Level 2 Translation Block Entry
840 *
841 * 63 59 58 55 54 53 52 51 48 47 25 24 12 11 10 9 8 7 6 5 4 2 1 0
842 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+
843 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:25] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V|
844 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+
845 *
846 * where:
847 * 'nG' notGlobal bit
848 * 'SH' Shareability field
849 * 'AP' access protection
850 * 'XN' eXecute Never bit
851 * 'PXN' Privilege eXecute Never bit
852 * 'NS' Non-Secure bit
853 * 'HINT' 16 entry continuguous output hint
854 * 'AttrIdx' Memory Attribute Index
855 */
856
857 #define TTE_SHIFT 3 /* shift width of a tte (sizeof(tte) == (1 << TTE_SHIFT)) */
858 #ifdef __ARM_16K_PG__
859 #define TTE_PGENTRIES (16384 >> TTE_SHIFT) /* number of ttes per page */
860 #else
861 #define TTE_PGENTRIES (4096 >> TTE_SHIFT) /* number of ttes per page */
862 #endif
863
864 #define ARM_TTE_MAX (TTE_PGENTRIES)
865
866 #define ARM_TTE_EMPTY 0x0000000000000000ULL /* unasigned - invalid entry */
867 #define ARM_TTE_TYPE_FAULT 0x0000000000000000ULL /* unasigned - invalid entry */
868
869 #define ARM_TTE_VALID 0x0000000000000001ULL /* valid entry */
870
871 #define ARM_TTE_TYPE_MASK 0x0000000000000002ULL /* mask for extracting the type */
872 #define ARM_TTE_TYPE_TABLE 0x0000000000000002ULL /* page table type */
873 #define ARM_TTE_TYPE_BLOCK 0x0000000000000000ULL /* block entry type */
874 #define ARM_TTE_TYPE_L3BLOCK 0x0000000000000002ULL
875 #define ARM_TTE_TYPE_MASK 0x0000000000000002ULL /* mask for extracting the type */
876
877 #ifdef __ARM_16K_PG__
878 /* Note that L0/L1 block entries are disallowed for the 16KB granule size; what are we doing with these? */
879 #define ARM_TTE_BLOCK_SHIFT 12 /* entry shift for a 16KB L3 TTE entry */
880 #define ARM_TTE_BLOCK_L0_SHIFT ARM_TT_L0_SHIFT /* block shift for 128TB section */
881 #define ARM_TTE_BLOCK_L1_MASK 0x0000fff000000000ULL /* mask to extract phys address from L1 block entry */
882 #define ARM_TTE_BLOCK_L1_SHIFT ARM_TT_L1_SHIFT /* block shift for 64GB section */
883 #define ARM_TTE_BLOCK_L2_MASK 0x0000fffffe000000ULL /* mask to extract phys address from Level 2 Translation Block entry */
884 #define ARM_TTE_BLOCK_L2_SHIFT ARM_TT_L2_SHIFT /* block shift for 32MB section */
885 #else
886 #define ARM_TTE_BLOCK_SHIFT 12 /* entry shift for a 4KB L3 TTE entry */
887 #define ARM_TTE_BLOCK_L0_SHIFT ARM_TT_L0_SHIFT /* block shift for 2048GB section */
888 #define ARM_TTE_BLOCK_L1_MASK 0x0000ffffc0000000ULL /* mask to extract phys address from L1 block entry */
889 #define ARM_TTE_BLOCK_L1_SHIFT ARM_TT_L1_SHIFT /* block shift for 1GB section */
890 #define ARM_TTE_BLOCK_L2_MASK 0x0000ffffffe00000ULL /* mask to extract phys address from Level 2 Translation Block entry */
891 #define ARM_TTE_BLOCK_L2_SHIFT ARM_TT_L2_SHIFT /* block shift for 2MB section */
892 #endif
893
894 #define ARM_TTE_BLOCK_APSHIFT 6
895 #define ARM_TTE_BLOCK_AP(x) ((x)<<ARM_TTE_BLOCK_APSHIFT) /* access protection */
896 #define ARM_TTE_BLOCK_APMASK (0x3 << ARM_TTE_BLOCK_APSHIFT)
897
898 #define ARM_TTE_BLOCK_ATTRINDX(x) ((x) << 2) /* memory attributes index */
899 #define ARM_TTE_BLOCK_ATTRINDXMASK (0x7ULL << 2) /* mask memory attributes index */
900
901 #define ARM_TTE_BLOCK_SH(x) ((x) << 8) /* access shared */
902 #define ARM_TTE_BLOCK_SHMASK (0x3ULL << 8) /* mask access shared */
903
904 #define ARM_TTE_BLOCK_AF 0x0000000000000400ULL /* value for access */
905 #define ARM_TTE_BLOCK_AFMASK 0x0000000000000400ULL /* access mask */
906
907 #define ARM_TTE_BLOCK_NG 0x0000000000000800ULL /* value for a global mapping */
908 #define ARM_TTE_BLOCK_NG_MASK 0x0000000000000800ULL /* notGlobal mapping mask */
909
910 #define ARM_TTE_BLOCK_NS 0x0000000000000020ULL /* value for a secure mapping */
911 #define ARM_TTE_BLOCK_NS_MASK 0x0000000000000020ULL /* notSecure mapping mask */
912
913 #define ARM_TTE_BLOCK_PNX 0x0020000000000000ULL /* value for privilege no execute bit */
914 #define ARM_TTE_BLOCK_PNXMASK 0x0020000000000000ULL /* privilege execute mask */
915
916 #define ARM_TTE_BLOCK_NX 0x0040000000000000ULL /* value for no execute */
917 #define ARM_TTE_BLOCK_NXMASK 0x0040000000000000ULL /* no execute mask */
918
919 #define ARM_TTE_BLOCK_WIRED 0x0080000000000000ULL /* value for software wired bit */
920 #define ARM_TTE_BLOCK_WIREDMASK 0x0080000000000000ULL /* software wired mask */
921
922 #define ARM_TTE_BLOCK_WRITEABLE 0x0100000000000000ULL /* value for software writeable bit */
923 #define ARM_TTE_BLOCK_WRITEABLEMASK 0x0100000000000000ULL /* software writeable mask */
924
925 #ifdef __ARM_16K_PG__
926 /*
927 * TODO: Do we care about the low bits being unused? It should technically work either way, but masking them out should be future proof;
928 * it is only a matter of time before someone wants to shove something into the free bits.
929 */
930 #define ARM_TTE_TABLE_MASK (0x0000ffffffffc000ULL) /* mask for extracting pointer to next table (works at any level) */
931 #else
932 #define ARM_TTE_TABLE_MASK (0x0000fffffffff000ULL) /* mask for extracting pointer to next table (works at any level) */
933 #endif
934
935 #define ARM_TTE_TABLE_APSHIFT 61
936 #define ARM_TTE_TABLE_AP(x) ((x)<<TTE_BLOCK_APSHIFT) /* access protection */
937
938 #define ARM_TTE_TABLE_NS 0x8000000000000020ULL /* value for a secure mapping */
939 #define ARM_TTE_TABLE_NS_MASK 0x8000000000000020ULL /* notSecure mapping mask */
940
941 #define ARM_TTE_TABLE_XN 0x1000000000000000ULL /* value for no execute */
942 #define ARM_TTE_TABLE_XNMASK 0x1000000000000000ULL /* no execute mask */
943
944 #define ARM_TTE_TABLE_PXN 0x0800000000000000ULL /* value for privilege no execute bit */
945 #define ARM_TTE_TABLE_PXNMASK 0x0800000000000000ULL /* privilege execute mask */
946
947 #define ARM_TTE_BOOT_BLOCK (ARM_TTE_TYPE_BLOCK | ARM_TTE_VALID | ARM_TTE_BLOCK_SH(SH_OUTER_MEMORY) \
948 | ARM_TTE_BLOCK_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_TTE_BLOCK_AF)
949
950 #define ARM_TTE_BOOT_TABLE (ARM_TTE_TYPE_TABLE | ARM_TTE_VALID )
951 /*
952 * L3 Translation table
953 *
954 * 4KB granule size:
955 * Each translation table is 4KB
956 * 512 64-bit entries of 4KB (2^12) of address space.
957 * Covers 2MB (2^21) of address space.
958 *
959 * 16KB granule size:
960 * Each translation table is 16KB
961 * 2048 64-bit entries of 16KB (2^14) of address space.
962 * Covers 32MB (2^25) of address space.
963 */
964
965 #ifdef __ARM_16K_PG__
966 #define ARM_PTE_SIZE 0x0000000000004000ULL /* size of area covered by a tte */
967 #define ARM_PTE_OFFMASK 0x0000000000003fffULL /* offset within pte area */
968 #define ARM_PTE_SHIFT 14 /* page descriptor shift */
969 #define ARM_PTE_MASK 0x0000ffffffffc000ULL /* mask for output address in PTE */
970 #else
971 #define ARM_PTE_SIZE 0x0000000000001000ULL /* size of area covered by a tte */
972 #define ARM_PTE_OFFMASK 0x0000000000000fffULL /* offset within pte area */
973 #define ARM_PTE_SHIFT 12 /* page descriptor shift */
974 #define ARM_PTE_MASK 0x0000fffffffff000ULL /* mask for output address in PTE */
975 #endif
976
977 /*
978 * L3 Page table entries
979 *
980 * The following page table entry types are possible:
981 *
982 * fault page entry
983 * 63 2 0
984 * +------------------------------+--+
985 * | ignored |00|
986 * +------------------------------+--+
987 *
988 *
989 * 63 59 58 55 54 53 52 51 48 47 12 11 10 9 8 7 6 5 4 2 1 0
990 * +-----+------+--+---+----+------+----------------------+--+--+----+----+--+-------+-+-+
991 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:12] |nG|AF| SH | AP |NS|AttrIdx|1|V|
992 * +-----+------+--+---+----+------+----------------------+--+--+----+----+--+-------+-+-+
993 *
994 * where:
995 * 'nG' notGlobal bit
996 * 'SH' Shareability field
997 * 'AP' access protection
998 * 'XN' eXecute Never bit
999 * 'PXN' Privilege eXecute Never bit
1000 * 'NS' Non-Secure bit
1001 * 'HINT' 16 entry continuguous output hint
1002 * 'AttrIdx' Memory Attribute Index
1003 */
1004
1005 #define PTE_SHIFT 3 /* shift width of a pte (sizeof(pte) == (1 << PTE_SHIFT)) */
1006 #ifdef __ARM_16K_PG__
1007 #define PTE_PGENTRIES (16384 >> PTE_SHIFT) /* number of ptes per page */
1008 #else
1009 #define PTE_PGENTRIES (4096 >> PTE_SHIFT) /* number of ptes per page */
1010 #endif
1011
1012 #define ARM_PTE_EMPTY 0x0000000000000000ULL /* unasigned - invalid entry */
1013
1014 /* markers for (invalid) PTE for a page sent to compressor */
1015 #define ARM_PTE_COMPRESSED 0x8000000000000000ULL /* compressed... */
1016 #define ARM_PTE_COMPRESSED_ALT 0x4000000000000000ULL /* ... and was "alt_acct" */
1017 #define ARM_PTE_COMPRESSED_MASK 0xC000000000000000ULL
1018 #define ARM_PTE_IS_COMPRESSED(x) \
1019 ((((x) & 0x3) == 0) && /* PTE is not valid... */ \
1020 ((x) & ARM_PTE_COMPRESSED) && /* ...has "compressed" marker" */ \
1021 ((!((x) & ~ARM_PTE_COMPRESSED_MASK)) || /* ...no other bits */ \
1022 (panic("compressed PTE %p 0x%llx has extra bits 0x%llx: corrupted?", \
1023 &(x), (x), (x) & ~ARM_PTE_COMPRESSED_MASK), FALSE)))
1024
1025 #define ARM_PTE_TYPE 0x0000000000000003ULL /* valid L3 entry: includes bit #1 (counterintuitively) */
1026 #define ARM_PTE_TYPE_VALID 0x0000000000000003ULL /* valid L3 entry: includes bit #1 (counterintuitively) */
1027 #define ARM_PTE_TYPE_FAULT 0x0000000000000000ULL /* invalid L3 entry */
1028 #define ARM_PTE_TYPE_MASK 0x0000000000000002ULL /* mask to get pte type */
1029
1030 #ifdef __ARM_16K_PG__
1031 /* TODO: What does the shift mean here? */
1032 #define ARM_PTE_PAGE_MASK 0x0000FFFFFFFFC000ULL /* mask for 16KB page */
1033 #else
1034 #define ARM_PTE_PAGE_MASK 0x0000FFFFFFFFF000ULL /* mask for 4KB page */
1035 #define ARM_PTE_PAGE_SHIFT 12 /* page shift for 4KB page */
1036 #endif
1037
1038 #define ARM_PTE_AP(x) ((x) << 6) /* access protections */
1039 #define ARM_PTE_APMASK (0x3ULL << 6) /* mask access protections */
1040 #define ARM_PTE_EXTRACT_AP(x) (((x) >> 6) & 0x3ULL) /* extract access protections from PTE */
1041
1042 #define ARM_PTE_ATTRINDX(x) ((x) << 2) /* memory attributes index */
1043 #define ARM_PTE_ATTRINDXMASK (0x7ULL << 2) /* mask memory attributes index */
1044
1045 #define ARM_PTE_SH(x) ((x) << 8) /* access shared */
1046 #define ARM_PTE_SHMASK (0x3ULL << 8) /* mask access shared */
1047
1048 #define ARM_PTE_AF 0x0000000000000400ULL /* value for access */
1049 #define ARM_PTE_AFMASK 0x0000000000000400ULL /* access mask */
1050
1051 #define ARM_PTE_NG 0x0000000000000800ULL /* value for a global mapping */
1052 #define ARM_PTE_NG_MASK 0x0000000000000800ULL /* notGlobal mapping mask */
1053
1054 #define ARM_PTE_NS 0x0000000000000020ULL /* value for a secure mapping */
1055 #define ARM_PTE_NS_MASK 0x0000000000000020ULL /* notSecure mapping mask */
1056
1057 #define ARM_PTE_HINT 0x0010000000000000ULL /* value for contiguous entries hint */
1058 #define ARM_PTE_HINT_MASK 0x0010000000000000ULL /* mask for contiguous entries hint */
1059
1060 #if __ARM_16K_PG__
1061 #define ARM_PTE_HINT_ENTRIES 128ULL /* number of entries the hint covers */
1062 #define ARM_PTE_HINT_ENTRIES_SHIFT 7ULL /* shift to construct the number of entries */
1063 #define ARM_PTE_HINT_ADDR_MASK 0x0000FFFFFFE00000ULL /* mask to extract the starting hint address */
1064 #define ARM_PTE_HINT_ADDR_SHIFT 21 /* shift for the hint address */
1065 #else
1066 #define ARM_PTE_HINT_ENTRIES 16ULL /* number of entries the hint covers */
1067 #define ARM_PTE_HINT_ENTRIES_SHIFT 4ULL /* shift to construct the number of entries */
1068 #define ARM_PTE_HINT_ADDR_MASK 0x0000FFFFFFFF0000ULL /* mask to extract the starting hint address */
1069 #define ARM_PTE_HINT_ADDR_SHIFT 16 /* shift for the hint address */
1070 #endif
1071
1072 #define ARM_PTE_PNX 0x0020000000000000ULL /* value for no execute */
1073 #define ARM_PTE_PNXMASK 0x0020000000000000ULL /* no execute mask */
1074
1075 #define ARM_PTE_NX 0x0040000000000000ULL /* value for privilege no execute bit */
1076 #define ARM_PTE_NXMASK 0x0040000000000000ULL /* privilege execute mask */
1077
1078 #define ARM_PTE_WIRED 0x0080000000000000ULL /* value for software wired bit */
1079 #define ARM_PTE_WIRED_MASK 0x0080000000000000ULL /* software wired mask */
1080
1081 #define ARM_PTE_WRITEABLE 0x0100000000000000ULL /* value for software writeable bit */
1082 #define ARM_PTE_WRITEABLE_MASK 0x0100000000000000ULL /* software writeable mask */
1083
1084 #if CONFIG_PGTRACE
1085 #define ARM_PTE_PGTRACE 0x0200000000000000ULL /* value for software trace bit */
1086 #define ARM_PTE_PGTRACE_MASK 0x0200000000000000ULL /* software trace mask */
1087 #endif
1088
1089 #define ARM_PTE_BOOT_PAGE (ARM_PTE_TYPE_VALID | ARM_PTE_SH(SH_OUTER_MEMORY) \
1090 | ARM_PTE_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_PTE_AF)
1091
1092 /*
1093 * Exception Syndrome Register
1094 *
1095 * 31 26 25 24 0
1096 * +------+--+------------------+
1097 * | EC |IL| ISS |
1098 * +------+--+------------------+
1099 *
1100 * EC - Exception Class
1101 * IL - Instruction Length
1102 * ISS- Instruction Specific Syndrome
1103 *
1104 * Note: The ISS can have many forms. These are defined separately below.
1105 */
1106
1107 #define ESR_EC_SHIFT 26
1108 #define ESR_EC_MASK (0x3F << ESR_EC_SHIFT)
1109 #define ESR_EC(x) ((x & ESR_EC_MASK) >> ESR_EC_SHIFT)
1110
1111 #define ESR_IL_SHIFT 25
1112 #define ESR_IL (1 << ESR_IL_SHIFT)
1113
1114 #define ESR_INSTR_IS_2BYTES(x) (!(x & ESR_IL))
1115
1116 #define ESR_ISS_MASK 0x01FFFFFF
1117 #define ESR_ISS(x) (x & ESR_ISS_MASK)
1118
1119 #ifdef __ASSEMBLER__
1120 /* Define only the classes we need to test in the exception vectors. */
1121 #define ESR_EC_IABORT_EL1 0x21
1122 #define ESR_EC_DABORT_EL1 0x25
1123 #define ESR_EC_SP_ALIGN 0x26
1124 #else
1125 typedef enum {
1126 ESR_EC_UNCATEGORIZED = 0x00,
1127 ESR_EC_WFI_WFE = 0x01,
1128 ESR_EC_MCR_MRC_CP15_TRAP = 0x03,
1129 ESR_EC_MCRR_MRRC_CP15_TRAP = 0x04,
1130 ESR_EC_MCR_MRC_CP14_TRAP = 0x05,
1131 ESR_EC_LDC_STC_CP14_TRAP = 0x06,
1132 ESR_EC_TRAP_SIMD_FP = 0x07,
1133 ESR_EC_MCRR_MRRC_CP14_TRAP = 0x0c,
1134 ESR_EC_ILLEGAL_INSTR_SET = 0x0e,
1135 ESR_EC_SVC_32 = 0x11,
1136 ESR_EC_SVC_64 = 0x15,
1137 ESR_EC_MSR_TRAP = 0x18,
1138 ESR_EC_IABORT_EL0 = 0x20,
1139 ESR_EC_IABORT_EL1 = 0x21,
1140 ESR_EC_PC_ALIGN = 0x22,
1141 ESR_EC_DABORT_EL0 = 0x24,
1142 ESR_EC_DABORT_EL1 = 0x25,
1143 ESR_EC_SP_ALIGN = 0x26,
1144 ESR_EC_FLOATING_POINT_32 = 0x28,
1145 ESR_EC_FLOATING_POINT_64 = 0x2C,
1146 ESR_EC_BKPT_REG_MATCH_EL0 = 0x30, // Breakpoint Debug event taken to the EL from a lower EL.
1147 ESR_EC_BKPT_REG_MATCH_EL1 = 0x31, // Breakpoint Debug event taken to the EL from the EL.
1148 ESR_EC_SW_STEP_DEBUG_EL0 = 0x32, // Software Step Debug event taken to the EL from a lower EL.
1149 ESR_EC_SW_STEP_DEBUG_EL1 = 0x33, // Software Step Debug event taken to the EL from the EL.
1150 ESR_EC_WATCHPT_MATCH_EL0 = 0x34, // Watchpoint Debug event taken to the EL from a lower EL.
1151 ESR_EC_WATCHPT_MATCH_EL1 = 0x35, // Watchpoint Debug event taken to the EL from the EL.
1152 ESR_EC_BKPT_AARCH32 = 0x38,
1153 ESR_EC_BRK_AARCH64 = 0x3C
1154 } esr_exception_class_t;
1155
1156 typedef enum {
1157 FSC_TRANSLATION_FAULT_L0 = 0x04,
1158 FSC_TRANSLATION_FAULT_L1 = 0x05,
1159 FSC_TRANSLATION_FAULT_L2 = 0x06,
1160 FSC_TRANSLATION_FAULT_L3 = 0x07,
1161 FSC_ACCESS_FLAG_FAULT_L1 = 0x09,
1162 FSC_ACCESS_FLAG_FAULT_L2 = 0x0A,
1163 FSC_ACCESS_FLAG_FAULT_L3 = 0x0B,
1164 FSC_PERMISSION_FAULT_L1 = 0x0D,
1165 FSC_PERMISSION_FAULT_L2 = 0x0E,
1166 FSC_PERMISSION_FAULT_L3 = 0x0F,
1167 FSC_SYNC_EXT_ABORT = 0x10,
1168 FSC_ASYNC_EXT_ABORT = 0x11,
1169 FSC_SYNC_EXT_ABORT_TT_L1 = 0x15,
1170 FSC_SYNC_EXT_ABORT_TT_L2 = 0x16,
1171 FSC_SYNC_EXT_ABORT_TT_L3 = 0x17,
1172 FSC_SYNC_PARITY = 0x18,
1173 FSC_ASYNC_PARITY = 0x19,
1174 FSC_SYNC_PARITY_TT_L1 = 0x1D,
1175 FSC_SYNC_PARITY_TT_L2 = 0x1E,
1176 FSC_SYNC_PARITY_TT_L3 = 0x1F,
1177 FSC_ALIGNMENT_FAULT = 0x21,
1178 FSC_DEBUG_FAULT = 0x22
1179 } fault_status_t;
1180 #endif /* ASSEMBLER */
1181
1182 /*
1183 * Software step debug event ISS (EL1)
1184 * 24 23 6 5 0
1185 * +---+-----------------+--+------+
1186 * |ISV|00000000000000000|EX| IFSC |
1187 * +---+-----------------+--+------+
1188 *
1189 * where:
1190 * ISV Instruction syndrome valid
1191 * EX Exclusive access
1192 * IFSC Instruction Fault Status Code
1193 */
1194
1195 #define ISS_SSDE_ISV_SHIFT 24
1196 #define ISS_SSDE_ISV (0x1 << ISS_SSDE_ISV_SHIFT)
1197
1198 #define ISS_SSDE_EX_SHIFT 6
1199 #define ISS_SSDE_EX (0x1 << ISS_SSDE_EX_SHIFT)
1200
1201 #define ISS_SSDE_FSC_MASK 0x3F
1202 #define ISS_SSDE_FSC(x) (x & ISS_SSDE_FSC_MASK)
1203
1204 /*
1205 * Instruction Abort ISS (EL1)
1206 * 24 10 9 5 0
1207 * +---------------+--+---+------+
1208 * |000000000000000|EA|000| IFSC |
1209 * +---------------+--+---+------+
1210 *
1211 * where:
1212 * EA External Abort type
1213 * IFSC Instruction Fault Status Code
1214 */
1215
1216 #define ISS_IA_EA_SHIFT 9
1217 #define ISS_IA_EA (0x1 << ISS_IA_EA_SHIFT)
1218
1219 #define ISS_IA_FSC_MASK 0x3F
1220 #define ISS_IA_FSC(x) (x & ISS_IA_FSC_MASK)
1221
1222
1223 /*
1224 * Data Abort ISS (EL1)
1225 *
1226 * 24 9 8 7 6 5 0
1227 * +---------------+--+--+-+---+----+
1228 * |000000000000000|EA|CM|0|WnR|DFSC|
1229 * +---------------+--+--+-+---+----+
1230 *
1231 * where:
1232 * EA External Abort type
1233 * CM Cache Maintenance operation
1234 * WnR Write not Read
1235 * DFSC Data Fault Status Code
1236 */
1237 #define ISS_DA_EA_SHIFT 9
1238 #define ISS_DA_EA (0x1 << ISS_DA_EA_SHIFT)
1239
1240 #define ISS_DA_CM_SHIFT 8
1241 #define ISS_DA_CM (0x1 << ISS_DA_CM_SHIFT)
1242
1243 #define ISS_DA_WNR_SHIFT 6
1244 #define ISS_DA_WNR (0x1 << ISS_DA_WNR_SHIFT)
1245
1246 #define ISS_DA_FSC_MASK 0x3F
1247 #define ISS_DA_FSC(x) (x & ISS_DA_FSC_MASK)
1248
1249 /*
1250 * Physical Address Register (EL1)
1251 */
1252 #define PAR_F_SHIFT 0
1253 #define PAR_F (0x1 << PAR_F_SHIFT)
1254
1255 #define PLATFORM_SYSCALL_TRAP_NO 0x80000000
1256
1257 #define ARM64_SYSCALL_CODE_REG_NUM (16)
1258
1259 #define ARM64_CLINE_SHIFT 6
1260
1261 #if defined(APPLE_ARM64_ARCH_FAMILY)
1262 #define L2CERRSTS_DATSBEESV (1ULL << 2) /* L2C data single bit ECC error */
1263 #define L2CERRSTS_DATDBEESV (1ULL << 4) /* L2C data double bit ECC error */
1264 #endif
1265
1266 /*
1267 * Timer definitions.
1268 */
1269 #define CNTKCTL_EL1_PL0PTEN (0x1 << 9) /* 1: EL0 access to physical timer regs permitted */
1270 #define CNTKCTL_EL1_PL0VTEN (0x1 << 8) /* 1: EL0 access to virtual timer regs permitted */
1271 #define CNTKCTL_EL1_EVENTI_MASK (0x000000f0) /* Mask for bits describing which bit to use for triggering event stream */
1272 #define CNTKCTL_EL1_EVENTI_SHIFT (0x4) /* Shift for same */
1273 #define CNTKCTL_EL1_EVENTDIR (0x1 << 3) /* 1: one-to-zero transition of specified bit causes event */
1274 #define CNTKCTL_EL1_EVNTEN (0x1 << 2) /* 1: enable event stream */
1275 #define CNTKCTL_EL1_PL0VCTEN (0x1 << 1) /* 1: EL0 access to physical timebase + frequency reg enabled */
1276 #define CNTKCTL_EL1_PL0PCTEN (0x1 << 0) /* 1: EL0 access to virtual timebase + frequency reg enabled */
1277
1278 #define CNTV_CTL_EL0_ISTATUS (0x1 << 2) /* (read only): whether interrupt asserted */
1279 #define CNTV_CTL_EL0_IMASKED (0x1 << 1) /* 1: interrupt masked */
1280 #define CNTV_CTL_EL0_ENABLE (0x1 << 0) /* 1: virtual timer enabled */
1281
1282 #define CNTP_CTL_EL0_ISTATUS CNTV_CTL_EL0_ISTATUS
1283 #define CNTP_CTL_EL0_IMASKED CNTV_CTL_EL0_IMASKED
1284 #define CNTP_CTL_EL0_ENABLE CNTV_CTL_EL0_ENABLE
1285
1286 /*
1287 * At present all other uses of ARM_DBG_* are shared bit compatibly with the 32bit definitons.
1288 * (cf. osfmk/arm/proc_reg.h)
1289 */
1290 #define ARM_DBG_VR_ADDRESS_MASK64 0xFFFFFFFFFFFFFFFCull /* BVR & WVR */
1291
1292 #define MIDR_EL1_REV_SHIFT 0
1293 #define MIDR_EL1_REV_MASK (0xf << MIDR_EL1_REV_SHIFT)
1294 #define MIDR_EL1_PNUM_SHIFT 4
1295 #define MIDR_EL1_PNUM_MASK (0xfff << MIDR_EL1_PNUM_SHIFT)
1296 #define MIDR_EL1_ARCH_SHIFT 16
1297 #define MIDR_EL1_ARCH_MASK (0xf << MIDR_EL1_ARCH_SHIFT)
1298 #define MIDR_EL1_VAR_SHIFT 20
1299 #define MIDR_EL1_VAR_MASK (0xf << MIDR_EL1_VAR_SHIFT)
1300 #define MIDR_EL1_IMP_SHIFT 24
1301 #define MIDR_EL1_IMP_MASK (0xff << MIDR_EL1_IMP_SHIFT)
1302
1303 /*
1304 * CoreSight debug registers
1305 */
1306 #define CORESIGHT_ED 0
1307 #define CORESIGHT_CTI 1
1308 #define CORESIGHT_PMU 2
1309 #define CORESIGHT_UTT 3 /* Not truly a coresight thing, but at a fixed convenient location right after the coresight region */
1310
1311 #define CORESIGHT_OFFSET(x) ((x) * 0x10000)
1312 #define CORESIGHT_REGIONS 4
1313 #define CORESIGHT_SIZE 0x1000
1314
1315
1316 /*
1317 * ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0
1318 *
1319 * 63 24 23 20 19 16 15 12 11 8 7 4 3 0
1320 * +----------+--------+------+------+------+-----+------+
1321 * | reserved | atomic |crc32 | sha2 | sha1 | aes | res0 |
1322 * +----------+--------+------+------+------+-----+------+
1323 */
1324
1325 #define ID_AA64ISAR0_EL1_ATOMIC_OFFSET 20
1326 #define ID_AA64ISAR0_EL1_ATOMIC_MASK (0xfull << ID_AA64ISAR0_EL1_ATOMIC_OFFSET)
1327 #define ID_AA64ISAR0_EL1_ATOMIC_8_1 (2ull << ID_AA64ISAR0_EL1_ATOMIC_OFFSET)
1328
1329 #define ID_AA64ISAR0_EL1_CRC32_OFFSET 16
1330 #define ID_AA64ISAR0_EL1_CRC32_MASK (0xfull << ID_AA64ISAR0_EL1_CRC32_OFFSET)
1331 #define ID_AA64ISAR0_EL1_CRC32_EN (1ull << ID_AA64ISAR0_EL1_CRC32_OFFSET)
1332
1333 #define ID_AA64ISAR0_EL1_SHA2_OFFSET 12
1334 #define ID_AA64ISAR0_EL1_SHA2_MASK (0xfull << ID_AA64ISAR0_EL1_SHA2_OFFSET)
1335 #define ID_AA64ISAR0_EL1_SHA2_EN (1ull << ID_AA64ISAR0_EL1_SHA2_OFFSET)
1336
1337 #define ID_AA64ISAR0_EL1_SHA1_OFFSET 8
1338 #define ID_AA64ISAR0_EL1_SHA1_MASK (0xfull << ID_AA64ISAR0_EL1_SHA1_OFFSET)
1339 #define ID_AA64ISAR0_EL1_SHA1_EN (1ull << ID_AA64ISAR0_EL1_SHA1_OFFSET)
1340
1341 #define ID_AA64ISAR0_EL1_AES_OFFSET 4
1342 #define ID_AA64ISAR0_EL1_AES_MASK (0xfull << ID_AA64ISAR0_EL1_AES_OFFSET)
1343 #define ID_AA64ISAR0_EL1_AES_EN (1ull << ID_AA64ISAR0_EL1_AES_OFFSET)
1344 #define ID_AA64ISAR0_EL1_AES_PMULL_EN (2ull << ID_AA64ISAR0_EL1_AES_OFFSET)
1345
1346
1347
1348 #ifdef __ASSEMBLER__
1349
1350 /*
1351 * Compute CPU version:
1352 * Version is constructed as [4 bits of MIDR variant]:[4 bits of MIDR revision]
1353 *
1354 * Where the "variant" is the major number and the "revision" is the minor number.
1355 *
1356 * For example:
1357 * Cyclone A0 is variant 0, revision 0, i.e. 0.
1358 * Cyclone B0 is variant 1, revision 0, i.e. 0x10
1359 * $0 - register to place value in
1360 */
1361 .macro GET_MIDR_CPU_VERSION
1362 mrs $0, MIDR_EL1 // Read MIDR_EL1 for CPUID
1363 bfi $0, $0, #(MIDR_EL1_VAR_SHIFT - 4), #4 // move bits 3:0 (revision) to 19:16 (below variant) to get values adjacent
1364 ubfx $0, $0, #(MIDR_EL1_VAR_SHIFT - 4), #8 // And extract the concatenated bitstring to beginning of register
1365 .endmacro
1366
1367 /*
1368 * To apply a workaround for CPU versions less than a given value
1369 * (e.g. earlier than when a fix arrived)
1370 *
1371 * $0 - scratch register1
1372 * $1 - version at which to stop applying workaround
1373 * $2 - label to branch to (at end of workaround)
1374 */
1375 .macro SKIP_IF_CPU_VERSION_GREATER_OR_EQUAL
1376 GET_MIDR_CPU_VERSION $0
1377 cmp $0, $1
1378 b.pl $2 // Unsigned "greater or equal"
1379 .endmacro
1380
1381 /*
1382 * To apply a workaround for CPU versions greater than a given value
1383 * (e.g. starting when a bug was introduced)
1384 *
1385 * $0 - scratch register1
1386 * $1 - version at which to stop applying workaround
1387 * $2 - label to branch to (at end of workaround)
1388 */
1389 .macro SKIP_IF_CPU_VERSION_LESS_THAN
1390 GET_MIDR_CPU_VERSION $0
1391 cmp $0, $1
1392 b.mi $2 // Unsigned "strictly less than"
1393 .endmacro
1394
1395 #endif /* __ASSEMBLER__ */
1396
1397 #define MSR(reg,src) __asm__ volatile ("msr " reg ", %0" :: "r" (src))
1398 #define MRS(dest,reg) __asm__ volatile ("mrs %0, " reg : "=r" (dest))
1399
1400
1401 #endif /* _ARM64_PROC_REG_H_ */
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