osfmk/i386/AT386/rtc.h

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * Copyright (c) 1999-2003 Apple Computer, Inc.  All Rights Reserved.
   7  *
   8  * This file contains Original Code and/or Modifications of Original Code
   9  * as defined in and that are subject to the Apple Public Source License
  10  * Version 2.0 (the 'License'). You may not use this file except in
  11  * compliance with the License. Please obtain a copy of the License at
  12  * http://www.opensource.apple.com/apsl/ and read it before using this
  13  * file.
  14  *
  15  * The Original Code and all software distributed under the License are
  16  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  17  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  18  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  20  * Please see the License for the specific language governing rights and
  21  * limitations under the License.
  22  *
  23  * @APPLE_LICENSE_HEADER_END@
  24  */
  25 /*
  26  * @OSF_COPYRIGHT@
  27  */
  28 /*
  29  * HISTORY
  30  *
  31  * Revision 1.1.1.1  1998/09/22 21:05:39  wsanchez
  32  * Import of Mac OS X kernel (~semeria)
  33  *
  34  * Revision 1.1.1.1  1998/03/07 02:25:40  wsanchez
  35  * Import of OSF Mach kernel (~mburg)
  36  *
  37  * Revision 1.1.6.1  1994/09/23  01:47:30  ezf
  38  *      change marker to not FREE
  39  *      [1994/09/22  21:20:22  ezf]
  40  *
  41  * Revision 1.1.2.3  1993/08/09  19:39:04  dswartz
  42  *      Add ANSI prototypes - CR#9523
  43  *      [1993/08/06  17:51:17  dswartz]
  44  *
  45  * Revision 1.1.2.2  1993/06/02  23:21:32  jeffc
  46  *      Added to OSF/1 R1.3 from NMK15.0.
  47  *      [1993/06/02  21:03:17  jeffc]
  48  *
  49  * Revision 1.1  1992/09/30  02:27:20  robert
  50  *      Initial revision
  51  *
  52  * $EndLog$
  53  */
  54 /* CMU_HIST */
  55 /*
  56  * Revision 2.7  91/05/14  16:30:03  mrt
  57  *      Correcting copyright
  58  *
  59  * Revision 2.6  91/03/16  14:47:03  rpd
  60  *      Fixed ioctl definitions for ANSI C.
  61  *      [91/02/20            rpd]
  62  *
  63  * Revision 2.5  91/02/05  17:20:25  mrt
  64  *      Changed to new Mach copyright
  65  *      [91/02/01  17:47:16  mrt]
  66  *
  67  * Revision 2.4  90/11/26  14:51:02  rvb
  68  *      jsb bet me to XMK34, sigh ...
  69  *      [90/11/26            rvb]
  70  *      Synched 2.5 & 3.0 at I386q (r1.5.1.3) & XMK35 (r2.4)
  71  *      [90/11/15            rvb]
  72  *
  73  * Revision 1.5.1.2  90/07/27  11:27:06  rvb
  74  *      Fix Intel Copyright as per B. Davies authorization.
  75  *      [90/07/27            rvb]
  76  *
  77  * Revision 2.2  90/05/03  15:46:11  dbg
  78  *      First checkin.
  79  *
  80  * Revision 1.5.1.1  90/01/08  13:29:46  rvb
  81  *      Add Intel copyright.
  82  *      [90/01/08            rvb]
  83  *
  84  * Revision 1.5  89/09/25  12:27:37  rvb
  85  *      File was provided by Intel 9/18/89.
  86  *      [89/09/23            rvb]
  87  *
  88  */
  89 /* CMU_ENDHIST */
  90 /*
  91  * Mach Operating System
  92  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
  93  * All Rights Reserved.
  94  *
  95  * Permission to use, copy, modify and distribute this software and its
  96  * documentation is hereby granted, provided that both the copyright
  97  * notice and this permission notice appear in all copies of the
  98  * software, derivative works or modified versions, and any portions
  99  * thereof, and that both notices appear in supporting documentation.
 100  *
 101  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 102  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
 103  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 104  *
 105  * Carnegie Mellon requests users of this software to return to
 106  *
 107  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 108  *  School of Computer Science
 109  *  Carnegie Mellon University
 110  *  Pittsburgh PA 15213-3890
 111  *
 112  * any improvements or extensions that they make and grant Carnegie Mellon
 113  * the rights to redistribute these changes.
 114  */
 115 /*
 116  */
 117
 118 /*
 119  *   Copyright 1988, 1989 by Intel Corporation, Santa Clara, California.
 120  *
 121  *              All Rights Reserved
 122  *
 123  * Permission to use, copy, modify, and distribute this software and
 124  * its documentation for any purpose and without fee is hereby
 125  * granted, provided that the above copyright notice appears in all
 126  * copies and that both the copyright notice and this permission notice
 127  * appear in supporting documentation, and that the name of Intel
 128  * not be used in advertising or publicity pertaining to distribution
 129  * of the software without specific, written prior permission.
 130  *
 131  * INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
 132  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
 133  * IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
 134  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
 135  * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
 136  * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
 137  * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 138  */
 139
 140 #define RTC_ADDR        0x70    /* I/O port address for register select */
 141 #define RTC_DATA        0x71    /* I/O port address for data read/write */
 142
 143 /*
 144  * Register A definitions
 145  */
 146 #define RTC_A           0x0a    /* register A address */
 147 #define RTC_UIP         0x80    /* Update in progress bit */
 148 #define RTC_DIV0        0x00    /* Time base of 4.194304 MHz */
 149 #define RTC_DIV1        0x10    /* Time base of 1.048576 MHz */
 150 #define RTC_DIV2        0x20    /* Time base of 32.768 KHz */
 151 #define RTC_RATE6       0x06    /* interrupt rate of 976.562 */
 152
 153 /*
 154  * Register B definitions
 155  */
 156 #define RTC_B           0x0b    /* register B address */
 157 #define RTC_SET         0x80    /* stop updates for time set */
 158 #define RTC_PIE         0x40    /* Periodic interrupt enable */
 159 #define RTC_AIE         0x20    /* Alarm interrupt enable */
 160 #define RTC_UIE         0x10    /* Update ended interrupt enable */
 161 #define RTC_SQWE        0x08    /* Square wave enable */
 162 #define RTC_DM          0x04    /* Date mode, 1 = binary, 0 = BCD */
 163 #define RTC_HM          0x02    /* hour mode, 1 = 24 hour, 0 = 12 hour */
 164 #define RTC_DSE         0x01    /* Daylight savings enable */
 165
 166 /*
 167  * Register C definitions
 168  */
 169 #define RTC_C           0x0c    /* register C address */
 170 #define RTC_IRQF        0x80    /* IRQ flag */
 171 #define RTC_PF          0x40    /* PF flag bit */
 172 #define RTC_AF          0x20    /* AF flag bit */
 173 #define RTC_UF          0x10    /* UF flag bit */
 174
 175 /*
 176  * Register D definitions
 177  */
 178 #define RTC_D           0x0d    /* register D address */
 179 #define RTC_VRT         0x80    /* Valid RAM and time bit */
 180
 181 #define RTC_NREG        0x0e    /* number of RTC registers */
 182 #define RTC_NREGP       0x0a    /* number of RTC registers to set time */
 183
 184 #define RTCRTIME        _IOR('c', 0x01, struct rtc_st) /* Read time from RTC */
 185 #define RTCSTIME        _IOW('c', 0x02, struct rtc_st) /* Set time into RTC */
 186
 187 struct rtc_st {
 188         char    rtc_sec;
 189         char    rtc_asec;
 190         char    rtc_min;
 191         char    rtc_amin;
 192         char    rtc_hr;
 193         char    rtc_ahr;
 194         char    rtc_dow;
 195         char    rtc_dom;
 196         char    rtc_mon;
 197         char    rtc_yr;
 198         char    rtc_statusa;
 199         char    rtc_statusb;
 200         char    rtc_statusc;
 201         char    rtc_statusd;
 202 };
 203
 204 /*
 205  * this macro reads contents of real time clock to specified buffer
 206  */
 207 #define load_rtc(regs) \
 208 {\
 209         register int i; \
 210         \
 211         for (i = 0; i < RTC_NREG; i++) { \
 212                 outb(RTC_ADDR, i); \
 213                 (regs)[i] = inb(RTC_DATA); \
 214         } \
 215 }
 216
 217 /*
 218  * this macro writes contents of specified buffer to real time clock
 219  */
 220 #define save_rtc(regs) \
 221 { \
 222         register int i; \
 223         for (i = 0; i < RTC_NREGP; i++) { \
 224                 outb(RTC_ADDR, i); \
 225                 outb(RTC_DATA, (regs)[i]);\
 226         } \
 227 }
 228
 229