osfmk/i386/proc_reg.h

   1 /*
   2  * Copyright (c) 2000-2012 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 /*
  29  * @OSF_COPYRIGHT@
  30  */
  31 /* CMU_ENDHIST */
  32 /*
  33  * Mach Operating System
  34  * Copyright (c) 1991,1990 Carnegie Mellon University
  35  * All Rights Reserved.
  36  *
  37  * Permission to use, copy, modify and distribute this software and its
  38  * documentation is hereby granted, provided that both the copyright
  39  * notice and this permission notice appear in all copies of the
  40  * software, derivative works or modified versions, and any portions
  41  * thereof, and that both notices appear in supporting documentation.
  42  *
  43  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  44  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
  45  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  46  *
  47  * Carnegie Mellon requests users of this software to return to
  48  *
  49  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  50  *  School of Computer Science
  51  *  Carnegie Mellon University
  52  *  Pittsburgh PA 15213-3890
  53  *
  54  * any improvements or extensions that they make and grant Carnegie Mellon
  55  * the rights to redistribute these changes.
  56  */
  57
  58 /*
  59  */
  60
  61 /*
  62  * Processor registers for i386 and i486.
  63  */
  64 #ifndef _I386_PROC_REG_H_
  65 #define _I386_PROC_REG_H_
  66
  67 /*
  68  * Model Specific Registers
  69  */
  70 #define MSR_P5_TSC              0x10    /* Time Stamp Register */
  71 #define MSR_P5_CESR             0x11    /* Control and Event Select Register */
  72 #define MSR_P5_CTR0             0x12    /* Counter #0 */
  73 #define MSR_P5_CTR1             0x13    /* Counter #1 */
  74
  75 #define MSR_P5_CESR_PC          0x0200  /* Pin Control */
  76 #define MSR_P5_CESR_CC          0x01C0  /* Counter Control mask */
  77 #define MSR_P5_CESR_ES          0x003F  /* Event Control mask */
  78
  79 #define MSR_P5_CESR_SHIFT       16              /* Shift to get Counter 1 */
  80 #define MSR_P5_CESR_MASK        (MSR_P5_CESR_PC|\
  81                                  MSR_P5_CESR_CC|\
  82                                  MSR_P5_CESR_ES) /* Mask Counter */
  83
  84 #define MSR_P5_CESR_CC_CLOCK    0x0100  /* Clock Counting (otherwise Event) */
  85 #define MSR_P5_CESR_CC_DISABLE  0x0000  /* Disable counter */
  86 #define MSR_P5_CESR_CC_CPL012   0x0040  /* Count if the CPL == 0, 1, 2 */
  87 #define MSR_P5_CESR_CC_CPL3     0x0080  /* Count if the CPL == 3 */
  88 #define MSR_P5_CESR_CC_CPL      0x00C0  /* Count regardless of the CPL */
  89
  90 #define MSR_P5_CESR_ES_DATA_READ       0x000000 /* Data Read */
  91 #define MSR_P5_CESR_ES_DATA_WRITE      0x000001 /* Data Write */
  92 #define MSR_P5_CESR_ES_DATA_RW         0x101000 /* Data Read or Write */
  93 #define MSR_P5_CESR_ES_DATA_TLB_MISS   0x000010 /* Data TLB Miss */
  94 #define MSR_P5_CESR_ES_DATA_READ_MISS  0x000011 /* Data Read Miss */
  95 #define MSR_P5_CESR_ES_DATA_WRITE_MISS 0x000100 /* Data Write Miss */
  96 #define MSR_P5_CESR_ES_DATA_RW_MISS    0x101001 /* Data Read or Write Miss */
  97 #define MSR_P5_CESR_ES_HIT_EM          0x000101 /* Write (hit) to M|E state */
  98 #define MSR_P5_CESR_ES_DATA_CACHE_WB   0x000110 /* Cache lines written back */
  99 #define MSR_P5_CESR_ES_EXTERNAL_SNOOP  0x000111 /* External Snoop */
 100 #define MSR_P5_CESR_ES_CACHE_SNOOP_HIT 0x001000 /* Data cache snoop hits */
 101 #define MSR_P5_CESR_ES_MEM_ACCESS_PIPE 0x001001 /* Mem. access in both pipes */
 102 #define MSR_P5_CESR_ES_BANK_CONFLICTS  0x001010 /* Bank conflicts */
 103 #define MSR_P5_CESR_ES_MISALIGNED      0x001011 /* Misaligned Memory or I/O */
 104 #define MSR_P5_CESR_ES_CODE_READ       0x001100 /* Code Read */
 105 #define MSR_P5_CESR_ES_CODE_TLB_MISS   0x001101 /* Code TLB miss */
 106 #define MSR_P5_CESR_ES_CODE_CACHE_MISS 0x001110 /* Code Cache miss */
 107 #define MSR_P5_CESR_ES_SEGMENT_LOADED  0x001111 /* Any segment reg. loaded */
 108 #define MSR_P5_CESR_ES_BRANCHE         0x010010 /* Branches */
 109 #define MSR_P5_CESR_ES_BTB_HIT         0x010011 /* BTB Hits */
 110 #define MSR_P5_CESR_ES_BRANCHE_BTB     0x010100 /* Taken branch or BTB Hit */
 111 #define MSR_P5_CESR_ES_PIPELINE_FLUSH  0x010101 /* Pipeline Flushes */
 112 #define MSR_P5_CESR_ES_INSTRUCTION     0x010110 /* Instruction executed */
 113 #define MSR_P5_CESR_ES_INSTRUCTION_V   0x010111 /* Inst. executed (v-pipe) */
 114 #define MSR_P5_CESR_ES_BUS_CYCLE       0x011000 /* Clocks while bus cycle */
 115 #define MSR_P5_CESR_ES_FULL_WRITE_BUF  0x011001 /* Clocks while full wrt buf. */
 116 #define MSR_P5_CESR_ES_DATA_MEM_READ   0x011010 /* Pipeline waiting for read */
 117 #define MSR_P5_CESR_ES_WRITE_EM        0x011011 /* Stall on write E|M state */
 118 #define MSR_P5_CESR_ES_LOCKED_CYCLE    0x011100 /* Locked bus cycles */
 119 #define MSR_P5_CESR_ES_IO_CYCLE        0x011101 /* I/O Read or Write cycles */
 120 #define MSR_P5_CESR_ES_NON_CACHEABLE   0x011110 /* Non-cacheable Mem. read */
 121 #define MSR_P5_CESR_ES_AGI             0x011111 /* Stall because of AGI */
 122 #define MSR_P5_CESR_ES_FLOP            0x100010 /* Floating Point operations */
 123 #define MSR_P5_CESR_ES_BREAK_DR0       0x100011 /* Breakpoint matches on DR0 */
 124 #define MSR_P5_CESR_ES_BREAK_DR1       0x100100 /* Breakpoint matches on DR1 */
 125 #define MSR_P5_CESR_ES_BREAK_DR2       0x100101 /* Breakpoint matches on DR2 */
 126 #define MSR_P5_CESR_ES_BREAK_DR3       0x100110 /* Breakpoint matches on DR3 */
 127 #define MSR_P5_CESR_ES_HARDWARE_IT     0x100111 /* Hardware interrupts */
 128
 129 /*
 130  * CR0
 131  */
 132 #define CR0_PG  0x80000000      /*       Enable paging */
 133 #define CR0_CD  0x40000000      /* i486: Cache disable */
 134 #define CR0_NW  0x20000000      /* i486: No write-through */
 135 #define CR0_AM  0x00040000      /* i486: Alignment check mask */
 136 #define CR0_WP  0x00010000      /* i486: Write-protect kernel access */
 137 #define CR0_NE  0x00000020      /* i486: Handle numeric exceptions */
 138 #define CR0_ET  0x00000010      /*       Extension type is 80387 */
 139                                 /*       (not official) */
 140 #define CR0_TS  0x00000008      /*       Task switch */
 141 #define CR0_EM  0x00000004      /*       Emulate coprocessor */
 142 #define CR0_MP  0x00000002      /*       Monitor coprocessor */
 143 #define CR0_PE  0x00000001      /*       Enable protected mode */
 144
 145 /*
 146  * CR4
 147  */
 148 #define CR4_SEE         0x00008000      /* Secure Enclave Enable XXX */
 149 #define CR4_SMAP        0x00200000      /* Supervisor-Mode Access Protect */
 150 #define CR4_SMEP        0x00100000      /* Supervisor-Mode Execute Protect */
 151 #define CR4_OSXSAVE     0x00040000      /* OS supports XSAVE */
 152 #define CR4_PCIDE       0x00020000      /* PCID Enable */
 153 #define CR4_RDWRFSGS    0x00010000      /* RDWRFSGS Enable */
 154 #define CR4_SMXE        0x00004000      /* Enable SMX operation */
 155 #define CR4_VMXE        0x00002000      /* Enable VMX operation */
 156 #define CR4_OSXMM       0x00000400      /* SSE/SSE2 exception support in OS */
 157 #define CR4_OSFXS       0x00000200      /* SSE/SSE2 OS supports FXSave */
 158 #define CR4_PCE         0x00000100      /* Performance-Monitor Count Enable */
 159 #define CR4_PGE         0x00000080      /* Page Global Enable */
 160 #define CR4_MCE         0x00000040      /* Machine Check Exceptions */
 161 #define CR4_PAE         0x00000020      /* Physical Address Extensions */
 162 #define CR4_PSE         0x00000010      /* Page Size Extensions */
 163 #define CR4_DE          0x00000008      /* Debugging Extensions */
 164 #define CR4_TSD         0x00000004      /* Time Stamp Disable */
 165 #define CR4_PVI         0x00000002      /* Protected-mode Virtual Interrupts */
 166 #define CR4_VME         0x00000001      /* Virtual-8086 Mode Extensions */
 167
 168 /*
 169  * XCR0 - XFEATURE_ENABLED_MASK (a.k.a. XFEM) register
 170  */
 171 #define XCR0_X87        (1ULL << 0)     /* x87, FPU/MMX (always set) */
 172 #define XCR0_SSE        (1ULL << 1)     /* SSE supported by XSAVE/XRESTORE */
 173 #define XCR0_YMM        (1ULL << 2)     /* YMM state available */
 174 #define XCR0_BNDREGS    (1ULL << 3)     /* MPX Bounds register state */
 175 #define XCR0_BNDCSR     (1ULL << 4)     /* MPX Bounds configuration/state  */
 176 #define XFEM_X87        XCR0_X87
 177 #define XFEM_SSE        XCR0_SSE
 178 #define XFEM_YMM        XCR0_YMM
 179 #define XFEM_BNDREGS    XCR0_BNDREGS
 180 #define XFEM_BNDCSR     XCR0_BNDCSR
 181 #define XCR0 (0)
 182
 183 #define PMAP_PCID_PRESERVE (1ULL << 63)
 184 #define PMAP_PCID_MASK (0xFFF)
 185
 186 #ifndef ASSEMBLER
 187
 188 #include <sys/cdefs.h>
 189 #include <stdint.h>
 190
 191 __BEGIN_DECLS
 192
 193 #define set_ts() set_cr0(get_cr0() | CR0_TS)
 194
 195 static inline uint16_t get_es(void)
 196 {
 197         uint16_t es;
 198         __asm__ volatile("mov %%es, %0" : "=r" (es));
 199         return es;
 200 }
 201
 202 static inline void set_es(uint16_t es)
 203 {
 204         __asm__ volatile("mov %0, %%es" : : "r" (es));
 205 }
 206
 207 static inline uint16_t get_ds(void)
 208 {
 209         uint16_t ds;
 210         __asm__ volatile("mov %%ds, %0" : "=r" (ds));
 211         return ds;
 212 }
 213
 214 static inline void set_ds(uint16_t ds)
 215 {
 216         __asm__ volatile("mov %0, %%ds" : : "r" (ds));
 217 }
 218
 219 static inline uint16_t get_fs(void)
 220 {
 221         uint16_t fs;
 222         __asm__ volatile("mov %%fs, %0" : "=r" (fs));
 223         return fs;
 224 }
 225
 226 static inline void set_fs(uint16_t fs)
 227 {
 228         __asm__ volatile("mov %0, %%fs" : : "r" (fs));
 229 }
 230
 231 static inline uint16_t get_gs(void)
 232 {
 233         uint16_t gs;
 234         __asm__ volatile("mov %%gs, %0" : "=r" (gs));
 235         return gs;
 236 }
 237
 238 static inline void set_gs(uint16_t gs)
 239 {
 240         __asm__ volatile("mov %0, %%gs" : : "r" (gs));
 241 }
 242
 243 static inline uint16_t get_ss(void)
 244 {
 245         uint16_t ss;
 246         __asm__ volatile("mov %%ss, %0" : "=r" (ss));
 247         return ss;
 248 }
 249
 250 static inline void set_ss(uint16_t ss)
 251 {
 252         __asm__ volatile("mov %0, %%ss" : : "r" (ss));
 253 }
 254
 255 static inline uintptr_t get_cr0(void)
 256 {
 257         uintptr_t cr0;
 258         __asm__ volatile("mov %%cr0, %0" : "=r" (cr0));
 259         return(cr0);
 260 }
 261
 262 static inline void set_cr0(uintptr_t value)
 263 {
 264         __asm__ volatile("mov %0, %%cr0" : : "r" (value));
 265 }
 266
 267 static inline uintptr_t get_cr2(void)
 268 {
 269         uintptr_t cr2;
 270         __asm__ volatile("mov %%cr2, %0" : "=r" (cr2));
 271         return(cr2);
 272 }
 273
 274 static inline uintptr_t get_cr3_raw(void)
 275 {
 276         uintptr_t cr3;
 277         __asm__ volatile("mov %%cr3, %0" : "=r" (cr3));
 278         return(cr3);
 279 }
 280
 281 static inline void set_cr3_raw(uintptr_t value)
 282 {
 283         __asm__ volatile("mov %0, %%cr3" : : "r" (value));
 284 }
 285
 286 static inline uintptr_t get_cr3_base(void)
 287 {
 288         uintptr_t cr3;
 289         __asm__ volatile("mov %%cr3, %0" : "=r" (cr3));
 290         return(cr3 & ~(0xFFFULL));
 291 }
 292
 293 static inline void set_cr3_composed(uintptr_t base, uint16_t pcid, uint32_t preserve)
 294 {
 295         __asm__ volatile("mov %0, %%cr3" : : "r" (base | pcid | ( ( (uint64_t)preserve) << 63) ) );
 296 }
 297
 298 static inline uintptr_t get_cr4(void)
 299 {
 300         uintptr_t cr4;
 301         __asm__ volatile("mov %%cr4, %0" : "=r" (cr4));
 302         return(cr4);
 303 }
 304
 305 static inline void set_cr4(uintptr_t value)
 306 {
 307         __asm__ volatile("mov %0, %%cr4" : : "r" (value));
 308 }
 309
 310 static inline uintptr_t x86_get_flags(void)
 311 {
 312         uintptr_t erflags;
 313         __asm__ volatile("pushf; pop    %0" :  "=r" (erflags));
 314         return erflags;
 315 }
 316
 317 static inline void clear_ts(void)
 318 {
 319         __asm__ volatile("clts");
 320 }
 321
 322 static inline unsigned short get_tr(void)
 323 {
 324         unsigned short seg;
 325         __asm__ volatile("str %0" : "=rm" (seg));
 326         return(seg);
 327 }
 328
 329 static inline void set_tr(unsigned int seg)
 330 {
 331         __asm__ volatile("ltr %0" : : "rm" ((unsigned short)(seg)));
 332 }
 333
 334 static inline unsigned short sldt(void)
 335 {
 336         unsigned short seg;
 337         __asm__ volatile("sldt %0" : "=rm" (seg));
 338         return(seg);
 339 }
 340
 341 static inline void lldt(unsigned int seg)
 342 {
 343         __asm__ volatile("lldt %0" : : "rm" ((unsigned short)(seg)));
 344 }
 345
 346 static inline void lgdt(uintptr_t *desc)
 347 {
 348         __asm__ volatile("lgdt %0" : : "m" (*desc));
 349 }
 350
 351 static inline void lidt(uintptr_t *desc)
 352 {
 353         __asm__ volatile("lidt %0" : : "m" (*desc));
 354 }
 355
 356 static inline void swapgs(void)
 357 {
 358         __asm__ volatile("swapgs");
 359 }
 360
 361 #ifdef MACH_KERNEL_PRIVATE
 362
 363 static inline void flush_tlb_raw(void)
 364 {
 365         set_cr3_raw(get_cr3_raw());
 366 }
 367 extern int rdmsr64_carefully(uint32_t msr, uint64_t *val);
 368 extern int wrmsr64_carefully(uint32_t msr, uint64_t val);
 369 #endif  /* MACH_KERNEL_PRIVATE */
 370
 371 static inline void wbinvd(void)
 372 {
 373         __asm__ volatile("wbinvd");
 374 }
 375
 376 static inline void invlpg(uintptr_t addr)
 377 {
 378         __asm__  volatile("invlpg (%0)" :: "r" (addr) : "memory");
 379 }
 380
 381 static inline void clac(void)
 382 {
 383         __asm__  volatile("clac");
 384 }
 385
 386 static inline void stac(void)
 387 {
 388         __asm__  volatile("stac");
 389 }
 390
 391 /*
 392  * Access to machine-specific registers (available on 586 and better only)
 393  * Note: the rd* operations modify the parameters directly (without using
 394  * pointer indirection), this allows gcc to optimize better
 395  */
 396
 397 #define rdmsr(msr,lo,hi) \
 398         __asm__ volatile("rdmsr" : "=a" (lo), "=d" (hi) : "c" (msr))
 399
 400 #define wrmsr(msr,lo,hi) \
 401         __asm__ volatile("wrmsr" : : "c" (msr), "a" (lo), "d" (hi))
 402
 403 #define rdtsc(lo,hi) \
 404         __asm__ volatile("lfence; rdtsc; lfence" : "=a" (lo), "=d" (hi))
 405
 406 #define rdtsc_nofence(lo,hi) \
 407         __asm__ volatile("rdtsc" : "=a" (lo), "=d" (hi))
 408
 409 #define write_tsc(lo,hi) wrmsr(0x10, lo, hi)
 410
 411 #define rdpmc(counter,lo,hi) \
 412         __asm__ volatile("rdpmc" : "=a" (lo), "=d" (hi) : "c" (counter))
 413
 414 #ifdef XNU_KERNEL_PRIVATE
 415 extern void do_mfence(void);
 416 #define mfence() do_mfence()
 417 #endif
 418
 419 static inline uint64_t rdpmc64(uint32_t pmc)
 420 {
 421         uint32_t lo=0, hi=0;
 422         rdpmc(pmc, lo, hi);
 423         return (((uint64_t)hi) << 32) | ((uint64_t)lo);
 424 }
 425
 426 static inline uint64_t rdmsr64(uint32_t msr)
 427 {
 428         uint32_t lo=0, hi=0;
 429         rdmsr(msr, lo, hi);
 430         return (((uint64_t)hi) << 32) | ((uint64_t)lo);
 431 }
 432
 433 static inline void wrmsr64(uint32_t msr, uint64_t val)
 434 {
 435         wrmsr(msr, (val & 0xFFFFFFFFUL), ((val >> 32) & 0xFFFFFFFFUL));
 436 }
 437
 438 static inline uint64_t rdtsc64(void)
 439 {
 440         uint64_t lo, hi;
 441         rdtsc(lo, hi);
 442         return ((hi) << 32) | (lo);
 443 }
 444
 445 static inline uint64_t rdtscp64(uint32_t *aux)
 446 {
 447         uint64_t lo, hi;
 448         __asm__ volatile("rdtscp; mov %%ecx, %1"
 449                                          : "=a" (lo), "=d" (hi), "=m" (*aux)
 450                                          :
 451                                          : "ecx");
 452         return ((hi) << 32) | (lo);
 453 }
 454
 455
 456 /*
 457  * rdmsr_carefully() returns 0 when the MSR has been read successfully,
 458  * or non-zero (1) if the MSR does not exist.
 459  * The implementation is in locore.s.
 460  */
 461 extern int rdmsr_carefully(uint32_t msr, uint32_t *lo, uint32_t *hi);
 462 __END_DECLS
 463
 464 #endif  /* ASSEMBLER */
 465
 466 #define MSR_IA32_P5_MC_ADDR                     0
 467 #define MSR_IA32_P5_MC_TYPE                     1
 468 #define MSR_IA32_PLATFORM_ID                    0x17
 469 #define MSR_IA32_EBL_CR_POWERON                 0x2a
 470
 471 #define MSR_IA32_APIC_BASE                      0x1b
 472 #define     MSR_IA32_APIC_BASE_BSP                  (1<<8)
 473 #define     MSR_IA32_APIC_BASE_EXTENDED             (1<<10)
 474 #define     MSR_IA32_APIC_BASE_ENABLE               (1<<11)
 475 #define     MSR_IA32_APIC_BASE_BASE                 (0xfffff<<12)
 476
 477 #define MSR_CORE_THREAD_COUNT                   0x35
 478
 479 #define MSR_IA32_FEATURE_CONTROL                0x3a
 480 #define     MSR_IA32_FEATCTL_LOCK                   (1<<0)
 481 #define     MSR_IA32_FEATCTL_VMXON_SMX              (1<<1)
 482 #define     MSR_IA32_FEATCTL_VMXON                  (1<<2)
 483 #define     MSR_IA32_FEATCTL_CSTATE_SMI             (1<<16)
 484
 485 #define MSR_IA32_UPDT_TRIG                      0x79
 486 #define MSR_IA32_BIOS_SIGN_ID                   0x8b
 487 #define MSR_IA32_UCODE_WRITE                    MSR_IA32_UPDT_TRIG
 488 #define MSR_IA32_UCODE_REV                      MSR_IA32_BIOS_SIGN_ID
 489
 490 #define MSR_IA32_PERFCTR0                       0xc1
 491 #define MSR_IA32_PERFCTR1                       0xc2
 492 #define MSR_IA32_PERFCTR3                       0xc3
 493 #define MSR_IA32_PERFCTR4                       0xc4
 494
 495 #define MSR_PLATFORM_INFO                       0xce
 496
 497 #define MSR_IA32_MPERF                          0xE7
 498 #define MSR_IA32_APERF                          0xE8
 499
 500 #define MSR_IA32_BBL_CR_CTL                     0x119
 501
 502 #define MSR_IA32_SYSENTER_CS                    0x174
 503 #define MSR_IA32_SYSENTER_ESP                   0x175
 504 #define MSR_IA32_SYSENTER_EIP                   0x176
 505
 506 #define MSR_IA32_MCG_CAP                        0x179
 507 #define MSR_IA32_MCG_STATUS                     0x17a
 508 #define MSR_IA32_MCG_CTL                        0x17b
 509
 510 #define MSR_IA32_EVNTSEL0                       0x186
 511 #define MSR_IA32_EVNTSEL1                       0x187
 512 #define MSR_IA32_EVNTSEL2                       0x188
 513 #define MSR_IA32_EVNTSEL3                       0x189
 514
 515 #define MSR_FLEX_RATIO                          0x194
 516 #define MSR_IA32_PERF_STS                       0x198
 517 #define MSR_IA32_PERF_CTL                       0x199
 518 #define MSR_IA32_CLOCK_MODULATION               0x19a
 519
 520 #define MSR_IA32_MISC_ENABLE                    0x1a0
 521
 522
 523 #define MSR_IA32_PACKAGE_THERM_STATUS           0x1b1
 524 #define MSR_IA32_PACKAGE_THERM_INTERRUPT        0x1b2
 525
 526 #define MSR_IA32_DEBUGCTLMSR                    0x1d9
 527 #define MSR_IA32_LASTBRANCHFROMIP               0x1db
 528 #define MSR_IA32_LASTBRANCHTOIP                 0x1dc
 529 #define MSR_IA32_LASTINTFROMIP                  0x1dd
 530 #define MSR_IA32_LASTINTTOIP                    0x1de
 531
 532 #define MSR_IA32_CR_PAT                         0x277
 533
 534 #define MSR_IA32_MTRRCAP                        0xfe
 535 #define MSR_IA32_MTRR_DEF_TYPE                  0x2ff
 536 #define MSR_IA32_MTRR_PHYSBASE(n)               (0x200 + 2*(n))
 537 #define MSR_IA32_MTRR_PHYSMASK(n)               (0x200 + 2*(n) + 1)
 538 #define MSR_IA32_MTRR_FIX64K_00000              0x250
 539 #define MSR_IA32_MTRR_FIX16K_80000              0x258
 540 #define MSR_IA32_MTRR_FIX16K_A0000              0x259
 541 #define MSR_IA32_MTRR_FIX4K_C0000               0x268
 542 #define MSR_IA32_MTRR_FIX4K_C8000               0x269
 543 #define MSR_IA32_MTRR_FIX4K_D0000               0x26a
 544 #define MSR_IA32_MTRR_FIX4K_D8000               0x26b
 545 #define MSR_IA32_MTRR_FIX4K_E0000               0x26c
 546 #define MSR_IA32_MTRR_FIX4K_E8000               0x26d
 547 #define MSR_IA32_MTRR_FIX4K_F0000               0x26e
 548 #define MSR_IA32_MTRR_FIX4K_F8000               0x26f
 549
 550 #define MSR_IA32_PERF_FIXED_CTR0                0x309
 551
 552 #define MSR_IA32_PERF_FIXED_CTR_CTRL            0x38D
 553 #define MSR_IA32_PERF_GLOBAL_STATUS             0x38E
 554 #define MSR_IA32_PERF_GLOBAL_CTRL               0x38F
 555 #define MSR_IA32_PERF_GLOBAL_OVF_CTRL   0x390
 556
 557 #define MSR_IA32_PKG_C3_RESIDENCY               0x3F8
 558 #define MSR_IA32_PKG_C6_RESIDENCY               0x3F9
 559 #define MSR_IA32_PKG_C7_RESIDENCY               0x3FA
 560
 561 #define MSR_IA32_CORE_C3_RESIDENCY              0x3FC
 562 #define MSR_IA32_CORE_C6_RESIDENCY              0x3FD
 563 #define MSR_IA32_CORE_C7_RESIDENCY              0x3FE
 564
 565 #define MSR_IA32_MC0_CTL                        0x400
 566 #define MSR_IA32_MC0_STATUS                     0x401
 567 #define MSR_IA32_MC0_ADDR                       0x402
 568 #define MSR_IA32_MC0_MISC                       0x403
 569
 570 #define MSR_IA32_VMX_BASE                                       0x480
 571 #define MSR_IA32_VMX_BASIC                                      MSR_IA32_VMX_BASE
 572 #define MSR_IA32_VMX_PINBASED_CTLS                      MSR_IA32_VMX_BASE+1
 573 #define MSR_IA32_VMX_PROCBASED_CTLS                     MSR_IA32_VMX_BASE+2
 574 #define MSR_IA32_VMX_EXIT_CTLS                          MSR_IA32_VMX_BASE+3
 575 #define MSR_IA32_VMX_ENTRY_CTLS                         MSR_IA32_VMX_BASE+4
 576 #define MSR_IA32_VMX_MISC                                       MSR_IA32_VMX_BASE+5
 577 #define MSR_IA32_VMX_CR0_FIXED0                         MSR_IA32_VMX_BASE+6
 578 #define MSR_IA32_VMX_CR0_FIXED1                         MSR_IA32_VMX_BASE+7
 579 #define MSR_IA32_VMX_CR4_FIXED0                         MSR_IA32_VMX_BASE+8
 580 #define MSR_IA32_VMX_CR4_FIXED1                         MSR_IA32_VMX_BASE+9
 581 #define MSR_IA32_VMX_VMCS_ENUM                          MSR_IA32_VMX_BASE+10
 582 #define MSR_IA32_VMX_PROCBASED_CTLS2            MSR_IA32_VMX_BASE+11
 583 #define MSR_IA32_VMX_EPT_VPID_CAP                       MSR_IA32_VMX_BASE+12
 584 #define         MSR_IA32_VMX_EPT_VPID_CAP_AD_SHIFT      21
 585 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS         MSR_IA32_VMX_BASE+13
 586 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS        MSR_IA32_VMX_BASE+14
 587 #define MSR_IA32_VMX_TRUE_VMEXIT_CTLS           MSR_IA32_VMX_BASE+15
 588 #define MSR_IA32_VMX_TRUE_VMENTRY_CTLS          MSR_IA32_VMX_BASE+16
 589 #define MSR_IA32_VMX_VMFUNC                                     MSR_IA32_VMX_BASE+17
 590
 591 #define MSR_IA32_DS_AREA                        0x600
 592
 593 #define MSR_IA32_PKG_POWER_SKU_UNIT             0x606
 594 #define MSR_IA32_PKG_C2_RESIDENCY               0x60D
 595 #define MSR_IA32_PKG_ENERGY_STATUS              0x611
 596 #define MSR_IA32_DDR_ENERGY_STATUS              0x619
 597 #define MSR_IA32_LLC_FLUSHED_RESIDENCY_TIMER    0x61D
 598 #define MSR_IA32_RING_PERF_STATUS               0x621
 599
 600 #define MSR_IA32_PKG_C8_RESIDENCY               0x630
 601 #define MSR_IA32_PKG_C9_RESIDENCY               0x631
 602 #define MSR_IA32_PKG_C10_RESIDENCY              0x632
 603
 604 #define MSR_IA32_PP0_ENERGY_STATUS              0x639
 605 #define MSR_IA32_PP1_ENERGY_STATUS              0x641
 606 #define MSR_IA32_IA_PERF_LIMIT_REASONS_SKL      0x64F
 607
 608 #define MSR_IA32_IA_PERF_LIMIT_REASONS          0x690
 609 #define MSR_IA32_GT_PERF_LIMIT_REASONS          0x6B0
 610
 611 #define MSR_IA32_TSC_DEADLINE                   0x6e0
 612
 613 #define MSR_IA32_EFER                           0xC0000080
 614 #define     MSR_IA32_EFER_SCE                       0x00000001
 615 #define     MSR_IA32_EFER_LME                       0x00000100
 616 #define     MSR_IA32_EFER_LMA                       0x00000400
 617 #define     MSR_IA32_EFER_NXE                       0x00000800
 618
 619 #define MSR_IA32_STAR                           0xC0000081
 620 #define MSR_IA32_LSTAR                          0xC0000082
 621 #define MSR_IA32_CSTAR                          0xC0000083
 622 #define MSR_IA32_FMASK                          0xC0000084
 623
 624 #define MSR_IA32_FS_BASE                        0xC0000100
 625 #define MSR_IA32_GS_BASE                        0xC0000101
 626 #define MSR_IA32_KERNEL_GS_BASE                 0xC0000102
 627 #define MSR_IA32_TSC_AUX                        0xC0000103
 628
 629 #define HV_VMX_EPTP_MEMORY_TYPE_UC              0x0
 630 #define HV_VMX_EPTP_MEMORY_TYPE_WB              0x6
 631 #define HV_VMX_EPTP_WALK_LENGTH(wl)             (0ULL | ((((wl) - 1) & 0x7) << 3))
 632 #define HV_VMX_EPTP_ENABLE_AD_FLAGS             (1ULL << 6)
 633
 634 #endif  /* _I386_PROC_REG_H_ */