osfmk/ppc/exception.h

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * Copyright (c) 1999-2003 Apple Computer, Inc.  All Rights Reserved.
   7  *
   8  * This file contains Original Code and/or Modifications of Original Code
   9  * as defined in and that are subject to the Apple Public Source License
  10  * Version 2.0 (the 'License'). You may not use this file except in
  11  * compliance with the License. Please obtain a copy of the License at
  12  * http://www.opensource.apple.com/apsl/ and read it before using this
  13  * file.
  14  *
  15  * The Original Code and all software distributed under the License are
  16  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  17  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  18  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  20  * Please see the License for the specific language governing rights and
  21  * limitations under the License.
  22  *
  23  * @APPLE_LICENSE_HEADER_END@
  24  */
  25 /*
  26  * @OSF_COPYRIGHT@
  27  */
  28
  29 /* Miscellaneous constants and structures used by the exception
  30  * handlers
  31  */
  32
  33 #ifndef _PPC_EXCEPTION_H_
  34 #define _PPC_EXCEPTION_H_
  35
  36 #include <ppc/savearea.h>
  37
  38 #ifndef ASSEMBLER
  39
  40 #include <cpus.h>
  41 #include <mach_kdb.h>
  42 #include <mach_kdp.h>
  43
  44 #include <mach/machine/vm_types.h>
  45 #include <mach/boolean.h>
  46 #include <kern/cpu_data.h>
  47 #include <pexpert/pexpert.h>
  48 #include <IOKit/IOInterrupts.h>
  49 #include <ppc/machine_routines.h>
  50
  51 /*      Per processor CPU features */
  52 #pragma pack(4)                                                 /* Make sure the structure stays as we defined it */
  53 struct procFeatures {
  54         unsigned int    Available;                      /* 0x000 */
  55 #define pfFloat         0x80000000
  56 #define pfFloatb        0
  57 #define pfAltivec       0x40000000
  58 #define pfAltivecb      1
  59 #define pfAvJava        0x20000000
  60 #define pfAvJavab       2
  61 #define pfSMPcap        0x10000000
  62 #define pfSMPcapb       3
  63 #define pfCanSleep      0x08000000
  64 #define pfCanSleepb     4
  65 #define pfCanNap        0x04000000
  66 #define pfCanNapb       5
  67 #define pfCanDoze       0x02000000
  68 #define pfCanDozeb      6
  69 #define pfThermal       0x01000000
  70 #define pfThermalb      7
  71 #define pfThermInt      0x00800000
  72 #define pfThermIntb     8
  73 #define pfSlowNap       0x00400000
  74 #define pfSlowNapb      9
  75 #define pfNoMuMMCK      0x00200000
  76 #define pfNoMuMMCKb     10
  77 #define pfNoL2PFNap     0x00100000
  78 #define pfNoL2PFNapb    11
  79 #define pfSCOMFixUp     0x00080000
  80 #define pfSCOMFixUpb    12
  81 #define pfHasDcba       0x00040000
  82 #define pfHasDcbab      13
  83 #define pfL1fa          0x00010000
  84 #define pfL1fab         15
  85 #define pfL2            0x00008000
  86 #define pfL2b           16
  87 #define pfL2fa          0x00004000
  88 #define pfL2fab         17
  89 #define pfL2i           0x00002000
  90 #define pfL2ib          18
  91 #define pfLClck         0x00001000
  92 #define pfLClckb        19
  93 #define pfWillNap       0x00000800
  94 #define pfWillNapb      20
  95 #define pfNoMSRir       0x00000400
  96 #define pfNoMSRirb      21
  97 #define pfL3pdet        0x00000200
  98 #define pfL3pdetb       22
  99 #define pf128Byte       0x00000080
 100 #define pf128Byteb      24
 101 #define pf32Byte        0x00000020
 102 #define pf32Byteb       26
 103 #define pf64Bit         0x00000010
 104 #define pf64Bitb        27
 105 #define pfL3            0x00000004
 106 #define pfL3b           29
 107 #define pfL3fa          0x00000002
 108 #define pfL3fab         30
 109 #define pfValid         0x00000001
 110 #define pfValidb        31
 111         unsigned short  rptdProc;                       /* 0x004 */
 112         unsigned short  lineSize;                       /* 0x006 */
 113         unsigned int    l1iSize;                        /* 0x008 */
 114         unsigned int    l1dSize;                        /* 0x00C */
 115         unsigned int    l2cr;                           /* 0x010 */
 116         unsigned int    l2Size;                         /* 0x014 */
 117         unsigned int    l3cr;                           /* 0x018 */
 118         unsigned int    l3Size;                         /* 0x01C */
 119         unsigned int    pfMSSCR0;                       /* 0x020 */
 120         unsigned int    pfMSSCR1;                       /* 0x024 */
 121         unsigned int    pfICTRL;                        /* 0x028 */
 122         unsigned int    pfLDSTCR;                       /* 0x02C */
 123         unsigned int    pfLDSTDB;                       /* 0x030 */
 124         unsigned int    pfMaxVAddr;                     /* 0x034 */
 125         unsigned int    pfMaxPAddr;                     /* 0x038 */
 126         unsigned int    pfPTEG;                         /* 0x03C */
 127         uint64_t                pfHID0;                         /* 0x040 */
 128         uint64_t                pfHID1;                         /* 0x048 */
 129         uint64_t                pfHID2;                         /* 0x050 */
 130         uint64_t                pfHID3;                         /* 0x058 */
 131         uint64_t                pfHID4;                         /* 0x060 */
 132         uint64_t                pfHID5;                         /* 0x068 */
 133         unsigned int    l2crOriginal;           /* 0x070 */
 134         unsigned int    l3crOriginal;           /* 0x074 */
 135         unsigned int    pfBootConfig;           /* 0x078 */
 136         unsigned int    pfPowerModes;           /* 0x07C */
 137 #define pmDPLLVmin              0x00010000
 138 #define pmDPLLVminb             15
 139 #define pmPowerTune             0x00000004
 140 #define pmPowerTuneb    29
 141 #define pmDualPLL               0x00000001
 142 #define pmDualPLLb              31
 143 };
 144 #pragma pack()
 145
 146 typedef struct procFeatures procFeatures;
 147
 148 #pragma pack(4)                                                 /* Make sure the structure stays as we defined it */
 149 struct thrmControl {
 150         unsigned int    maxTemp;                        /* Maximum temprature before damage */
 151         unsigned int    throttleTemp;           /* Temprature at which to throttle down */
 152         unsigned int    lowTemp;                        /* Interrupt when temprature drops below */
 153         unsigned int    highTemp;                       /* Interrupt when temprature exceeds this */
 154         unsigned int    thrm3val;                       /* Value for thrm3 register */
 155         unsigned int    rsvd[3];                        /* Pad to cache line */
 156 };
 157 #pragma pack()
 158
 159 typedef struct thrmControl thrmControl;
 160
 161 /*
 162  *
 163  *              Various performance counters
 164  */
 165 #pragma pack(4)                                                 /* Make sure the structure stays as we defined it */
 166 struct hwCtrs {
 167
 168         unsigned int    hwInVains;                              /* In vain */
 169         unsigned int    hwResets;                               /* Reset */
 170         unsigned int    hwMachineChecks;                /* Machine check */
 171         unsigned int    hwDSIs;                                 /* DSIs */
 172         unsigned int    hwISIs;                                 /* ISIs */
 173         unsigned int    hwExternals;                    /* Externals */
 174         unsigned int    hwAlignments;                   /* Alignment */
 175         unsigned int    hwPrograms;                     /* Program */
 176         unsigned int    hwFloatPointUnavailable;        /* Floating point */
 177         unsigned int    hwDecrementers;                 /* Decrementer */
 178         unsigned int    hwIOErrors;                     /* I/O error */
 179         unsigned int    hwrsvd0;                                /* Reserved */
 180         unsigned int    hwSystemCalls;                  /* System call */
 181         unsigned int    hwTraces;                               /* Trace */
 182         unsigned int    hwFloatingPointAssists; /* Floating point assist */
 183         unsigned int    hwPerformanceMonitors;  /* Performance monitor */
 184         unsigned int    hwAltivecs;                     /* VMX */
 185         unsigned int    hwrsvd1;                                /* Reserved */
 186         unsigned int    hwrsvd2;                                /* Reserved */
 187         unsigned int    hwrsvd3;                                /* Reserved */
 188         unsigned int    hwInstBreakpoints;              /* Instruction breakpoint */
 189         unsigned int    hwSystemManagements;    /* System management */
 190         unsigned int    hwAltivecAssists;               /* Altivec Assist */
 191         unsigned int    hwThermal;                              /* Thermals */
 192         unsigned int    hwrsvd5;                                /* Reserved */
 193         unsigned int    hwrsvd6;                                /* Reserved */
 194         unsigned int    hwrsvd7;                                /* Reserved */
 195         unsigned int    hwrsvd8;                                /* Reserved */
 196         unsigned int    hwrsvd9;                                /* Reserved */
 197         unsigned int    hwrsvd10;                               /* Reserved */
 198         unsigned int    hwrsvd11;                               /* Reserved */
 199         unsigned int    hwrsvd12;                               /* Reserved */
 200         unsigned int    hwrsvd13;                               /* Reserved */
 201         unsigned int    hwTrace601;                             /* Trace */
 202         unsigned int    hwSIGPs;                                /* SIGP */
 203         unsigned int    hwPreemptions;                  /* Preemption */
 204         unsigned int    hwContextSwitchs;               /* Context switch */
 205         unsigned int    hwShutdowns;                    /* Shutdowns */
 206         unsigned int    hwChokes;                               /* System ABENDs */
 207         unsigned int    hwDataSegments;                 /* Data Segment Interruptions */
 208         unsigned int    hwInstructionSegments;  /* Instruction Segment Interruptions */
 209         unsigned int    hwSoftPatches;                  /* Soft Patch interruptions */
 210         unsigned int    hwMaintenances;                 /* Maintenance interruptions */
 211         unsigned int    hwInstrumentations;             /* Instrumentation interruptions */
 212         unsigned int    hwrsvd14;                               /* Reswerved */
 213 /*                                                                                      0x0B4 */
 214
 215         unsigned int    hwspare0[17];                   /* Reserved */
 216         unsigned int    hwRedrives;                             /* Number of redriven interrupts */
 217         unsigned int    hwSteals;                               /* PTE Steals */
 218 /*                                                                                      0x100 */
 219
 220         unsigned int    hwMckHang;                              /* ? */
 221         unsigned int    hwMckSLBPE;                             /* ? */
 222         unsigned int    hwMckTLBPE;                             /* ? */
 223         unsigned int    hwMckERCPE;                             /* ? */
 224         unsigned int    hwMckL1DPE;                             /* ? */
 225         unsigned int    hwMckL1TPE;                             /* ? */
 226         unsigned int    hwMckUE;                                /* ? */
 227         unsigned int    hwMckIUE;                               /* ? */
 228         unsigned int    hwMckIUEr;                              /* ? */
 229         unsigned int    hwMckDUE;                               /* ? */
 230         unsigned int    hwMckDTW;                               /* ? */
 231         unsigned int    hwMckUnk;                               /* ? */
 232         unsigned int    hwMckExt;                               /* ? */
 233         unsigned int    hwMckICachePE;                  /* ? */
 234         unsigned int    hwMckITagPE;                    /* ? */
 235         unsigned int    hwMckIEratPE;                   /* ? */
 236         unsigned int    hwMckDEratPE;                   /* ? */
 237         unsigned int    hwspare2[15];                   /* Pad to next 128 bndry */
 238 /*                                                                                      0x180 */
 239
 240         unsigned int    napStamp[2];                    /* Time base when we napped */
 241         unsigned int    napTotal[2];                    /* Total nap time in ticks */
 242         unsigned int    numSIGPast;                             /* Number of SIGP asts recieved */
 243         unsigned int    numSIGPcpureq;                  /* Number of SIGP cpu requests recieved */
 244         unsigned int    numSIGPdebug;                   /* Number of SIGP debugs recieved */
 245         unsigned int    numSIGPwake;                    /* Number of SIGP wakes recieved */
 246         unsigned int    numSIGPtimo;                    /* Number of SIGP send timeouts */
 247         unsigned int    numSIGPmast;                    /* Number of SIGPast messages merged */
 248         unsigned int    numSIGPmwake;                   /* Number of SIGPwake messages merged */
 249
 250         unsigned int    hwspare3[21];                   /* Pad to 512 */
 251
 252 };
 253 #pragma pack()
 254
 255 typedef struct hwCtrs hwCtrs;
 256
 257 struct patch_entry {
 258         unsigned int    *addr;
 259         unsigned int    data;
 260         unsigned int    type;
 261         unsigned int    value;
 262 };
 263
 264 typedef struct patch_entry patch_entry_t;
 265
 266 #define PATCH_INVALID           0
 267 #define PATCH_PROCESSOR         1
 268 #define PATCH_FEATURE           2
 269
 270 #define PATCH_TABLE_SIZE        12
 271
 272 #define PatchExt32              0x80000000
 273 #define PatchExt32b             0
 274 #define PatchLwsync             0x40000000
 275 #define PatchLwsyncb    1
 276
 277 /* When an exception is taken, this info is accessed via sprg0 */
 278 /* We should always have this one on a cache line boundary */
 279
 280 #pragma pack(4)                                                 /* Make sure the structure stays as we defined it */
 281 struct per_proc_info {
 282         unsigned short  cpu_number;
 283         unsigned short  cpu_flags;                      /* Various low-level flags */
 284         vm_offset_t     istackptr;
 285         vm_offset_t     intstack_top_ss;
 286
 287         vm_offset_t     debstackptr;
 288         vm_offset_t     debstack_top_ss;
 289
 290         unsigned int    spcFlags;                       /* Special thread flags */
 291         unsigned int    Uassist;                        /* User Assist Word */
 292         unsigned int    old_thread;
 293
 294         /* PPC cache line boundary here - 020 */
 295
 296         unsigned int    rsrvd020[2];
 297         unsigned int    need_ast;                       /* pointer to need_ast[CPU_NO] */
 298 /*
 299  *      Note: the following two pairs of words need to stay in order and each pair must
 300  *      be in the same reservation (line) granule
 301  */
 302         struct facility_context *FPU_owner;     /* Owner of the FPU on this cpu */
 303         unsigned int    liveVRSave;                     /* VRSave assiciated with live vector registers */
 304         struct facility_context *VMX_owner;     /* Owner of the VMX on this cpu */
 305         unsigned int    holdQFret;                      /* Hold off releasing quickfret list */
 306         unsigned int    save_exception_type;
 307
 308         /* PPC cache line boundary here - 040 */
 309         addr64_t                quickfret;                      /* List of saveareas to release */
 310         addr64_t                lclfree;                        /* Pointer to local savearea list */
 311         unsigned int    lclfreecnt;                     /* Entries in local savearea list */
 312         unsigned int    spcTRc;                         /* Special trace count */
 313         unsigned int    spcTRp;                         /* Special trace buffer pointer */
 314         unsigned int    ppbbTaskEnv;            /* BlueBox Task Environment */
 315
 316         /* PPC cache line boundary here - 060 */
 317         boolean_t               interrupts_enabled;
 318         IOInterruptHandler      interrupt_handler;
 319         void *                  interrupt_nub;
 320         unsigned int    interrupt_source;
 321         void *                  interrupt_target;
 322         void *                  interrupt_refCon;
 323         uint64_t                next_savearea;                  /* pointer to the next savearea */
 324
 325         /* PPC cache line boundary here - 080 */
 326         unsigned int    MPsigpStat;                     /* Signal Processor status (interlocked update for this one) */
 327 #define MPsigpMsgp              0xC0000000              /* Message pending (busy + pass ) */
 328 #define MPsigpBusy              0x80000000              /* Processor area busy, i.e., locked */
 329 #define MPsigpPass              0x40000000              /* Busy lock passed to receiving processor */
 330 #define MPsigpAck               0x20000000              /* Ack Busy lock passed to receiving processor */
 331 #define MPsigpSrc               0x000000FF              /* Processor that owns busy, i.e., the ID of */
 332                                                                                 /*   whomever set busy. When a busy is passed, */
 333                                                                                 /*   this is the requestor of the function. */
 334 #define MPsigpFunc              0x0000FF00              /* Current function */
 335 #define MPsigpIdle              0x00                    /* No function pending */
 336 #define MPsigpSigp              0x04                    /* Signal a processor */
 337 #define SIGPast         0                                       /* Requests an ast on target processor */
 338 #define SIGPcpureq      1                                       /* Requests CPU specific function */
 339 #define SIGPdebug       2                                       /* Requests a debugger entry */
 340 #define SIGPwake        3                                       /* Wake up a sleeping processor */
 341 #define CPRQtemp        0                                       /* Get temprature of processor */
 342 #define CPRQtimebase    1                                       /* Get timebase of processor */
 343 #define CPRQsegload     2                                       /* Segment registers reload */
 344 #define CPRQscom        3                                       /* SCOM */
 345 #define CPRQchud        4                                       /* CHUD perfmon */
 346         unsigned int    MPsigpParm0;            /* SIGP parm 0 */
 347         unsigned int    MPsigpParm1;            /* SIGP parm 1 */
 348         unsigned int    MPsigpParm2;            /* SIGP parm 2 */
 349         cpu_id_t                cpu_id;
 350         vm_offset_t             start_paddr;
 351         unsigned int    ruptStamp[2];           /* Timebase at last interruption */
 352
 353         /* PPC cache line boundary here - 0A0 */
 354         procFeatures    pf;                                     /* Processor features */
 355
 356         /* PPC cache line boundary here - 120 */
 357         thrmControl             thrm;                           /* Thermal controls */
 358
 359         /* PPC cache line boundary here - 140 */
 360         unsigned int    ppRsvd140[8];           /* Reserved */
 361
 362         /* PPC cache line boundary here - 160 */
 363         time_base_enable_t      time_base_enable;
 364         unsigned int    ppRsvd164[4];           /* Reserved */
 365         cpu_data_t              pp_cpu_data;            /* cpu data info */
 366
 367         /* PPC cache line boundary here - 180 */
 368         unsigned int    ppRsvd180[2];           /* Reserved */
 369         uint64_t                validSegs;                      /* Valid SR/STB slots */
 370         addr64_t                ppUserPmap;                     /* Current user state pmap (physical address) */
 371         unsigned int    ppUserPmapVirt;         /* Current user state pmap (virtual address) */
 372         unsigned int    ppMapFlags;                     /* Mapping flags */
 373
 374         /* PPC cache line boundary here - 1A0 */
 375         unsigned short  ppInvSeg;                       /* Forces complete invalidate of SRs/SLB (this must stay with ppInvSeg) */
 376         unsigned short  ppCurSeg;                       /* Set to 1 if user segments, 0 if kernel (this must stay with ppInvSeg) */
 377         unsigned int    ppSegSteal;                     /* Count of segment slot steals */
 378         ppnum_t                 VMMareaPhys;            /* vmm state page physical addr */
 379         unsigned int    VMMXAFlgs;                      /* vmm extended flags */
 380         unsigned int    FAMintercept;           /* vmm FAM Exceptions to intercept */
 381         unsigned int    rsrvd1B4[3];            /* Reserved slots */
 382
 383         /* PPC cache line boundary here - 1C0 */
 384         unsigned int    ppCIOmp[16];            /* Linkage mapping for copyin/out - 64 bytes */
 385
 386         /* PPC cache line boundary here - 200 */
 387         uint64_t                tempr0;                         /* temporary savearea */
 388         uint64_t                tempr1;
 389         uint64_t                tempr2;
 390         uint64_t                tempr3;
 391
 392         uint64_t                tempr4;
 393         uint64_t                tempr5;
 394         uint64_t                tempr6;
 395         uint64_t                tempr7;
 396
 397         uint64_t                tempr8;
 398         uint64_t                tempr9;
 399         uint64_t                tempr10;
 400         uint64_t                tempr11;
 401
 402         uint64_t                tempr12;
 403         uint64_t                tempr13;
 404         uint64_t                tempr14;
 405         uint64_t                tempr15;
 406
 407         uint64_t                tempr16;
 408         uint64_t                tempr17;
 409         uint64_t                tempr18;
 410         uint64_t                tempr19;
 411
 412         uint64_t                tempr20;
 413         uint64_t                tempr21;
 414         uint64_t                tempr22;
 415         uint64_t                tempr23;
 416
 417         uint64_t                tempr24;
 418         uint64_t                tempr25;
 419         uint64_t                tempr26;
 420         uint64_t                tempr27;
 421
 422         uint64_t                tempr28;
 423         uint64_t                tempr29;
 424         uint64_t                tempr30;
 425         uint64_t                tempr31;
 426
 427
 428         /* PPC cache line boundary here - 300 */
 429         double                  emfp0;                          /* Copies of floating point registers */
 430         double                  emfp1;                          /* Used for emulation purposes */
 431         double                  emfp2;
 432         double                  emfp3;
 433
 434         double                  emfp4;
 435         double                  emfp5;
 436         double                  emfp6;
 437         double                  emfp7;
 438
 439         double                  emfp8;
 440         double                  emfp9;
 441         double                  emfp10;
 442         double                  emfp11;
 443
 444         double                  emfp12;
 445         double                  emfp13;
 446         double                  emfp14;
 447         double                  emfp15;
 448
 449         double                  emfp16;
 450         double                  emfp17;
 451         double                  emfp18;
 452         double                  emfp19;
 453
 454         double                  emfp20;
 455         double                  emfp21;
 456         double                  emfp22;
 457         double                  emfp23;
 458
 459         double                  emfp24;
 460         double                  emfp25;
 461         double                  emfp26;
 462         double                  emfp27;
 463
 464         double                  emfp28;
 465         double                  emfp29;
 466         double                  emfp30;
 467         double                  emfp31;
 468
 469 /*                                                                 - 400 */
 470         unsigned int    emfpscr_pad;
 471         unsigned int    emfpscr;
 472         unsigned int    empadfp[6];
 473
 474 /*                                                                 - 420 */
 475         unsigned int    emvr0[4];                       /* Copies of vector registers used both */
 476         unsigned int    emvr1[4];                       /* for full vector emulation or */
 477         unsigned int    emvr2[4];                       /* as saveareas while assisting denorms */
 478         unsigned int    emvr3[4];
 479         unsigned int    emvr4[4];
 480         unsigned int    emvr5[4];
 481         unsigned int    emvr6[4];
 482         unsigned int    emvr7[4];
 483         unsigned int    emvr8[4];
 484         unsigned int    emvr9[4];
 485         unsigned int    emvr10[4];
 486         unsigned int    emvr11[4];
 487         unsigned int    emvr12[4];
 488         unsigned int    emvr13[4];
 489         unsigned int    emvr14[4];
 490         unsigned int    emvr15[4];
 491         unsigned int    emvr16[4];
 492         unsigned int    emvr17[4];
 493         unsigned int    emvr18[4];
 494         unsigned int    emvr19[4];
 495         unsigned int    emvr20[4];
 496         unsigned int    emvr21[4];
 497         unsigned int    emvr22[4];
 498         unsigned int    emvr23[4];
 499         unsigned int    emvr24[4];
 500         unsigned int    emvr25[4];
 501         unsigned int    emvr26[4];
 502         unsigned int    emvr27[4];
 503         unsigned int    emvr28[4];
 504         unsigned int    emvr29[4];
 505         unsigned int    emvr30[4];
 506         unsigned int    emvr31[4];
 507         unsigned int    emvscr[4];
 508         unsigned int    empadvr[4];
 509 /*                                                                 - 640 */
 510 /* note implicit dependence on kSkipListMaxLists, which must be <= 28 */
 511     addr64_t            skipListPrev[28];       /* prev ptrs saved as side effect of calling mapSearchFull() */
 512
 513 /*                                                                 - 720 */
 514
 515         unsigned int    patcharea[56];
 516 /*                                                                 - 800 */
 517
 518         hwCtrs                  hwCtr;                                  /* Hardware exception counters */
 519 /*                                                                 - A00 */
 520
 521         unsigned int    pppadpage[384];                 /* Pad to end of page */
 522 /*                                                                 - 1000 */
 523
 524
 525 };
 526
 527 #define pp_preemption_count     pp_cpu_data.preemption_level
 528 #define pp_simple_lock_count    pp_cpu_data.simple_lock_count
 529 #define pp_interrupt_level      pp_cpu_data.interrupt_level
 530
 531 #pragma pack()
 532
 533
 534 extern struct per_proc_info per_proc_info[NCPUS];
 535
 536
 537 extern char *trap_type[];
 538
 539 #endif /* ndef ASSEMBLER */                                                                                     /* with this savearea should be redriven */
 540
 541 /* cpu_flags defs */
 542 #define SIGPactive      0x8000
 543 #define needSRload      0x4000
 544 #define turnEEon        0x2000
 545 #define traceBE     0x1000                                      /* user mode BE tracing in enabled */
 546 #define traceBEb    3                                           /* bit number for traceBE */
 547 #define SleepState      0x0800
 548 #define SleepStateb     4
 549 #define mcountOff       0x0400
 550 #define SignalReady     0x0200
 551 #define BootDone        0x0100
 552 #define loadMSR         0x7FF4
 553
 554 #define T_VECTOR_SIZE   4                                       /* function pointer size */
 555
 556 /* Hardware exceptions */
 557
 558 #define T_IN_VAIN                               (0x00 * T_VECTOR_SIZE)
 559 #define T_RESET                                 (0x01 * T_VECTOR_SIZE)
 560 #define T_MACHINE_CHECK                 (0x02 * T_VECTOR_SIZE)
 561 #define T_DATA_ACCESS                   (0x03 * T_VECTOR_SIZE)
 562 #define T_INSTRUCTION_ACCESS    (0x04 * T_VECTOR_SIZE)
 563 #define T_INTERRUPT                             (0x05 * T_VECTOR_SIZE)
 564 #define T_ALIGNMENT                             (0x06 * T_VECTOR_SIZE)
 565 #define T_PROGRAM                               (0x07 * T_VECTOR_SIZE)
 566 #define T_FP_UNAVAILABLE                (0x08 * T_VECTOR_SIZE)
 567 #define T_DECREMENTER                   (0x09 * T_VECTOR_SIZE)
 568 #define T_IO_ERROR                              (0x0a * T_VECTOR_SIZE)
 569 #define T_RESERVED                              (0x0b * T_VECTOR_SIZE)
 570 #define T_SYSTEM_CALL                   (0x0c * T_VECTOR_SIZE)
 571 #define T_TRACE                                 (0x0d * T_VECTOR_SIZE)
 572 #define T_FP_ASSIST                             (0x0e * T_VECTOR_SIZE)
 573 #define T_PERF_MON                              (0x0f * T_VECTOR_SIZE)
 574 #define T_VMX                                   (0x10 * T_VECTOR_SIZE)
 575 #define T_INVALID_EXCP0                 (0x11 * T_VECTOR_SIZE)
 576 #define T_INVALID_EXCP1                 (0x12 * T_VECTOR_SIZE)
 577 #define T_INVALID_EXCP2                 (0x13 * T_VECTOR_SIZE)
 578 #define T_INSTRUCTION_BKPT              (0x14 * T_VECTOR_SIZE)
 579 #define T_SYSTEM_MANAGEMENT             (0x15 * T_VECTOR_SIZE)
 580 #define T_ALTIVEC_ASSIST                (0x16 * T_VECTOR_SIZE)
 581 #define T_THERMAL                               (0x17 * T_VECTOR_SIZE)
 582 #define T_INVALID_EXCP5                 (0x18 * T_VECTOR_SIZE)
 583 #define T_INVALID_EXCP6                 (0x19 * T_VECTOR_SIZE)
 584 #define T_INVALID_EXCP7                 (0x1A * T_VECTOR_SIZE)
 585 #define T_INVALID_EXCP8                 (0x1B * T_VECTOR_SIZE)
 586 #define T_INVALID_EXCP9                 (0x1C * T_VECTOR_SIZE)
 587 #define T_INVALID_EXCP10                (0x1D * T_VECTOR_SIZE)
 588 #define T_INVALID_EXCP11                (0x1E * T_VECTOR_SIZE)
 589 #define T_INVALID_EXCP12                (0x1F * T_VECTOR_SIZE)
 590 #define T_EMULATE                               (0x20 * T_VECTOR_SIZE)
 591
 592 #define T_RUNMODE_TRACE                 (0x21 * T_VECTOR_SIZE) /* 601 only */
 593
 594 #define T_SIGP                                  (0x22 * T_VECTOR_SIZE)
 595 #define T_PREEMPT                               (0x23 * T_VECTOR_SIZE)
 596 #define T_CSWITCH                               (0x24 * T_VECTOR_SIZE)
 597 #define T_SHUTDOWN                              (0x25 * T_VECTOR_SIZE)
 598 #define T_CHOKE                                 (0x26 * T_VECTOR_SIZE)
 599
 600 #define T_DATA_SEGMENT                  (0x27 * T_VECTOR_SIZE)
 601 #define T_INSTRUCTION_SEGMENT   (0x28 * T_VECTOR_SIZE)
 602
 603 #define T_SOFT_PATCH                    (0x29 * T_VECTOR_SIZE)
 604 #define T_MAINTENANCE                   (0x2A * T_VECTOR_SIZE)
 605 #define T_INSTRUMENTATION               (0x2B * T_VECTOR_SIZE)
 606 #define T_ARCHDEP0                              (0x2C * T_VECTOR_SIZE)
 607
 608 #define T_AST                                   (0x100 * T_VECTOR_SIZE)
 609 #define T_MAX                                   T_CHOKE          /* Maximum exception no */
 610
 611 #define T_FAM                                   0x00004000
 612
 613 #define EXCEPTION_VECTOR(exception)     (exception * 0x100 / T_VECTOR_SIZE )
 614
 615 /*
 616  *              System choke (failure) codes
 617  */
 618
 619 #define failDebug 0
 620 #define failStack 1
 621 #define failMapping 2
 622 #define failContext 3
 623 #define failNoSavearea 4
 624 #define failSaveareaCorr 5
 625 #define failBadLiveContext 6
 626 #define failSkipLists 7
 627 #define failUnalignedStk 8
 628
 629 /* Always must be last - update failNames table in model_dep.c as well */
 630 #define failUnknown 9
 631
 632 #ifndef ASSEMBLER
 633
 634 #pragma pack(4)                                                 /* Make sure the structure stays as we defined it */
 635 typedef struct resethandler {
 636         unsigned int    type;
 637         vm_offset_t     call_paddr;
 638         vm_offset_t     arg__paddr;
 639 } resethandler_t;
 640 #pragma pack()
 641
 642 extern resethandler_t ResetHandler;
 643
 644 #endif
 645
 646 #define RESET_HANDLER_NULL      0x0
 647 #define RESET_HANDLER_START     0x1
 648 #define RESET_HANDLER_BUPOR     0x2
 649 #define RESET_HANDLER_IGNORE    0x3
 650
 651 #endif /* _PPC_EXCEPTION_H_ */