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1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22 /*
23 * @OSF_COPYRIGHT@
24 */
25
26 #define __APPLE_API_PRIVATE
27
28 #include <cpus.h>
29 #include <mach_kdb.h>
30 #include <mach_kdp.h>
31 #include <mach_kgdb.h>
32 #include <ppc/asm.h>
33 #include <ppc/proc_reg.h>
34 #include <ppc/spec_reg.h>
35 #include <machine/cpu_capabilities.h>
36 #include <mach/ppc/vm_param.h>
37 #include <assym.s>
38
39 #define ptFilter 0
40 #define ptVersion 4
41 #define ptRevision 6
42 #define ptFeatures 8
43 #define ptCPUCap 12
44 #define ptPwrModes 16
45 #define ptPatch 20
46 #define ptInitRout 24
47 #define ptRptdProc 28
48 #define ptLineSize 32
49 #define ptl1iSize 36
50 #define ptl1dSize 40
51 #define ptPTEG 44
52 #define ptMaxVAddr 48
53 #define ptMaxPAddr 52
54 #define ptSize 56
55
56 #define bootCPU 10
57 #define firstInit 9
58 #define firstBoot 8
59
60 /*
61 * Interrupt and bootup stack for initial processor
62 */
63
64 .file "start.s"
65
66 /*
67 * All CPUs start here.
68 *
69 * This code is called from SecondaryLoader
70 *
71 * Various arguments are passed via a table:
72 * R3 = pointer to other startup parameters
73 */
74 .text
75
76 ENTRY(resetPOR,TAG_NO_FRAME_USED)
77
78 li r12,0 ; Get a 0
79 stw r12,0xF0(0) ; Make sure the special flag is clear
80 mtmsrd r12 ; Make sure we are in 32-bit mode
81 isync ; Really make sure
82 lwz r3,0xF4(0) ; Get the boot_args pointer
83 b startJoin ; Join up...
84
85
86 ENTRY(_start_cpu,TAG_NO_FRAME_USED)
87 crclr bootCPU ; Set non-boot processor
88 crclr firstInit ; Set not first time init
89 mr r30,r3 ; Set current per_proc
90
91 ;
92 ; Note that we are just trying to get close. The real TB sync will take
93 ; place later. The value we are loading is set in two places. For the
94 ; main processor, it will be the TB at the last interrupt before we went
95 ; to sleep. For the others, it will be the time just before the main
96 ; processor woke us up.
97 ;
98
99 lwz r15,ruptStamp(r3) ; Get the timebase from the other processor
100 li r17,0 ; Clear this out
101 lwz r16,ruptStamp+4(r3) ; Get the timebase from the other processor
102 mtspr tbl,r17 ; Clear bottom so we do not tick
103 mtspr tbu,r15 ; Set top
104 mtspr tbl,r16 ; Then bottom again
105 b allstart
106
107 ENTRY(_start,TAG_NO_FRAME_USED)
108
109 startJoin:
110 mflr r2 ; Save the return address
111 lis r30,hi16(EXT(per_proc_info)) ; Set current per_proc
112 ori r30,r30,lo16(EXT(per_proc_info)) ; Set current per_proc
113 crset bootCPU ; Set boot processor
114
115 lwz r17,pfAvailable(r30) ; Get the available bits
116 rlwinm. r0,r17,0,pfValidb,pfValidb ; Have we initialized the feature flags yet?
117 crmove firstInit,cr0_eq ; Set if we are doing first time init
118 bne allstart ; Yeah, we must be waking up from sleep...
119
120 ;
121 ; Here is where we do any one time general low-level initialization
122
123 lis r20,HIGH_ADDR(fwdisplock) ; Get address of the firmware display lock
124 li r19,0 ; Zorch a register
125 ori r20,r20,LOW_ADDR(fwdisplock) ; Get address of the firmware display lock
126 stw r19,0(r20) ; Make sure the lock is free
127
128 allstart:
129 mr r31,r3 ; Save away arguments
130
131 crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
132
133 mtsprg 0,r30 ; Set the per_proc
134
135 li r9,0 ; Clear out a register
136 mtsprg 1,r9 ; Clear the SPRGs
137 mtsprg 2,r9
138 mtsprg 3,r9
139
140 li r7,MSR_VM_OFF ; Get real mode MSR
141 mtmsr r7 ; Set the real mode SRR
142 isync
143
144 lis r26,hi16(processor_types) ; Point to processor table
145 ori r26,r26,lo16(processor_types) ; Other half
146 mfpvr r10 ; Get the PVR
147
148 nextPVR: lwz r28,ptFilter(r26) ; Get the filter
149 lwz r27,ptVersion(r26) ; Get the version and revision codes
150 and r28,r10,r28 ; Throw away dont care bits
151 cmplw r27,r28 ; Is this the right set?
152 beq donePVR ; We have the right one...
153 addi r26,r26,ptSize ; Point to the next type
154 b nextPVR ; Check it out...
155
156 donePVR: lwz r20,ptInitRout(r26) ; Grab the special init routine
157 mtlr r20 ; Setup to call the init
158
159 bf firstBoot,notFirst ; Not first boot, go...
160
161 ;
162 ; The following code just does a general initialization of the features just
163 ; after the initial first-time boot. This is not done after waking up or on
164 ; any "secondary" processor. Just after the boot-processor init, we copy the
165 ; features to any possible per_proc.
166 ;
167 ; We are just setting defaults. The specific initialization code will modify these
168 ; if necessary.
169 ;
170 lis r18,hi16(EXT(_cpu_capabilities)) ; Get the address of _cpu_capabilities
171 ori r18,r18,lo16(EXT(_cpu_capabilities))
172 lwz r17,ptCPUCap(r26) ; Get the default cpu capabilities
173 stw r17, 0(r18) ; Save the default value in _cpu_capabilities
174
175 lwz r17,ptFeatures(r26) ; Pick up the features
176
177 lwz r18,ptRptdProc(r26) ; Get the reported processor
178 sth r18,pfrptdProc(r30) ; Set the reported processor
179
180 lwz r13,ptPwrModes(r26) ; Get the supported power modes
181 stw r13,pfPowerModes(r30) ; Set the supported power modes
182
183 lwz r13,ptLineSize(r26) ; Get the cache line size
184 sth r13,pflineSize(r30) ; Save it
185 lwz r13,ptl1iSize(r26) ; Get icache size
186 stw r13,pfl1iSize(r30) ; Save it
187 lwz r13,ptl1dSize(r26) ; Get dcache size
188 stw r13,pfl1dSize(r30) ; Save it
189 lwz r13,ptPTEG(r26) ; Get PTEG size address
190 stw r13,pfPTEG(r30) ; Save it
191 lwz r13,ptMaxVAddr(r26) ; Get max virtual address
192 stw r13,pfMaxVAddr(r30) ; Save it
193 lwz r13,ptMaxPAddr(r26) ; Get max physical address
194 stw r13,pfMaxPAddr(r30) ; Save it
195 lis r11,hi16(EXT(patch_table))
196 ori r11,r11,lo16(EXT(patch_table))
197 lwz r19,ptPatch(r26) ; Get ptPatch field
198 li r12,PATCH_TABLE_SIZE
199 mtctr r12
200 patch_loop:
201 lwz r16,patchType(r11) ; Load the patch type
202 lwz r15,patchValue(r11) ; Load the patch value
203 cmplwi cr1,r16,PATCH_FEATURE ; Is it a patch feature entry
204 and. r14,r15,r19 ; Is it set in the patch feature
205 crandc cr0_eq,cr1_eq,cr0_eq ; Do we have a match
206 beq patch_apply ; Yes, patch memory
207 cmplwi cr1,r16,PATCH_PROCESSOR ; Is it a patch processor entry
208 cmplw cr0,r15,r18 ; Check matching processor
209 crand cr0_eq,cr1_eq,cr0_eq ; Do we have a match
210 bne patch_skip ; No, skip patch memory
211 patch_apply:
212 lwz r13,patchAddr(r11) ; Load the address to patch
213 lwz r14,patchData(r11) ; Load the patch data
214 stw r14,0(r13) ; Patch the location
215 dcbf 0,r13 ; Flush the old one
216 sync ; Make sure we see it all
217 icbi 0,r13 ; Flush the i-cache
218 isync ; Hang out
219 sync ; Hang out some more...
220 patch_skip:
221 addi r11,r11,peSize ; Point to the next patch entry
222 bdnz patch_loop ; Loop if in the range
223 b doOurInit ; Go do processor specific initialization...
224
225 notFirst: lwz r17,pfAvailable(r30) ; Get our features
226
227 doOurInit: mr. r20,r20 ; See if initialization routine
228 crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
229 bnelrl ; Do the initialization
230
231 ori r17,r17,lo16(pfValid) ; Set the valid bit
232 stw r17,pfAvailable(r30) ; Set the available features
233
234 bf firstBoot,nofeatcpy ; Skip feature propagate if not first time boot...
235
236 li r2,NCPUS ; Get number of CPUs
237 lis r23,hi16(EXT(per_proc_info)) ; Set base per_proc
238 ori r23,r23,lo16(EXT(per_proc_info)) ; Set base per_proc
239 addi r6,r23,ppSize ; Point to the next one
240
241 cpyFCpu: addic. r2,r2,-1 ; Count down
242 la r8,pfAvailable(r23) ; Point to features of boot processor
243 la r7,pfAvailable(r6) ; Point to features of our processor
244 li r9,pfSize/4 ; Get size of a features area
245 ble-- nofeatcpy ; Copied all we need
246
247 cpyFeat: subi r9,r9,1 ; Count word
248 lwz r0,0(r8) ; Get boot cpu features
249 stw r0,0(r7) ; Copy to ours
250 mr. r9,r9 ; Finished?
251 addi r7,r7,4 ; Next out
252 addi r8,r8,4 ; Next in
253 bgt cpyFeat ; Copy all boot cpu features to us...
254
255 lwz r17,pfAvailable(r6) ; Get our newly initialized features
256 addi r6,r6,ppSize ; Point to the next one
257 b cpyFCpu ; Do the next per_proc...
258
259
260 nofeatcpy: rlwinm. r0,r17,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
261 mtsprg 2,r17 ; Remember the feature flags
262
263 bne++ start64 ; Skip following if 64-bit...
264
265 mfspr r6,hid0 ; Get the HID0
266 rlwinm r6,r6,0,sleep+1,doze-1 ; Remove any vestiges of sleep
267 mtspr hid0,r6 ; Set the insominac HID0
268 isync
269
270 ; Clear the BAT registers
271
272 li r9,0 ; Clear out a register
273 sync
274 isync
275 mtdbatu 0,r9 ; Invalidate maps
276 mtdbatl 0,r9 ; Invalidate maps
277 mtdbatu 1,r9 ; Invalidate maps
278 mtdbatl 1,r9 ; Invalidate maps
279 mtdbatu 2,r9 ; Invalidate maps
280 mtdbatl 2,r9 ; Invalidate maps
281 mtdbatu 3,r9 ; Invalidate maps
282 mtdbatl 3,r9 ; Invalidate maps
283 sync
284 isync
285 mtibatu 0,r9 ; Invalidate maps
286 mtibatl 0,r9 ; Invalidate maps
287 mtibatu 1,r9 ; Invalidate maps
288 mtibatl 1,r9 ; Invalidate maps
289 mtibatu 2,r9 ; Invalidate maps
290 mtibatl 2,r9 ; Invalidate maps
291 mtibatu 3,r9 ; Invalidate maps
292 mtibatl 3,r9 ; Invalidate maps
293 sync
294 isync
295 b startcommon ; Go join up the common start routine
296
297 start64: lis r5,hi16(startcommon) ; Get top of address of continue point
298 mfspr r6,hid0 ; Get the HID0
299 ori r5,r5,lo16(startcommon) ; Get low of address of continue point
300 lis r9,hi16(MASK(MSR_HV)) ; ?
301 lis r20,hi16(dozem|napm|sleepm) ; Get mask of power saving features
302 li r7,MSR_VM_OFF ; Get real mode MSR, 64-bit off
303 sldi r9,r9,32 ; Slide into position
304 sldi r20,r20,32 ; Slide power stuff into position
305 or r9,r9,r7 ; Form initial MSR
306 andc r6,r6,r20 ; Remove any vestiges of sleep
307 isync
308 mtspr hid0,r6 ; Set the insominac HID0
309 mfspr r6,hid0 ; Get it
310 mfspr r6,hid0 ; Get it
311 mfspr r6,hid0 ; Get it
312 mfspr r6,hid0 ; Get it
313 mfspr r6,hid0 ; Get it
314 mfspr r6,hid0 ; Get it
315 isync
316 mtsrr0 r5 ; Set the continue point
317 mtsrr1 r9 ; Set our normal disabled MSR
318 rfid ; Tally ho...
319
320 .align 5
321
322 startcommon:
323 rlwinm. r0,r17,0,pfFloatb,pfFloatb ; See if there is floating point
324 beq- noFloat ; Nope, this is a really stupid machine...
325
326 li r0,MSR_VM_OFF|MASK(MSR_FP) ; Enable for floating point
327 mtmsr r0 /* Set the standard MSR values */
328 isync
329
330 lis r5,HIGH_ADDR(EXT(FloatInit)) /* Get top of floating point init value */
331 ori r5,r5,LOW_ADDR(EXT(FloatInit)) /* Slam bottom */
332 lfd f0,0(r5) /* Initialize FP0 */
333 fmr f1,f0 /* Ours in not */
334 fmr f2,f0 /* to wonder why, */
335 fmr f3,f0 /* ours is but to */
336 fmr f4,f0 /* do or die! */
337 fmr f5,f0
338 fmr f6,f0
339 fmr f7,f0
340 fmr f8,f0
341 fmr f9,f0
342 fmr f10,f0
343 fmr f11,f0
344 fmr f12,f0
345 fmr f13,f0
346 fmr f14,f0
347 fmr f15,f0
348 fmr f16,f0
349 fmr f17,f0
350 fmr f18,f0
351 fmr f19,f0
352 fmr f20,f0
353 fmr f21,f0
354 fmr f22,f0
355 fmr f23,f0
356 fmr f24,f0
357 fmr f25,f0
358 fmr f26,f0
359 fmr f27,f0
360 fmr f28,f0
361 fmr f29,f0
362 fmr f30,f0
363 fmr f31,f0
364
365 li r0, MSR_VM_OFF ; Turn off floating point
366 mtmsr r0
367 isync
368
369 noFloat: rlwinm. r0,r17,0,pfAltivecb,pfAltivecb ; See if there is Altivec
370 beq- noVector ; Nope...
371
372 li r0,0 ; Clear out a register
373
374 lis r7,hi16(MSR_VEC_ON) ; Get real mode MSR + Altivec
375 ori r7,r7,lo16(MSR_VM_OFF) ; Get real mode MSR + Altivec
376 mtmsr r7 ; Set the real mode SRR */
377 isync ; Make sure it has happened
378
379 lis r5,hi16(EXT(QNaNbarbarian)) ; Altivec initializer
380 ori r5,r5,lo16(EXT(QNaNbarbarian)) ; Altivec initializer
381
382 mtspr vrsave,r0 ; Set that no VRs are used yet */
383
384 vspltish v1,1 ; Turn on the non-Java bit and saturate
385 vspltisw v0,1 ; Turn on the saturate bit
386 vxor v1,v1,v0 ; Turn off saturate and leave non-Java set
387 lvx v0,br0,r5 ; Initialize VR0
388 mtvscr v1 ; Clear the vector status register
389 vor v2,v0,v0 ; Copy into the next register
390 vor v1,v0,v0 ; Copy into the next register
391 vor v3,v0,v0 ; Copy into the next register
392 vor v4,v0,v0 ; Copy into the next register
393 vor v5,v0,v0 ; Copy into the next register
394 vor v6,v0,v0 ; Copy into the next register
395 vor v7,v0,v0 ; Copy into the next register
396 vor v8,v0,v0 ; Copy into the next register
397 vor v9,v0,v0 ; Copy into the next register
398 vor v10,v0,v0 ; Copy into the next register
399 vor v11,v0,v0 ; Copy into the next register
400 vor v12,v0,v0 ; Copy into the next register
401 vor v13,v0,v0 ; Copy into the next register
402 vor v14,v0,v0 ; Copy into the next register
403 vor v15,v0,v0 ; Copy into the next register
404 vor v16,v0,v0 ; Copy into the next register
405 vor v17,v0,v0 ; Copy into the next register
406 vor v18,v0,v0 ; Copy into the next register
407 vor v19,v0,v0 ; Copy into the next register
408 vor v20,v0,v0 ; Copy into the next register
409 vor v21,v0,v0 ; Copy into the next register
410 vor v22,v0,v0 ; Copy into the next register
411 vor v23,v0,v0 ; Copy into the next register
412 vor v24,v0,v0 ; Copy into the next register
413 vor v25,v0,v0 ; Copy into the next register
414 vor v26,v0,v0 ; Copy into the next register
415 vor v27,v0,v0 ; Copy into the next register
416 vor v28,v0,v0 ; Copy into the next register
417 vor v29,v0,v0 ; Copy into the next register
418 vor v30,v0,v0 ; Copy into the next register
419 vor v31,v0,v0 ; Copy into the next register
420
421 li r0, MSR_VM_OFF ; Turn off vectors
422 mtmsr r0
423 isync
424
425 noVector: rlwinm. r0,r17,0,pfSMPcapb,pfSMPcapb ; See if we can do SMP
426 beq- noSMP ; Nope...
427
428 lhz r13,PP_CPU_NUMBER(r30) ; Get the CPU number
429 mtspr pir,r13 ; Set the PIR
430
431 noSMP:
432
433 bl EXT(cacheInit) ; Initializes all caches (including the TLB)
434
435 rlwinm. r0,r17,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
436 beq++ isnot64 ; Skip following if not 64-bit...
437
438 mfmsr r29 ; Get the MSR
439 rlwinm r29,r29,0,0,31 ; Make sure that 64-bit mode is off
440 mtmsrd r29 ; Set it
441 isync ; Make sure
442
443 isnot64: bf bootCPU,callcpu
444
445 lis r29,HIGH_ADDR(EXT(intstack_top_ss)) ; move onto interrupt stack
446 ori r29,r29,LOW_ADDR(EXT(intstack_top_ss))
447 lwz r29,0(r29)
448
449 li r28,0
450 stw r28,FM_BACKPTR(r29) ; store a null frame backpointer
451
452 mr r1,r29
453 mr r3,r31 ; Restore any arguments we may have trashed
454
455 ; Note that we exit from here with translation still off
456
457 bl EXT(ppc_init) ; Jump into boot init code
458 BREAKPOINT_TRAP
459
460 callcpu:
461 lwz r29,PP_INTSTACK_TOP_SS(r31) ; move onto interrupt stack
462
463 li r28,0
464 stw r28,FM_BACKPTR(r29) ; store a null frame backpointer
465
466
467 mr r1,r29 ; move onto new stack
468 mr r3,r31 ; Restore any arguments we may have trashed
469
470 ; Note that we exit from here with translation still off
471
472 bl EXT(ppc_init_cpu) ; Jump into cpu init code
473 BREAKPOINT_TRAP ; Should never return
474
475 ;
476 ; Specific processor initialization routines
477 ;
478
479 ; 750
480
481 init750:
482 bf firstBoot, init750nb ; No init for wakeup....
483
484 mfspr r13,l2cr ; Get the L2CR
485 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
486 bne+ i750hl2 ; Yes...
487 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
488
489 i750hl2:
490 lis r14,hi16(256*1024) ; Base L2 size
491 addis r15,r13,0x3000 ; Hah... Figure this one out...
492 rlwinm r15,r15,4,30,31 ; Isolate
493 rlwinm. r8,r13,0,l2siz,l2sizf ; Was size valid?
494 slw r14,r14,r15 ; Set 256KB, 512KB, or 1MB
495 beq- init750l2none ; Not a valid setting...
496
497 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
498 stw r13,pfl2cr(r30) ; Shadow the L2CR
499 stw r14,pfl2Size(r30) ; Set the L2 size
500 b init750l2done ; Done with L2
501
502 init750l2none:
503 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No level 2 cache
504
505 init750l2done:
506 mfspr r11,hid0 ; Get the current HID0
507 stw r11,pfHID0(r30) ; Save the HID0 value
508 blr ; Return...
509
510 init750nb:
511 lwz r11,pfHID0(r30) ; Get HID0
512 sync
513 mtspr hid0,r11 ; Set the HID
514 isync
515 sync
516 blr
517
518 ; 750CX
519
520 init750CX:
521 bf firstBoot, init750 ; No init for wakeup....
522 mfspr r13,hid1 ; Get HID1
523 li r14,lo16(0xFD5F) ; Get valid
524 rlwinm r13,r13,4,28,31 ; Isolate
525 slw r14,r14,r13 ; Position
526 rlwimi r17,r14,15-pfCanNapb,pfCanNapb,pfCanNapb ; Set it
527 b init750 ; Join common...
528
529
530 ; 750FX
531
532 init750FX:
533 bf firstBoot, init750FXnb
534 mfspr r11, hid1
535 stw r11, pfHID1(r30) ; Save the HID1 value
536 b init750
537
538 init750FXnb:
539 lwz r13, pfHID0(r30) ; Get HID0
540 lwz r11, pfHID1(r30) ; Get HID1
541
542 rlwinm. r0, r11, 0, hid1ps, hid1ps ; Isolate the hid1ps bit
543 beq init750FXnb2 ; Clear BTIC if hid1ps set
544 rlwinm r13, r13, 0, btic+1, btic-1 ; Clear the BTIC bit
545
546 init750FXnb2:
547 sync
548 mtspr hid0, r13 ; Set the HID
549 isync
550 sync
551
552 rlwinm r12, r11, 0, hid1ps+1, hid1ps-1 ; Select PLL0
553 mtspr hid1, r12 ; Restore PLL config
554 mftb r13 ; Wait 5000 ticks (> 200 us)
555
556 init750FXnbloop:
557 mftb r14
558 sub r14, r14, r13
559 cmpli cr0, r14, 5000
560 ble init750FXnbloop
561 mtspr hid1, r11 ; Select the desired PLL
562 blr
563
564 ; 750FX vers 2.0 or later
565 init750FXV2:
566 bf firstBoot, init750FXV2nb ; Wake from sleep
567
568 mfspr r11, hid2
569 stw r11, pfHID2(r30) ; Save the HID2 value
570 b init750FX ; Continue with 750FX init
571
572 init750FXV2nb:
573 lwz r13, pfHID2(r30) ; Get HID2
574 rlwinm r13, r13, 0, hid2vmin+1, hid2vmin-1 ; Clear the vmin bit
575 mtspr hid2, r13 ; Restore HID2 value
576 sync ; Wait for it to be done
577 b init750FX
578
579 ; 7400
580
581 init7400: bf firstBoot,i7400nb ; Do different if not initial boot...
582 mfspr r13,l2cr ; Get the L2CR
583 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
584 bne+ i7400hl2 ; Yes...
585 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
586
587 i7400hl2: lis r14,hi16(256*1024) ; Base L2 size
588 addis r15,r13,0x3000 ; Hah... Figure this one out...
589 rlwinm r15,r15,4,30,31
590 slw r14,r14,r15 ; Set 256KB, 512KB, 1MB, or 2MB
591
592 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
593 stw r13,pfl2cr(r30) ; Shadow the L2CR
594 stw r14,pfl2Size(r30) ; Set the L2 size
595
596 mfspr r11,hid0 ; Get the current HID0
597 oris r11,r11,hi16(emcpm|eiecm) ; ?
598 mtspr hid0,r11 ; ?
599 isync
600 stw r11,pfHID0(r30) ; Save the HID0 value
601
602 mfspr r11,msscr0 ; Get the msscr0 register
603 stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
604 mfspr r11,msscr1 ; Get the msscr1 register
605 stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
606 blr ; Return...
607
608 i7400nb:
609 li r11,0
610 mtspr l2cr,r11 ; Make sure L2CR is zero
611 lwz r11,pfHID0(r30) ; Get HID0
612 sync
613 mtspr hid0,r11 ; Set the HID
614 isync
615 sync
616 lwz r11,pfMSSCR0(r30) ; Get MSSCR0
617 isync
618 sync
619 mtspr msscr0,r11 ; Set the MSSCR0
620 lwz r11,pfMSSCR1(r30) ; Get msscr1
621 isync
622 sync
623 mtspr msscr1,r11 ; Set the msscr1
624 isync
625 sync
626 blr
627
628 ; 7400 (ver 2.0 - ver 2.7)
629
630 init7400v2_7:
631 bf firstBoot, init7400
632 mfspr r13, hid0 ; Get the HID0
633 ori r13, r13, nopdstm ; ?
634 mtspr hid0, r13 ; Set the HID0
635 isync
636 sync
637 b init7400
638
639 ; 7410
640 ; Note that this is the same as 7400 except we initialize the l2cr2 register
641
642 init7410: li r13,0 ; Clear
643 mtspr 1016,r13 ; Turn off direct cache
644 b init7400 ; Join up with common....
645
646
647 ; 745X - Any 7450 family processor
648
649 init745X:
650 bf firstBoot,init745Xnb ; Do different if not initial boot...
651
652 mfspr r13,l2cr ; Get the L2CR
653 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
654 bne+ init745Xhl2 ; Yes...
655 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
656
657 init745Xhl2:
658 mfpvr r14 ; Get processor version
659 rlwinm r14,r14,16,16,31 ; Isolate processor version
660 cmpli cr0, r14, PROCESSOR_VERSION_7457 ; Test for 7457 or
661 cmpli cr1, r14, PROCESSOR_VERSION_7447A ; 7447A
662 cror cr0_eq, cr1_eq, cr0_eq
663 lis r14,hi16(512*1024) ; 512KB L2
664 beq init745Xhl2_2
665
666 lis r14,hi16(256*1024) ; Base L2 size
667 rlwinm r15,r13,22,12,13 ; Convert to 256k, 512k, or 768k
668 add r14,r14,r15 ; Add in minimum
669
670 init745Xhl2_2:
671 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
672 stw r13,pfl2cr(r30) ; Shadow the L2CR
673 stw r14,pfl2Size(r30) ; Set the L2 size
674
675 ; Take care of level 3 cache
676
677 mfspr r13,l3cr ; Get the L3CR
678 rlwinm. r0,r13,0,l3e,l3e ; Any L3?
679 bne+ init745Xhl3 ; Yes...
680 rlwinm r17,r17,0,pfL3b+1,pfL3b-1 ; No L3, turn off feature
681
682 init745Xhl3: cmplwi cr0,r13,0 ; No L3 if L3CR is zero
683 beq- init745Xnone ; Go turn off the features...
684 lis r14,hi16(1024*1024) ; Base L3 size
685 rlwinm r15,r13,4,31,31 ; Get size multiplier
686 slw r14,r14,r15 ; Set 1 or 2MB
687
688 stw r13,pfl3crOriginal(r30) ; Shadow the L3CR
689 stw r13,pfl3cr(r30) ; Shadow the L3CR
690 stw r14,pfl3Size(r30) ; Set the L3 size
691 b init745Xfin ; Return....
692
693 init745Xnone:
694 rlwinm r17,r17,0,pfL3fab+1,pfL3b-1 ; No 3rd level cache or assist
695 rlwinm r11,r17,pfWillNapb-pfCanNapb,pfCanNapb,pfCanNapb ; Set pfCanNap if pfWillNap is set
696 or r17,r17,r11
697
698 init745Xfin:
699 rlwinm r17,r17,0,pfWillNapb+1,pfWillNapb-1 ; Make sure pfWillNap is not set
700
701 mfspr r11,hid0 ; Get the current HID0
702 stw r11,pfHID0(r30) ; Save the HID0 value
703 mfspr r11,hid1 ; Get the current HID1
704 stw r11,pfHID1(r30) ; Save the HID1 value
705 mfspr r11,msscr0 ; Get the msscr0 register
706 stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
707 mfspr r11,msscr1 ; Get the msscr1 register
708 stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
709 mfspr r11,ictrl ; Get the ictrl register
710 stw r11,pfICTRL(r30) ; Save the ICTRL value
711 mfspr r11,ldstcr ; Get the ldstcr register
712 stw r11,pfLDSTCR(r30) ; Save the LDSTCR value
713 mfspr r11,ldstdb ; Get the ldstdb register
714 stw r11,pfLDSTDB(r30) ; Save the LDSTDB value
715 mfspr r11,pir ; Get the pir register
716 stw r11,pfBootConfig(r30) ; Save the BootConfig value
717 blr ; Return....
718
719
720 init745Xnb: lwz r11,pfHID0(r30) ; Get HID0
721 sync
722 mtspr hid0,r11 ; Set the HID
723 isync
724 lwz r11,pfHID1(r30) ; Get HID1
725 sync
726 mtspr hid1,r11 ; Set the HID
727 isync
728 lwz r11,pfMSSCR0(r30) ; Get MSSCR0
729 sync
730 mtspr msscr0,r11 ; Set the MSSCR0
731 isync
732 sync
733 lwz r11,pfICTRL(r30) ; Get ICTRL
734 sync
735 mtspr ictrl,r11 ; Set the ICTRL
736 isync
737 sync
738 lwz r11,pfLDSTCR(r30) ; Get LDSTCR
739 sync
740 mtspr ldstcr,r11 ; Set the LDSTCR
741 isync
742 sync
743 lwz r11,pfLDSTDB(r30) ; Get LDSTDB
744 sync
745 mtspr ldstdb,r11 ; Set the LDSTDB
746 isync
747 sync
748 blr
749
750 ; 7450 - Specific
751
752 init7450:
753 bf firstBoot, init745X ; Not boot, use standard init
754
755 mfspr r13, pir ; Get BootConfig from PIR
756 rlwinm. r14, r13, 0, 20, 23 ; Is the pdet value zero
757 bne init7450done ; No, done for now
758
759 ori r13, r13, 0x0400 ; Force pdet value to 4
760 mtspr pir, r13 ; Write back the BootConfig
761
762 init7450done:
763 b init745X ; Continue with standard init
764
765
766 init970:
767 li r20,0 ; Clear this
768 mtspr hior,r20 ; Make sure that 0 is interrupt prefix
769 bf firstBoot,init970nb ; No init for wakeup or second processor....
770
771
772 mfspr r11,hid0 ; Get original hid0
773 std r11,pfHID0(r30) ; Save original
774 mfspr r11,hid1 ; Get original hid1
775 std r11,pfHID1(r30) ; Save original
776 mfspr r11,hid4 ; Get original hid4
777 std r11,pfHID4(r30) ; Save original
778 mfspr r11,hid5 ; Get original hid5
779 std r11,pfHID5(r30) ; Save original
780
781 lis r0, hi16(dnapm) ; Create a mask for the dnap bit
782 sldi r0, r0, 32 ; Shift to the top half
783 ld r11,pfHID0(r30) ; Load the hid0 value
784 andc r11, r11, r0 ; Clear the dnap bit
785 isync
786 mtspr hid0,r11 ; Stuff it
787 mfspr r11,hid0 ; Get it
788 mfspr r11,hid0 ; Get it
789 mfspr r11,hid0 ; Get it
790 mfspr r11,hid0 ; Get it
791 mfspr r11,hid0 ; Get it
792 mfspr r11,hid0 ; Get it
793 isync
794
795 ;
796 ; We can not query or change the L2 size. We will just
797 ; phoney up a L2CR to make sysctl "happy" and set the
798 ; L2 size to 512K.
799 ;
800
801 lis r0,0x8000 ; Synthesize a "valid" but non-existant L2CR
802 stw r0,pfl2crOriginal(r30) ; Set a dummy L2CR
803 stw r0,pfl2cr(r30) ; Set a dummy L2CR
804 lis r0,8 ; Get 512K
805 stw r0,pfl2Size(r30) ; Set the L2 size
806
807 blr
808
809 ;
810 ; Start up code for second processor or wake up from sleep
811 ;
812
813 init970nb:
814 lis r0, hi16(dnapm) ; Create a mask for the dnap bit
815 sldi r0, r0, 32 ; Shift to the top half
816 ld r11,pfHID0(r30) ; Load the hid0 value
817 andc r11, r11, r0 ; Clear the dnap bit
818 isync
819 mtspr hid0,r11 ; Stuff it
820 mfspr r11,hid0 ; Get it
821 mfspr r11,hid0 ; Get it
822 mfspr r11,hid0 ; Get it
823 mfspr r11,hid0 ; Get it
824 mfspr r11,hid0 ; Get it
825 mfspr r11,hid0 ; Get it
826 isync
827
828 ld r11,pfHID1(r30) ; Get it
829 isync
830 mtspr hid1,r11 ; Stick it
831 mtspr hid1,r11 ; Stick it again
832 isync
833
834 ld r11,pfHID4(r30) ; Get it
835 sync
836 mtspr hid4,r11 ; Stick it
837 isync
838
839 ld r11,pfHID5(r30) ; Get it
840 mtspr hid5,r11 ; Set it
841 isync
842 blr ; Leave...
843
844
845 ; Unsupported Processors
846 initUnsupported:
847 mtlr r2 ; Restore the return address
848 blr ; Return to the booter
849
850
851 ;
852 ; Processor to feature table
853
854 ; .align 2 - Always on word boundary
855 ; .long ptFilter - Mask of significant bits in the Version/Revision code
856 ; - NOTE: Always order from most restrictive to least restrictive matching
857 ; .short ptVersion - Version code from PVR. Always start with 0 which is default
858 ; .short ptRevision - Revision code from PVR. A zero value denotes the generic attributes if not specific
859 ; .long ptFeatures - Available features
860 ; .long ptCPUCap - Default value for _cpu_capabilities
861 ; .long ptPwrModes - Available power management features
862 ; .long ptPatch - Patch features
863 ; .long ptInitRout - Initilization routine. Can modify any of the other attributes.
864 ; .long ptRptdProc - Processor type reported
865 ; .long ptLineSize - Level 1 cache line size
866 ; .long ptl1iSize - Level 1 instruction cache size
867 ; .long ptl1dSize - Level 1 data cache size
868 ; .long ptPTEG - Size of PTEG
869 ; .long ptMaxVAddr - Maximum effective address
870 ; .long ptMaxPAddr - Maximum physical address
871 ;
872
873 .align 2
874 processor_types:
875
876 ; 750CX (ver 2.x)
877
878 .align 2
879 .long 0xFFFF0F00 ; 2.x vers
880 .short PROCESSOR_VERSION_750
881 .short 0x0200
882 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2
883 .long kCache32 | kHasGraphicsOps | kHasStfiwx
884 .long 0
885 .long PatchExt32
886 .long init750CX
887 .long CPU_SUBTYPE_POWERPC_750
888 .long 32
889 .long 32*1024
890 .long 32*1024
891 .long 64
892 .long 52
893 .long 32
894
895 ; 750 (generic)
896
897 .align 2
898 .long 0xFFFF0000 ; All revisions
899 .short PROCESSOR_VERSION_750
900 .short 0
901 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2
902 .long kCache32 | kHasGraphicsOps | kHasStfiwx
903 .long 0
904 .long PatchExt32
905 .long init750
906 .long CPU_SUBTYPE_POWERPC_750
907 .long 32
908 .long 32*1024
909 .long 32*1024
910 .long 64
911 .long 52
912 .long 32
913
914 ; 750FX (ver 1.x)
915
916 .align 2
917 .long 0xFFFF0F00 ; 1.x vers
918 .short PROCESSOR_VERSION_750FX
919 .short 0x0100
920 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pf32Byte | pfL2
921 .long kCache32 | kHasGraphicsOps | kHasStfiwx
922 .long pmDualPLL
923 .long PatchExt32
924 .long init750FX
925 .long CPU_SUBTYPE_POWERPC_750
926 .long 32
927 .long 32*1024
928 .long 32*1024
929 .long 64
930 .long 52
931 .long 32
932
933 ; 750FX (generic)
934
935 .align 2
936 .long 0xFFFF0000 ; All revisions
937 .short PROCESSOR_VERSION_750FX
938 .short 0
939 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pf32Byte | pfL2
940 .long kCache32 | kHasGraphicsOps | kHasStfiwx
941 .long pmDualPLL | pmDPLLVmin
942 .long PatchExt32
943 .long init750FXV2
944 .long CPU_SUBTYPE_POWERPC_750
945 .long 32
946 .long 32*1024
947 .long 32*1024
948 .long 64
949 .long 52
950 .long 32
951
952 ; 7400 (ver 2.0 - ver 2.7)
953
954 .align 2
955 .long 0xFFFFFFF8 ; ver 2.0 - 2.7
956 .short PROCESSOR_VERSION_7400
957 .short 0x0200
958 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
959 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
960 .long 0
961 .long PatchExt32
962 .long init7400v2_7
963 .long CPU_SUBTYPE_POWERPC_7400
964 .long 32
965 .long 32*1024
966 .long 32*1024
967 .long 64
968 .long 52
969 .long 32
970
971 ; 7400 (generic)
972
973 .align 2
974 .long 0xFFFF0000 ; All revisions
975 .short PROCESSOR_VERSION_7400
976 .short 0
977 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
978 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
979 .long 0
980 .long PatchExt32
981 .long init7400
982 .long CPU_SUBTYPE_POWERPC_7400
983 .long 32
984 .long 32*1024
985 .long 32*1024
986 .long 64
987 .long 52
988 .long 36
989
990 ; 7410 (ver 1.1)
991
992 .align 2
993 .long 0xFFFFFFFF ; Exact match
994 .short PROCESSOR_VERSION_7400
995 .short 0x1101
996 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
997 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
998 .long 0
999 .long PatchExt32
1000 .long init7410
1001 .long CPU_SUBTYPE_POWERPC_7400
1002 .long 32
1003 .long 32*1024
1004 .long 32*1024
1005 .long 64
1006 .long 52
1007 .long 36
1008
1009 ; 7410 (generic)
1010
1011 .align 2
1012 .long 0xFFFF0000 ; All other revisions
1013 .short PROCESSOR_VERSION_7410
1014 .short 0
1015 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1016 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1017 .long 0
1018 .long PatchExt32
1019 .long init7410
1020 .long CPU_SUBTYPE_POWERPC_7400
1021 .long 32
1022 .long 32*1024
1023 .long 32*1024
1024 .long 64
1025 .long 52
1026 .long 36
1027
1028 ; 7450 (ver 1.xx)
1029
1030 .align 2
1031 .long 0xFFFFFF00 ; Just revisions 1.xx
1032 .short PROCESSOR_VERSION_7450
1033 .short 0x0100
1034 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1035 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1036 .long 0
1037 .long PatchExt32
1038 .long init7450
1039 .long CPU_SUBTYPE_POWERPC_7450
1040 .long 32
1041 .long 32*1024
1042 .long 32*1024
1043 .long 64
1044 .long 52
1045 .long 36
1046
1047 ; 7450 (2.0)
1048
1049 .align 2
1050 .long 0xFFFFFFFF ; Just revision 2.0
1051 .short PROCESSOR_VERSION_7450
1052 .short 0x0200
1053 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1054 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1055 .long 0
1056 .long PatchExt32
1057 .long init7450
1058 .long CPU_SUBTYPE_POWERPC_7450
1059 .long 32
1060 .long 32*1024
1061 .long 32*1024
1062 .long 64
1063 .long 52
1064 .long 36
1065
1066 ; 7450 (2.1)
1067
1068 .align 2
1069 .long 0xFFFF0000 ; All other revisions
1070 .short PROCESSOR_VERSION_7450
1071 .short 0
1072 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1073 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1074 .long 0
1075 .long PatchExt32
1076 .long init7450
1077 .long CPU_SUBTYPE_POWERPC_7450
1078 .long 32
1079 .long 32*1024
1080 .long 32*1024
1081 .long 64
1082 .long 52
1083 .long 36
1084
1085 ; 7455 (1.xx) Just like 7450 2.0
1086
1087 .align 2
1088 .long 0xFFFFFF00 ; Just revisions 1.xx
1089 .short PROCESSOR_VERSION_7455
1090 .short 0x0100
1091 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1092 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1093 .long 0
1094 .long PatchExt32
1095 .long init745X
1096 .long CPU_SUBTYPE_POWERPC_7450
1097 .long 32
1098 .long 32*1024
1099 .long 32*1024
1100 .long 64
1101 .long 52
1102 .long 36
1103
1104 ; 7455 (2.0)
1105
1106 .align 2
1107 .long 0xFFFFFFFF ; Just revision 2.0
1108 .short PROCESSOR_VERSION_7455
1109 .short 0x0200
1110 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1111 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1112 .long 0
1113 .long PatchExt32
1114 .long init745X
1115 .long CPU_SUBTYPE_POWERPC_7450
1116 .long 32
1117 .long 32*1024
1118 .long 32*1024
1119 .long 64
1120 .long 52
1121 .long 36
1122
1123 ; 7455 (2.1)
1124
1125 .align 2
1126 .long 0xFFFF0000 ; All other revisions
1127 .short PROCESSOR_VERSION_7455
1128 .short 0
1129 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1130 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1131 .long 0
1132 .long PatchExt32
1133 .long init745X
1134 .long CPU_SUBTYPE_POWERPC_7450
1135 .long 32
1136 .long 32*1024
1137 .long 32*1024
1138 .long 64
1139 .long 52
1140 .long 36
1141
1142 ; 7457
1143
1144 .align 2
1145 .long 0xFFFF0000 ; All revisions
1146 .short PROCESSOR_VERSION_7457
1147 .short 0
1148 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1149 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1150 .long 0
1151 .long PatchExt32
1152 .long init745X
1153 .long CPU_SUBTYPE_POWERPC_7450
1154 .long 32
1155 .long 32*1024
1156 .long 32*1024
1157 .long 64
1158 .long 52
1159 .long 36
1160
1161 ; 7447A
1162
1163 .align 2
1164 .long 0xFFFF0000 ; All revisions
1165 .short PROCESSOR_VERSION_7447A
1166 .short 0
1167 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1168 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1169 .long pmDFS
1170 .long PatchExt32
1171 .long init745X
1172 .long CPU_SUBTYPE_POWERPC_7450
1173 .long 32
1174 .long 32*1024
1175 .long 32*1024
1176 .long 64
1177 .long 52
1178 .long 36
1179
1180 ; 970
1181
1182 .align 2
1183 .long 0xFFFF0000 ; All versions so far
1184 .short PROCESSOR_VERSION_970
1185 .short 0
1186 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pf128Byte | pf64Bit | pfL2 | pfSCOMFixUp
1187 .long kHasAltivec | k64Bit | kCache128 | kDataStreamsAvailable | kDcbtStreamsRecommended | kDcbtStreamsAvailable | kHasGraphicsOps | kHasStfiwx | kHasFsqrt
1188 .long 0
1189 .long PatchLwsync
1190 .long init970
1191 .long CPU_SUBTYPE_POWERPC_970
1192 .long 128
1193 .long 64*1024
1194 .long 32*1024
1195 .long 128
1196 .long 65
1197 .long 42
1198
1199 ; 970FX
1200
1201 .align 2
1202 .long 0xFFFF0000 ; All versions so far
1203 .short PROCESSOR_VERSION_970FX
1204 .short 0
1205 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pf128Byte | pf64Bit | pfL2
1206 .long kHasAltivec | k64Bit | kCache128 | kDataStreamsAvailable | kDcbtStreamsRecommended | kDcbtStreamsAvailable | kHasGraphicsOps | kHasStfiwx | kHasFsqrt
1207 .long pmPowerTune
1208 .long PatchLwsync
1209 .long init970
1210 .long CPU_SUBTYPE_POWERPC_970
1211 .long 128
1212 .long 64*1024
1213 .long 32*1024
1214 .long 128
1215 .long 65
1216 .long 42
1217
1218 ; All other processors are not supported
1219
1220 .align 2
1221 .long 0x00000000 ; Matches everything
1222 .short 0
1223 .short 0
1224 .long pfFloat | pf32Byte
1225 .long kCache32 | kHasGraphicsOps | kHasStfiwx
1226 .long 0
1227 .long PatchExt32
1228 .long initUnsupported
1229 .long CPU_SUBTYPE_POWERPC_ALL
1230 .long 32
1231 .long 32*1024
1232 .long 32*1024
1233 .long 64
1234 .long 52
1235 .long 32
1236
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