osfmk/ppc/commpage/cacheflush.s

   1 /*
   2  * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28
  29 #define ASSEMBLER
  30 #include <sys/appleapiopts.h>
  31 #include <ppc/asm.h>                                    // EXT, LEXT
  32 #include <machine/cpu_capabilities.h>
  33 #include <machine/commpage.h>
  34
  35         .text
  36         .align  2
  37
  38
  39 // *********************************************
  40 // * C O M M P A G E _ F L U S H _ D C A C H E *
  41 // *********************************************
  42 //
  43 // Note that this routine is called both in 32 and 64-bit mode.
  44 //
  45 //      r3 = ptr to 1st byte to flush
  46 //      r4 = length to flush (may be 0)
  47
  48 commpage_flush_dcache:
  49         mr.     r4,r4           // test length for 0 in mode-independent way
  50         lhz             r5,_COMM_PAGE_CACHE_LINESIZE(0)
  51         subi    r9,r5,1                 // get (linesize-1)
  52         and             r0,r3,r9                // get offset within line of 1st byte
  53         add             r4,r4,r0                // adjust length so we flush them all
  54         add             r4,r4,r9                // round length up...
  55         andc    r4,r4,r9                // ...to multiple of cache lines
  56         beqlr--                                 // length was 0, so exit
  57 1:
  58         sub.    r4,r4,r5                // more to go?
  59         dcbf    0,r3                    // flush another line
  60         add             r3,r3,r5
  61         bne             1b
  62         sync                                    // make sure lines are flushed before we return
  63         blr
  64
  65         COMMPAGE_DESCRIPTOR(commpage_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,0,0,kCommPageBoth)
  66
  67
  68 // *********************************************
  69 // * C O M M P A G E _ F L U S H _ I C A C H E *
  70 // *********************************************
  71 //
  72 // Note that this routine is called both in 32 and 64-bit mode.
  73 //
  74 //      r3 = ptr to 1st byte to flush
  75 //      r4 = length to flush (may be 0)
  76
  77 commpage_flush_icache:
  78         mr.     r4,r4           // test length for 0 in mode-independent way
  79         lhz             r5,_COMM_PAGE_CACHE_LINESIZE(0)
  80         subi    r9,r5,1                 // get (linesize-1)
  81         and             r0,r3,r9                // get offset within line of 1st byte
  82         add             r4,r4,r0                // adjust length so we flush them all
  83         mr              r7,r3                   // copy ptr
  84         add             r4,r4,r9                // round length up...
  85         andc    r4,r4,r9                // ...to multiple of cache lines
  86         mr              r6,r4                   // copy length
  87         beqlr--                                 // length was 0, so exit
  88 1:
  89         sub.    r4,r4,r5                // more to go?
  90         dcbf    0,r3                    // flush another line
  91         add             r3,r3,r5
  92         bne             1b
  93         sync                                    // make sure lines are flushed
  94 2:
  95         sub.    r6,r6,r5                // more to go?
  96         icbi    0,r7
  97         add             r7,r7,r5
  98         bne             2b
  99
 100         // The following sync is only needed on MP machines, probably only on
 101         // 7400-family MP machines.  But because we're not certain of this, and
 102         // this isn't a speed critical routine, we are conservative and always sync.
 103
 104         sync                                    // wait until other processors see the icbi's
 105         isync                                   // make sure we haven't prefetched old instructions
 106
 107         blr
 108
 109         COMMPAGE_DESCRIPTOR(commpage_flush_icache,_COMM_PAGE_FLUSH_ICACHE,0,0,kCommPageBoth)
 110
 111