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[apple/xnu.git] / osfmk / ppc / Firmware.s
1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * Copyright (c) 1999-2003 Apple Computer, Inc. All Rights Reserved.
7 *
8 * This file contains Original Code and/or Modifications of Original Code
9 * as defined in and that are subject to the Apple Public Source License
10 * Version 2.0 (the 'License'). You may not use this file except in
11 * compliance with the License. Please obtain a copy of the License at
12 * http://www.opensource.apple.com/apsl/ and read it before using this
13 * file.
14 *
15 * The Original Code and all software distributed under the License are
16 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
17 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
18 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
20 * Please see the License for the specific language governing rights and
21 * limitations under the License.
22 *
23 * @APPLE_LICENSE_HEADER_END@
24 */
25 /*
26 * @OSF_FREE_COPYRIGHT@
27 */
28 /*
29 * @APPLE_FREE_COPYRIGHT@
30 */
31
32 /*
33 Firmware.s
34
35 Handle things that should be treated as an extension of the hardware
36
37 Lovingly crafted by Bill Angell using traditional methods and only natural or recycled materials.
38 No animal products are used other than rendered otter bile and deep fried pork lard.
39
40 */
41
42 #include <cpus.h>
43 #include <ppc/asm.h>
44 #include <ppc/proc_reg.h>
45 #include <ppc/spec_reg.h>
46 #include <ppc/POWERMAC/mp/MPPlugIn.h>
47 #include <ppc/exception.h>
48 #include <mach/machine/vm_param.h>
49 #include <assym.s>
50
51
52 /*
53 * Here we generate the table of supported firmware calls
54 */
55
56
57
58 .data
59 .align 5 /* Line up on cache line */
60
61 .globl EXT(FWtable)
62
63 EXT(FWtable):
64
65 .globl CutTrace /* Let everyone know 'bout it */
66 .set CutTrace,(.-EXT(FWtable))/4|0x80000000 /* Call number for CutTrace */
67 .long callUnimp /* This was already handled in lowmem_vectors */
68
69 #include <ppc/FirmwareCalls.h>
70
71 .set EXT(FirmwareCnt), (.-EXT(FWtable))/4 /* Get the top number */
72
73 .text
74
75 #define SIMPLESCC 1
76 #define NOTQUITEASSIMPLE 1
77 /*
78 * This routine handles the firmware call routine. It must be entered with IR and DR off,
79 * interruptions disabled, and in supervisor state.
80 *
81 * When we enter, we expect R0 to have call number, and LR
82 * to point to the return. Also, all registers saved in savearea in R13.
83 * R3 is as passed in by the user. All others must be gotten from the save area
84 */
85
86 ENTRY(FirmwareCall, TAG_NO_FRAME_USED)
87
88 rlwinm r1,r0,2,1,29 /* Clear out bit 0 and multiply by 4 */
89 lis r12,HIGH_ADDR(EXT(FWtable)) /* Get the high part of the firmware call table */
90 cmplwi r1,EXT(FirmwareCnt)*4 /* Is it a valid firmware call number */
91 mflr r11 /* Save the return */
92 ori r12,r12,LOW_ADDR(EXT(FWtable)) /* Now the low part */
93 ble+ goodCall /* Yeah, it is... */
94
95 li r3,T_SYSTEM_CALL /* Tell the vector handler that we know nothing */
96 blr /* Return for errors... */
97
98 goodCall: mfsprg r10,0 /* Make sure about the per_proc block */
99 lwzx r1,r1,r12 /* Pick up the address of the routine */
100 lwz r4,saver4(r13) /* Pass in caller's R4 */
101 lwz r5,saver5(r13) /* Pass in caller's R5 */
102 rlwinm. r1,r1,0,0,29 /* Make sure the flag bits are clear */
103 stw r11,PP_TEMPWORK1(r10) /* Save our return point */
104
105 mtlr r1 /* Put it in the LR */
106 beq- callUnimp /* This one was unimplimented... */
107
108 blrl /* Call the routine... */
109
110 mfsprg r10,0 /* Make sure about the per_proc again */
111 stw r3,saver3(r13) /* Pass back the return code to caller */
112 lwz r11,PP_TEMPWORK1(r10) /* Get our return point */
113 li r3,T_IN_VAIN /* Tell the vector handler that we took care of it */
114 mtlr r11 /* Set the return */
115 blr /* Bye, dudes... */
116
117 callUnimp: lwz r11,PP_TEMPWORK1(r10) /* Restore the return address */
118 li r3,T_SYSTEM_CALL /* Tell the vector handler that we know nothing */
119 mtlr r11 /* Restore the LR */
120 blr /* Return for errors... */
121
122 /*
123 * This routine is used to store using a real address. It stores parmeter1 at parameter2.
124 */
125
126 ENTRY(StoreReal, TAG_NO_FRAME_USED)
127
128 lis r0,HIGH_ADDR(StoreRealCall) /* Get the top part of the SC number */
129 ori r0,r0,LOW_ADDR(StoreRealCall) /* and the bottom part */
130 sc /* Do it to it */
131 blr /* Bye bye, Birdie... */
132
133 ENTRY(StoreRealLL, TAG_NO_FRAME_USED)
134
135 stw r3,0(r4) /* Store the word */
136 blr /* Leave... */
137
138 /*
139 * This routine is used to clear a range of physical pages.
140 */
141
142 ENTRY(ClearReal, TAG_NO_FRAME_USED)
143
144 lis r0,HIGH_ADDR(ClearRealCall) /* Get the top part of the SC number */
145 ori r0,r0,LOW_ADDR(ClearRealCall) /* and the bottom part */
146 sc /* Do it to it */
147 blr /* Bye bye, Birdie... */
148
149 ENTRY(ClearRealLL, TAG_NO_FRAME_USED)
150
151 /*
152 * We take the first parameter as a physical address. The second is the length in bytes.
153 * Being crazy, I'll round the address down, and the length up. We could end up clearing
154 * an extra page at the start and one at the end, but we don't really care. If someone
155 * is stupid enough to give me unaligned addresses and lengths, I am just arrogant enough
156 * to take them at their word and to hell with them.
157 */
158
159 neg r5,r3 /* Negate the address */
160 addi r4,r4,4095 /* Round length up */
161 rlwinm r5,r5,0,20,31 /* Save extra length */
162 rlwinm r3,r3,0,0,19 /* Round the page on down */
163 add r4,r4,r5 /* Add up all extra lengths */
164 li r6,32 /* Get a displacement */
165 rlwinm r4,r4,0,0,19 /* Round the length back down */
166
167 clrloop: subi r4,r4,32 /* Back off a cache line */
168 dcbz 0,r3 /* Do the even line */
169 sub. r4,r4,r6 /* Back off a second time (we only do this to generate a CR */
170 dcbz r6,r3 /* Clear the even line */
171 addi r3,r3,64 /* Move up to every other line */
172 bgt+ clrloop /* Go until we've done it all... */
173
174 blr /* Leave... */
175 /*
176 * This routine will read in 32 byte of real storage.
177 */
178
179 ENTRY(ReadReal, TAG_NO_FRAME_USED)
180
181 mfmsr r0 /* Get the MSR */
182 rlwinm r5,r0,0,28,26 /* Clear DR bit */
183 rlwinm r5,r5,0,17,15 /* Clear EE bit */
184 mtmsr r5 /* Disable EE and DR */
185 isync /* Just make sure about it */
186
187 lwz r5,0(r3) /* Get word 0 */
188 lwz r6,4(r3) /* Get word 1 */
189 lwz r7,8(r3) /* Get word 2 */
190 lwz r8,12(r3) /* Get word 3 */
191 rlwinm r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
192 lwz r9,16(r3) /* Get word 4 */
193 lwz r10,20(r3) /* Get word 5 */
194 rlwinm r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
195 lwz r11,24(r3) /* Get word 6 */
196 lwz r12,28(r3) /* Get word 7 */
197
198 mtmsr r0 /* Restore original machine state */
199 isync /* Insure goodness */
200
201 stw r5,0(r4) /* Set word 0 */
202 stw r6,4(r4) /* Set word 1 */
203 stw r7,8(r4) /* Set word 2 */
204 stw r8,12(r4) /* Set word 3 */
205 stw r9,16(r4) /* Set word 4 */
206 stw r10,20(r4) /* Set word 5 */
207 stw r11,24(r4) /* Set word 6 */
208 stw r12,28(r4) /* Set word 7 */
209
210 blr
211
212
213 /*
214 * This routine is used to load all 4 DBATs.
215 */
216
217 ENTRY(LoadDBATs, TAG_NO_FRAME_USED)
218
219 lis r0,HIGH_ADDR(LoadDBATsCall) /* Top half of LoadDBATsCall firmware call number */
220 ori r0,r0,LOW_ADDR(LoadDBATsCall) /* Bottom half */
221 sc /* Do it to it */
222
223 blr /* Bye bye, Birdie... */
224
225 ENTRY(xLoadDBATsLL, TAG_NO_FRAME_USED)
226
227 lwz r4,0(r3) /* Get DBAT 0 high */
228 lwz r5,4(r3) /* Get DBAT 0 low */
229 lwz r6,8(r3) /* Get DBAT 1 high */
230 lwz r7,12(r3) /* Get DBAT 1 low */
231 lwz r8,16(r3) /* Get DBAT 2 high */
232 lwz r9,20(r3) /* Get DBAT 2 low */
233 lwz r10,24(r3) /* Get DBAT 3 high */
234 lwz r11,28(r3) /* Get DBAT 3 low */
235
236 sync /* Common decency and the state law require that you wash your hands */
237 mtdbatu 0,r4 /* Load DBAT 0 high */
238 mtdbatl 0,r5 /* Load DBAT 0 low */
239 mtdbatu 1,r6 /* Load DBAT 1 high */
240 mtdbatl 1,r7 /* Load DBAT 1 low */
241 mtdbatu 2,r8 /* Load DBAT 2 high */
242 mtdbatl 2,r9 /* Load DBAT 2 low */
243 mtdbatu 3,r10 /* Load DBAT 3 high */
244 mtdbatl 3,r11 /* Load DBAT 3 low */
245 sync /* Make sure it's done */
246 isync /* Toss out anything new */
247
248 blr /* Leave... */
249
250 /*
251 * This routine is used to load all 4 IBATs.
252 */
253
254 ENTRY(LoadIBATs, TAG_NO_FRAME_USED)
255
256 lis r0,HIGH_ADDR(LoadIBATsCall) /* Top half of LoadIBATsCall firmware call number */
257 ori r0,r0,LOW_ADDR(LoadIBATsCall) /* Bottom half */
258 sc /* Do it to it */
259 blr /* Bye bye, Birdie... */
260
261 ENTRY(xLoadIBATsLL, TAG_NO_FRAME_USED)
262
263 lwz r4,0(r3) /* Get IBAT 0 high */
264 lwz r5,4(r3) /* Get IBAT 0 low */
265 lwz r6,8(r3) /* Get IBAT 1 high */
266 lwz r7,12(r3) /* Get IBAT 1 low */
267 lwz r8,16(r3) /* Get IBAT 2 high */
268 lwz r9,20(r3) /* Get IBAT 2 low */
269 lwz r10,24(r3) /* Get IBAT 3 high */
270 lwz r11,28(r3) /* Get IBAT 3 low */
271
272 sync /* Common decency and the state law require that you wash your hands */
273 mtibatu 0,r4 /* Load IBAT 0 high */
274 mtibatl 0,r5 /* Load IBAT 0 low */
275 mtibatu 1,r6 /* Load IBAT 1 high */
276 mtibatl 1,r7 /* Load IBAT 1 low */
277 mtibatu 2,r8 /* Load IBAT 2 high */
278 mtibatl 2,r9 /* Load IBAT 2 low */
279 mtibatu 3,r10 /* Load IBAT 3 high */
280 mtibatl 3,r11 /* Load IBAT 3 low */
281 sync /* Make sure it's done */
282 isync /* Toss out anything new */
283
284 blr /* Leave... */
285
286
287 /*
288 * This is the glue to call the CutTrace firmware call
289 */
290
291 ENTRY(dbgTrace, TAG_NO_FRAME_USED)
292
293 lis r0,HIGH_ADDR(CutTrace) /* Top half of CreateFakeIO firmware call number */
294 ori r0,r0,LOW_ADDR(CutTrace) /* Bottom half */
295 sc /* Do it to it */
296 blr /* Bye bye, Birdie... */
297
298 /*
299 * This is the glue to create a fake I/O interruption
300 */
301
302 ENTRY(CreateFakeIO, TAG_NO_FRAME_USED)
303
304 lis r0,HIGH_ADDR(CreateFakeIOCall) /* Top half of CreateFakeIO firmware call number */
305 ori r0,r0,LOW_ADDR(CreateFakeIOCall) /* Bottom half */
306 sc /* Do it to it */
307 blr /* Bye bye, Birdie... */
308
309 /*
310 * This is the glue to create a fake Dec interruption
311 */
312
313 ENTRY(CreateFakeDEC, TAG_NO_FRAME_USED)
314
315 #if 0
316 mflr r4 ; (TEST/DEBUG)
317 bl EXT(ml_sense_nmi) ; (TEST/DEBUG)
318 mtlr r4 ; (TEST/DEBUG)
319 #endif
320 lis r0,HIGH_ADDR(CreateFakeDECCall) /* Top half of CreateFakeDEC firmware call number */
321 ori r0,r0,LOW_ADDR(CreateFakeDECCall) /* Bottom half */
322 sc /* Do it to it */
323 blr /* Bye bye, Birdie... */
324
325
326 /*
327 * This is the glue to create a shutdown context
328 */
329
330 ENTRY(CreateShutdownCTX, TAG_NO_FRAME_USED)
331
332 lis r0,HIGH_ADDR(CreateShutdownCTXCall) /* Top half of CreateFakeIO firmware call number */
333 ori r0,r0,LOW_ADDR(CreateShutdownCTXCall) /* Bottom half */
334 sc /* Do it to it */
335 blr /* Bye bye, Birdie... */
336
337 /*
338 * This is the glue to choke system
339 */
340
341 ENTRY(ChokeSys, TAG_NO_FRAME_USED)
342
343 lis r0,HIGH_ADDR(Choke) /* Top half of Choke firmware call number */
344 ori r0,r0,LOW_ADDR(Choke) /* Bottom half */
345 sc /* Do it to it */
346 blr /* Bye bye, Birdie... */
347
348 /*
349 * Used to initialize the SCC for debugging output
350 */
351
352
353 ENTRY(fwSCCinit, TAG_NO_FRAME_USED)
354
355 mfmsr r8 /* Save the MSR */
356 mr. r3,r3 /* See if printer or modem */
357 rlwinm r12,r8,0,28,25 /* Turn off translation */
358 lis r10,0xF301 /* Set the top part */
359 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
360 #if 0
361 mtmsr r12 /* Smash the MSR */
362 isync /* Make it clean */
363 #endif
364
365 ori r10,r10,0x2000 /* Assume the printer (this is the normal one) */
366 beq+ fwSCCprnt /* It sure are... */
367 ori r10,r10,0x0002 /* Move it over to the modem port */
368
369 fwSCCprnt: dcbf 0,r10 /* Insure it is out */
370 sync
371 eieio
372 dcbi 0,r10 /* Toss it */
373 sync
374
375
376 li r7,0x09 /* Set the register */
377 stb r7,0(r10) /* Set the register */
378 dcbf 0,r10 /* Force it out */
379 sync /* Make sure it's out there */
380 dcbi 0,r10
381 eieio
382
383 li r7,0x80 /* Reset channel A */
384 stb r7,0(r10) /* Set the register */
385 dcbf 0,r10 /* Force it out */
386 sync /* Make sure it's out there */
387 dcbi 0,r10
388 eieio
389
390 li r7,0x04 /* Set the register */
391 stb r7,0(r10) /* Set the register */
392 dcbf 0,r10 /* Force it out */
393 sync /* Make sure it's out there */
394 dcbi 0,r10
395 eieio
396
397 li r7,0x44 /* x16 clock, 1 stop bit */
398 stb r7,0(r10) /* Set the register */
399 dcbf 0,r10 /* Force it out */
400 sync /* Make sure it's out there */
401 dcbi 0,r10
402 eieio
403
404 li r7,0x03 /* Set the register */
405 stb r7,0(r10) /* Set the register */
406 dcbf 0,r10 /* Force it out */
407 sync /* Make sure it's out there */
408 dcbi 0,r10
409 eieio
410
411 li r7,0xC0 /* 8 bits per char */
412 stb r7,0(r10) /* Set the register */
413 dcbf 0,r10 /* Force it out */
414 sync /* Make sure it's out there */
415 dcbi 0,r10
416 eieio
417
418 li r7,0x05 /* Set the register */
419 stb r7,0(r10) /* Set the register */
420 dcbf 0,r10 /* Force it out */
421 sync /* Make sure it's out there */
422 dcbi 0,r10
423 eieio
424
425 li r7,0xE2 /* DTR mode, 8bit/char */
426 stb r7,0(r10) /* Set the register */
427 dcbf 0,r10 /* Force it out */
428 sync /* Make sure it's out there */
429 dcbi 0,r10
430 eieio
431
432 li r7,0x02 /* Set the register */
433 stb r7,0(r10) /* Set the register */
434 dcbf 0,r10 /* Force it out */
435 sync /* Make sure it's out there */
436 dcbi 0,r10
437 eieio
438
439 li r7,0x00 /* Vector 0 */
440 stb r7,0(r10) /* Set the register */
441 dcbf 0,r10 /* Force it out */
442 sync /* Make sure it's out there */
443 dcbi 0,r10
444 eieio
445
446 li r7,0x0A /* Set the register */
447 stb r7,0(r10) /* Set the register */
448 dcbf 0,r10 /* Force it out */
449 sync /* Make sure it's out there */
450 dcbi 0,r10
451 eieio
452
453 li r7,0x00 /* Clear misc controls */
454 stb r7,0(r10) /* Set the register */
455 dcbf 0,r10 /* Force it out */
456 sync /* Make sure it's out there */
457 dcbi 0,r10
458 eieio
459
460 li r7,0x0B /* Set the register */
461 stb r7,0(r10) /* Set the register */
462 dcbf 0,r10 /* Force it out */
463 sync /* Make sure it's out there */
464 dcbi 0,r10
465 eieio
466
467 li r7,0x50 /* B/R gen T/R */
468 stb r7,0(r10) /* Set the register */
469 dcbf 0,r10 /* Force it out */
470 sync /* Make sure it's out there */
471 dcbi 0,r10
472 eieio
473
474 li r7,0x0C /* Set the register */
475 stb r7,0(r10) /* Set the register */
476 dcbf 0,r10 /* Force it out */
477 sync /* Make sure it's out there */
478 dcbi 0,r10
479 eieio
480
481 li r7,0x0A /* 9600 baud low */
482 stb r7,0(r10) /* Set the register */
483 dcbf 0,r10 /* Force it out */
484 sync /* Make sure it's out there */
485 dcbi 0,r10
486 eieio
487
488 li r7,0x0D /* Set the register */
489 stb r7,0(r10) /* Set the register */
490 dcbf 0,r10 /* Force it out */
491 sync /* Make sure it's out there */
492 dcbi 0,r10
493 eieio
494
495 li r7,0x00 /* 9600 baud high */
496 stb r7,0(r10) /* Set the register */
497 dcbf 0,r10 /* Force it out */
498 sync /* Make sure it's out there */
499 dcbi 0,r10
500 eieio
501
502 li r7,0x03 /* Set the register */
503 stb r7,0(r10) /* Set the register */
504 dcbf 0,r10 /* Force it out */
505 sync /* Make sure it's out there */
506 dcbi 0,r10
507 eieio
508
509 li r7,0xC1 /* 8 bits/char, Rx enable */
510 stb r7,0(r10) /* Set the register */
511 dcbf 0,r10 /* Force it out */
512 sync /* Make sure it's out there */
513 dcbi 0,r10
514 eieio
515
516 li r7,0x05 /* Set the register */
517 stb r7,0(r10) /* Set the register */
518 dcbf 0,r10 /* Force it out */
519 sync /* Make sure it's out there */
520 dcbi 0,r10
521 eieio
522
523 li r7,0xEA /* 8 bits/char, Tx enable */
524 stb r7,0(r10) /* Set the register */
525 dcbf 0,r10 /* Force it out */
526 sync /* Make sure it's out there */
527 dcbi 0,r10
528 eieio
529
530 li r7,0x0E /* Set the register */
531 stb r7,0(r10) /* Set the register */
532 dcbf 0,r10 /* Force it out */
533 sync /* Make sure it's out there */
534 dcbi 0,r10
535 eieio
536
537 li r7,0x01 /* BR rate gen enable */
538 stb r7,0(r10) /* Set the register */
539 dcbf 0,r10 /* Force it out */
540 sync /* Make sure it's out there */
541 dcbi 0,r10
542 eieio
543
544 li r7,0x0F /* Set the register */
545 stb r7,0(r10) /* Set the register */
546 dcbf 0,r10 /* Force it out */
547 sync /* Make sure it's out there */
548 dcbi 0,r10
549 eieio
550
551 li r7,0x00 /* ints off */
552 stb r7,0(r10) /* Set the register */
553 dcbf 0,r10 /* Force it out */
554 sync /* Make sure it's out there */
555 dcbi 0,r10
556 eieio
557
558 li r7,0x10 /* Reset ext/stat ints */
559 stb r7,0(r10) /* Set the register */
560 dcbf 0,r10 /* Force it out */
561 sync /* Make sure it's out there */
562 dcbi 0,r10
563 eieio
564
565 li r7,0x10 /* Reset ext/stat ints */
566 stb r7,0(r10) /* Set the register */
567 dcbf 0,r10 /* Force it out */
568 sync /* Make sure it's out there */
569 dcbi 0,r10
570 eieio
571
572 li r7,0x01 /* Set the register */
573 stb r7,0(r10) /* Set the register */
574 dcbf 0,r10 /* Force it out */
575 sync /* Make sure it's out there */
576 dcbi 0,r10
577 eieio
578
579 li r7,0x10 /* int on Rx, no Tx int enable */
580 stb r7,0(r10) /* Set the register */
581 dcbf 0,r10 /* Force it out */
582 sync /* Make sure it's out there */
583 dcbi 0,r10
584 eieio
585
586 li r7,0x09 /* Set the register */
587 stb r7,0(r10) /* Set the register */
588 dcbf 0,r10 /* Force it out */
589 sync /* Make sure it's out there */
590 dcbi 0,r10
591 eieio
592
593 li r7,0x0A /* int on Rx, Tx int enable */
594 stb r7,0(r10) /* Set the register */
595 dcbf 0,r10 /* Force it out */
596 sync /* Master enable, no vector */
597 dcbi 0,r10
598 eieio
599
600 li r7,0x09 /* Set the register */
601 stb r7,0(r10) /* Set the register */
602 dcbf 0,r10 /* Force it out */
603 sync /* Make sure it's out there */
604 dcbi 0,r10
605 eieio
606
607 li r7,0x02 /* No vector */
608 stb r7,0(r10) /* Set the register */
609 dcbf 0,r10 /* Force it out */
610 sync /* Master enable, no vector */
611 dcbi 0,r10
612 eieio
613
614 lbz r7,0(r10) /* Clear interrupts */
615 sync /* Master enable, no vector */
616 dcbi 0,r10
617 eieio
618
619 wSCCrdy: eieio /* Barricade it */
620 lbz r7,0(r10) /* Get current status */
621 dcbi 0,r10
622 sync
623 andi. r7,r7,0x04 /* Is transmitter empty? */
624 beq wSCCrdy /* Nope... */
625
626 eieio
627
628 #if 0
629 mtmsr r8 /* Restore 'rupts and TR */
630 isync
631 #endif
632 blr /* Leave... */
633
634 /*
635 * This routine is used to write debug output to either the modem or printer port.
636 * parm 1 is printer (0) or modem (1); parm 2 is ID (printed directly); parm 3 converted to hex
637 */
638
639 ENTRY(dbgDisp, TAG_NO_FRAME_USED)
640
641 mr r12,r0 /* Keep R0 pristene */
642 lis r0,HIGH_ADDR(dbgDispCall) /* Top half of dbgDispCall firmware call number */
643 ori r0,r0,LOW_ADDR(dbgDispCall) /* Bottom half */
644
645 sc /* Go display the stuff */
646
647 mr r0,r12 /* Restore R0 */
648 blr /* Return... */
649
650 /* Here's the low-level part of dbgDisp */
651
652 ENTRY(dbgDispLL, TAG_NO_FRAME_USED)
653
654 dbgDispInt: mfmsr r8 /* Save the MSR */
655
656 #if 0
657 lis r10,0xF301 /* (TEST/DEBUG) */
658 ori r10,r10,0x2002 /* (TEST/DEBUG) */
659 dcbf 0,r10 /* (TEST/DEBUG) */
660 sync /* (TEST/DEBUG) */
661 dcbi 0,r10 /* (TEST/DEBUG) */
662 eieio /* (TEST/DEBUG) */
663 li r7,0x35 /* (TEST/DEBUG) */
664 stb r7,4(r10) /* (TEST/DEBUG) */
665
666 lis r7,10 /* (TEST/DEBUG) */
667 spw6: addi r7,r7,-1 /* (TEST/DEBUG) */
668 mr. r7,r7 /* (TEST/DEBUG) */
669 bne- spw6 /* (TEST/DEBUG) */
670 dcbf 0,r10 /* (TEST/DEBUG) */
671 sync /* (TEST/DEBUG) */
672 dcbi 0,r10 /* (TEST/DEBUG) */
673 eieio /* (TEST/DEBUG) */
674 #endif
675
676 rlwinm r12,r8,0,28,25 /* Turn off translation */
677 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
678
679 mflr r11 /* Save the link register */
680
681 #if 0
682 mr r7,r12 /* (TEST/DEBUG) */
683 bl dumpr7 /* (TEST/DEBUG) */
684 #endif
685
686 mr. r3,r3 /* See if printer or modem */
687 lis r10,0xF301 /* Set the top part */
688 mr r3,r4 /* Copy the ID parameter */
689
690 #if 0
691 mr r9,r12 /* (TEST/DEBUG) */
692
693 mtmsr r12 /* (TEST/DEBUG) */
694 isync /* (TEST/DEBUG) */
695
696 #if 0
697 mtmsr r8 /* (TEST/DEBUG) */
698 isync /* (TEST/DEBUG) */
699 #endif
700
701 lis r12,0xF301 /* (TEST/DEBUG) */
702 ori r12,r12,0x2002 /* (TEST/DEBUG) */
703 #if 1
704 dcbf 0,r12 /* (TEST/DEBUG) */
705 sync /* (TEST/DEBUG) */
706 dcbi 0,r12 /* (TEST/DEBUG) */
707 #endif
708
709 xqrw1: eieio /* (TEST/DEBUG) */
710 lbz r7,0(r12) /* (TEST/DEBUG) */
711 dcbi 0,r12 /* (TEST/DEBUG) */
712 sync /* (TEST/DEBUG) */
713 andi. r7,r7,0x04 /* (TEST/DEBUG) */
714 beq xqrw1 /* (TEST/DEBUG) */
715
716 eieio /* (TEST/DEBUG) */
717 li r7,0x36 /* (TEST/DEBUG) */
718 stb r7,4(r12) /* (TEST/DEBUG) */
719 eieio
720 dcbf 0,r12 /* (TEST/DEBUG) */
721 sync /* (TEST/DEBUG) */
722 dcbi 0,r12 /* (TEST/DEBUG) */
723 eieio /* (TEST/DEBUG) */
724
725
726 lis r7,10 /* (TEST/DEBUG) */
727 spw7: addi r7,r7,-1 /* (TEST/DEBUG) */
728 mr. r7,r7 /* (TEST/DEBUG) */
729 bne- spw7 /* (TEST/DEBUG) */
730 dcbf 0,r12 /* (TEST/DEBUG) */
731 sync /* (TEST/DEBUG) */
732 dcbi 0,r12 /* (TEST/DEBUG) */
733 eieio /* (TEST/DEBUG) */
734 mr r12,r9 /* (TEST/DEBUG) */
735 #endif
736
737 mtmsr r12 /* Smash the MSR */
738 isync /* Make it clean */
739
740
741 #if SIMPLESCC && !NOTQUITEASSIMPLE
742 ori r10,r10,0x3010 /* Assume the printer (this is the normal one) */
743 #else
744 ori r10,r10,0x2000 /* Assume the printer (this is the normal one) */
745 #endif
746 beq+ dbgDprintr /* It sure are... */
747 #if SIMPLESCC && !NOTQUITEASSIMPLE
748 ori r10,r10,0x0020 /* Move it over to the modem port */
749 #else
750 ori r10,r10,0x0002 /* Move it over to the modem port */
751
752 #if !NOTQUITEASSIMPLE
753 lis r7,0xF300 /* Address of SCC rounded to 128k */
754 ori r7,r7,0x0032 /* Make it cache inhibited */
755 mtdbatl 3,r7 /* Load DBAT 3 low */
756 lis r7,0xF300 /* Address of SCC rounded to 128k */
757 ori r7,r7,0x0002 /* Make it supervisor only */
758 mtdbatu 3,r7 /* Load DBAT 3 high */
759 ori r12,r12,0x0010 /* Turn on DR */
760 mtmsr r12 /* Smash the MSR */
761 isync /* Make it clean */
762
763 #endif
764 #endif
765
766 dbgDprintr: sync
767 #if 0
768 mr r7,r10 /* (TEST/DEBUG) */
769 bl dumpr7 /* (TEST/DEBUG) */
770 #endif
771
772 dcbi 0,r10 /* Toss it */
773 eieio
774
775 #if 0
776 lis r12,0xF301 /* (TEST/DEBUG) */
777 ori r12,r12,0x2002 /* (TEST/DEBUG) */
778 dcbf 0,r12 /* (TEST/DEBUG) */
779 sync /* (TEST/DEBUG) */
780 dcbi 0,r12 /* (TEST/DEBUG) */
781 eieio /* (TEST/DEBUG) */
782 li r7,0x37 /* (TEST/DEBUG) */
783 stb r7,4(r12) /* (TEST/DEBUG) */
784
785 lis r7,12 /* (TEST/DEBUG) */
786 spw8: addi r7,r7,-1 /* (TEST/DEBUG) */
787 mr. r7,r7 /* (TEST/DEBUG) */
788 bne- spw8 /* (TEST/DEBUG) */
789 dcbf 0,r12 /* (TEST/DEBUG) */
790 sync /* (TEST/DEBUG) */
791 dcbi 0,r12 /* (TEST/DEBUG) */
792 eieio /* (TEST/DEBUG) */
793 #endif
794
795
796 /* Print the ID parameter */
797
798 lis r12,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
799 ori r12,r12,LOW_ADDR(fwdisplock) /* Last part */
800
801 lwarx r7,0,r12 ; ?
802
803 ddwait0: lwarx r7,0,r12 /* Get the lock */
804 mr. r7,r7 /* Is it locked? */
805 bne- ddwait0 /* Yup... */
806 stwcx. r12,0,r12 /* Try to get it */
807 bne- ddwait0 /* Nope, start all over... */
808
809 #if 0
810 dcbf 0,r10 /* (TEST/DEBUG) */
811 sync /* (TEST/DEBUG) */
812 dcbi 0,r10 /* (TEST/DEBUG) */
813 eieio /* (TEST/DEBUG) */
814 li r7,0x38 /* (TEST/DEBUG) */
815 stb r7,6(r10) /* (TEST/DEBUG) */
816
817 lis r7,10 /* (TEST/DEBUG) */
818 spwa: addi r7,r7,-1 /* (TEST/DEBUG) */
819 mr. r7,r7 /* (TEST/DEBUG) */
820 bne- spwa /* (TEST/DEBUG) */
821 dcbf 0,r10 /* (TEST/DEBUG) */
822 sync /* (TEST/DEBUG) */
823 dcbi 0,r10 /* (TEST/DEBUG) */
824 eieio /* (TEST/DEBUG) */
825 #endif
826
827 rlwinm r3,r3,8,0,31 /* Get the first character */
828 bl dbgDchar /* Print it */
829 rlwinm r3,r3,8,0,31 /* Get the second character */
830 bl dbgDchar /* Print it */
831 rlwinm r3,r3,8,0,31 /* Get the third character */
832 bl dbgDchar /* Print it */
833 rlwinm r3,r3,8,0,31 /* Get the fourth character */
834 bl dbgDchar /* Print it */
835
836 li r3,0x20 /* Get a space for a separator */
837 bl dbgDchar /* Print it */
838 bl dbg4byte /* Print register 5 in hex */
839
840 li r3,0x0A /* Linefeed */
841 bl dbgDchar /* Send it */
842 li r3,0x0D /* Carriage return */
843 bl dbgDchar /* Send it */
844
845 mtlr r11 /* Get back the return */
846 #if !SIMPLESCC && !NOTQUITEASSIMPLE
847 li r7,0 /* Get a zero */
848 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */
849 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */
850 #endif
851 lis r12,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
852 li r7,0 /* Get a zero */
853 ori r12,r12,LOW_ADDR(fwdisplock) /* Last part */
854 dcbi 0,r10 /* ? */
855 stw r7,0(r12) /* Release the display lock */
856 mtmsr r8 /* Restore the MSR */
857 isync /* Wait for it */
858 blr /* Leave... */
859
860
861 dbg4byte: mflr r12 /* Save the return */
862
863 lis r4,HIGH_ADDR(hexTab) /* Point to the top of table */
864 li r6,8 /* Set number of hex digits to dump */
865 ori r4,r4,LOW_ADDR(hexTab) /* Point to the bottom of table */
866
867 dbgDnext: rlwinm r5,r5,4,0,31 /* Rotate a nybble */
868 subi r6,r6,1 /* Back down the count */
869 rlwinm r3,r5,0,28,31 /* Isolate the last nybble */
870 lbzx r3,r4,r3 /* Convert to ascii */
871 bl dbgDchar /* Print it */
872 mr. r6,r6 /* Any more? */
873 bne+ dbgDnext /* Convert 'em all... */
874
875 li r3,0x20 /* Space */
876 bl dbgDchar /* Send it */
877 mtlr r12 /* Restore LR */
878 blr /* Return... */
879
880 /* Write to whichever serial port. Try to leave it clean, but not too hard (this is a hack) */
881
882 dbgDchar:
883 #if SIMPLESCC && !NOTQUITEASSIMPLE
884 stb r3,0(r10) /* ? */
885 dcbf 0,r10 /* Force it out */
886 sync /* Make sure it's out there */
887
888 lis r7,3 /* Get enough for about 1ms */
889
890 dbgDchar0: addi r7,r7,-1 /* Count down */
891 mr. r7,r7 /* Waited long enough? */
892 bgt+ dbgDchar0 /* Nope... */
893 #endif
894 #if NOTQUITEASSIMPLE
895 #if 0
896 li r7,0x01 /* ? */
897 stb r7,0(r10) /* ? */
898 dcbf 0,r10 /* Force it out */
899 sync /* Make sure it's out there */
900 dcbi 0,r10
901 eieio
902
903 lbz r7,0(r10) /* ? */
904 dcbi 0,r10 /* Force it out */
905 sync /* kill it off */
906 eieio
907
908 li r7,0x00 /* ? */
909 stb r7,0(r10) /* ? */
910 dcbf 0,r10 /* Force it out */
911 sync /* Make sure it's out there */
912 dcbi 0,r10
913 eieio
914
915 lbz r7,0(r10) /* ? */
916 dcbi 0,r10 /* Force it out */
917 sync /* kill it off */
918 eieio
919 #endif
920
921 qrw1: eieio /* Barricade it */
922 lbz r7,0(r10) /* ? */
923 dcbi 0,r10
924 sync
925 andi. r7,r7,0x04 /* ? */
926 beq qrw1 /* Nope... */
927
928 eieio
929
930 stb r3,4(r10) /* ? */
931 dcbf 0,r10 /* Force it out */
932 sync /* Make sure it's out there */
933 dcbi 0,r10
934 eieio
935
936 qrw2: eieio /* Barricade it */
937 lbz r7,0(r10) /* ? */
938 dcbi 0,r10
939 sync
940 andi. r7,r7,0x04 /* ? */
941 beq qrw2 /* Nope... */
942
943 #if 0
944 eieio
945 li r7,0x10 /* ? */
946 stb r7,0(r10) /* ? */
947 dcbf 0,r10 /* Force it out */
948 sync /* Make sure it's out there */
949 dcbi 0,r10
950 eieio
951
952 lbz r7,0(r10) /* ? */
953 dcbi 0,r10 /* Force it out */
954 sync /* kill it off */
955 eieio
956 #endif
957
958 lis r7,0x0080 /* ? */
959 lis r9,0xF300 /* ? */
960 ori r7,r7,0x010F /* ? */
961 stw r7,0x28(r9) /* ? */
962 dcbf 0,r10 /* Force it out */
963 sync /* Make sure it's out there */
964 dcbi 0,r10
965 eieio
966
967 #endif
968 #if !SIMPLESCC && !NOTQUITEASSIMPLE
969 rlwinm r9,r10,0,0,29 /* Get channel a */
970 eieio /* Barricade it */
971
972 li r7,0x03 /* ? */
973 stb r7,0(r9) /* ? */
974 eieio /* Barricade it */
975
976 lbz r7,0(r9) /* ? */
977
978 eieio /* Barricade it */
979 lbz r7,0(r9) /* ? */
980
981 dchrw1: eieio /* Barricade it */
982 lbz r7,0(r10) /* ? */
983 andi. r7,r7,0x04 /* ? */
984 beq dchrw1 /* Nope... */
985
986 stb r3,4(r10) /* ? */
987 sync /* Make sure it's there */
988 eieio /* Don't get confused */
989
990 dchrw2: eieio /* Barricade it */
991 lbz r7,0(r10) /* ? */
992 andi. r7,r7,0x04 /* ? */
993 beq dchrw2 /* Nope... */
994
995 eieio /* Avoid confusion */
996 lbz r7,0(r10) /* ? */
997 andi. r7,r7,0x40 /* ? */
998 beq+ nounder /* Nope... */
999
1000 eieio /* Avoid confusion */
1001 li r7,0xC0 /* ? */
1002 stb r7,0(r10) /* ? */
1003
1004 nounder: eieio /* Avoid confusion */
1005 li r7,0x10 /* ? */
1006 stb r7,0(r10) /* ? */
1007
1008 eieio /* Avoid confusion */
1009 li r7,0x38 /* ? */
1010 stb r7,0(r9) /* ? */
1011
1012 eieio /* Avoid confusion */
1013 li r7,0x30 /* ? */
1014 stb r7,0(r10) /* ? */
1015
1016 eieio /* Avoid confusion */
1017 li r7,0x20 /* ? */
1018 stb r7,0(r10) /* ? */
1019 eieio /* Avoid confusion */
1020 sync
1021
1022 #endif
1023 blr /* Return */
1024
1025 .globl hexTab
1026
1027 hexTab: STRINGD "0123456789ABCDEF" /* Convert hex numbers to printable hex */
1028
1029
1030 /*
1031 * Dumps all the registers in the savearea in R13
1032 */
1033
1034
1035 ENTRY(dbgRegsLL, TAG_NO_FRAME_USED)
1036
1037 li r3,0 /* ? */
1038 bl dbgRegsCm /* Join on up... */
1039
1040 /*
1041 * Note that we bypass the normal return 'cause we don't wanna mess up R3
1042 */
1043 mfsprg r11,0 /* Get the per_proc */
1044 lwz r11,PP_TEMPWORK1(r11) /* Get our return point */
1045 li r3,T_IN_VAIN /* Tell the vector handler that we took care of it */
1046 mtlr r11 /* Set the return */
1047 blr /* Bye, dudes... */
1048
1049 ENTRY(dbgRegs, TAG_NO_FRAME_USED)
1050
1051 dbgRegsCm: mfmsr r8 /* Save the MSR */
1052 mr. r3,r3 /* ? */
1053 rlwinm r12,r8,0,28,25 /* Turn off translation */
1054 lis r10,0xF301 /* Set the top part */
1055 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
1056 mtmsr r12 /* Smash the MSR */
1057 isync /* Make it clean */
1058 #if SIMPLESCC && !NOTQUITEASSIMPLE
1059 ori r10,r10,0x3010 /* ? */
1060 #else
1061 ori r10,r10,0x2000 /* ? */
1062 #endif
1063 mflr r11 /* Save the link register */
1064 beq+ dbgDprints /* It sure are... */
1065 #if SIMPLESCC && !NOTQUITEASSIMPLE
1066 ori r10,r10,0x0020 /* ? */
1067 #else
1068 ori r10,r10,0x0002 /* ? */
1069
1070 dcbf 0,r10 /* Insure it is out */
1071 sync
1072 dcbi 0,r10 /* Toss it */
1073 #if !NOTQUITEASSIMPLE
1074 lis r7,0xF300 /* ? */
1075 ori r7,r7,0x0032 /* ? */
1076 mtdbatl 3,r7 /* ? */
1077 lis r7,0xF300 /* ? */
1078 ori r7,r7,0x0002 /* ? */
1079 mtdbatu 3,r7 /* ? */
1080 ori r12,r12,0x0010 /* ? */
1081 mtmsr r12 /* ? */
1082 isync /* ? */
1083 #endif
1084 #endif
1085
1086 dbgDprints:
1087 lis r3,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
1088 ori r3,r3,LOW_ADDR(fwdisplock) /* Last part */
1089
1090 lwarx r5,0,r3 ; ?
1091 ddwait1: lwarx r5,0,r3 /* Get the lock */
1092 mr. r5,r5 /* Is it locked? */
1093 bne- ddwait1 /* Yup... */
1094 stwcx. r3,0,r3 /* Try to get it */
1095 bne- ddwait1 /* Nope, start all over... */
1096
1097 li r3,0x52 /* Print eyecatcher */
1098 bl dbgDchar /* Send it */
1099 li r3,0x65 /* Print eyecatcher */
1100 bl dbgDchar /* Send it */
1101 li r3,0x67 /* Print eyecatcher */
1102 bl dbgDchar /* Send it */
1103 li r3,0x73 /* Print eyecatcher */
1104 bl dbgDchar /* Send it */
1105 li r3,0x20 /* Print eyecatcher */
1106 bl dbgDchar /* Send it */
1107
1108 lwz r5,saver0(r13) /* Do register */
1109 bl dbg4byte /* Print */
1110 lwz r5,saver1(r13) /* Do register */
1111 bl dbg4byte /* Print */
1112 lwz r5,saver2(r13) /* Do register */
1113 bl dbg4byte /* Print */
1114 lwz r5,saver3(r13) /* Do register */
1115 bl dbg4byte /* Print */
1116 li r3,0x0A /* Linefeed */
1117 bl dbgDchar /* Send it */
1118 li r3,0x0D /* Carriage return */
1119 bl dbgDchar /* Send it */
1120
1121 li r3,0x20 /* Print eyecatcher */
1122 bl dbgDchar /* Send it */
1123 li r3,0x20 /* Print eyecatcher */
1124 bl dbgDchar /* Send it */
1125 li r3,0x20 /* Print eyecatcher */
1126 bl dbgDchar /* Send it */
1127 li r3,0x20 /* Print eyecatcher */
1128 bl dbgDchar /* Send it */
1129 li r3,0x20 /* Print eyecatcher */
1130 bl dbgDchar /* Send it */
1131 lwz r5,saver4(r13) /* Do register */
1132 bl dbg4byte /* Print */
1133 lwz r5,saver5(r13) /* Do register */
1134 bl dbg4byte /* Print */
1135 lwz r5,saver6(r13) /* Do register */
1136 bl dbg4byte /* Print */
1137 lwz r5,saver7(r13) /* Do register */
1138 bl dbg4byte /* Print */
1139 li r3,0x0A /* Linefeed */
1140 bl dbgDchar /* Send it */
1141 li r3,0x0D /* Carriage return */
1142 bl dbgDchar /* Send it */
1143
1144 li r3,0x20 /* Print eyecatcher */
1145 bl dbgDchar /* Send it */
1146 li r3,0x20 /* Print eyecatcher */
1147 bl dbgDchar /* Send it */
1148 li r3,0x20 /* Print eyecatcher */
1149 bl dbgDchar /* Send it */
1150 li r3,0x20 /* Print eyecatcher */
1151 bl dbgDchar /* Send it */
1152 li r3,0x20 /* Print eyecatcher */
1153 bl dbgDchar /* Send it */
1154 lwz r5,saver8(r13) /* Do register */
1155 bl dbg4byte /* Print */
1156 lwz r5,saver9(r13) /* Do register */
1157 bl dbg4byte /* Print */
1158 lwz r5,saver10(r13) /* Do register */
1159 bl dbg4byte /* Print */
1160 lwz r5,saver11(r13) /* Do register */
1161 bl dbg4byte /* Print */
1162 li r3,0x0A /* Linefeed */
1163 bl dbgDchar /* Send it */
1164 li r3,0x0D /* Carriage return */
1165 bl dbgDchar /* Send it */
1166
1167 li r3,0x20 /* Print eyecatcher */
1168 bl dbgDchar /* Send it */
1169 li r3,0x20 /* Print eyecatcher */
1170 bl dbgDchar /* Send it */
1171 li r3,0x20 /* Print eyecatcher */
1172 bl dbgDchar /* Send it */
1173 li r3,0x20 /* Print eyecatcher */
1174 bl dbgDchar /* Send it */
1175 li r3,0x20 /* Print eyecatcher */
1176 bl dbgDchar /* Send it */
1177 lwz r5,saver12(r13) /* Do register */
1178 bl dbg4byte /* Print */
1179 lwz r5,saver13(r13) /* Do register */
1180 bl dbg4byte /* Print */
1181 lwz r5,saver14(r13) /* Do register */
1182 bl dbg4byte /* Print */
1183 lwz r5,saver15(r13) /* Do register */
1184 bl dbg4byte /* Print */
1185 li r3,0x0A /* Linefeed */
1186 bl dbgDchar /* Send it */
1187 li r3,0x0D /* Carriage return */
1188 bl dbgDchar /* Send it */
1189
1190 li r3,0x20 /* Print eyecatcher */
1191 bl dbgDchar /* Send it */
1192 li r3,0x20 /* Print eyecatcher */
1193 bl dbgDchar /* Send it */
1194 li r3,0x20 /* Print eyecatcher */
1195 bl dbgDchar /* Send it */
1196 li r3,0x20 /* Print eyecatcher */
1197 bl dbgDchar /* Send it */
1198 li r3,0x20 /* Print eyecatcher */
1199 bl dbgDchar /* Send it */
1200 lwz r5,saver16(r13) /* Do register */
1201 bl dbg4byte /* Print */
1202 lwz r5,saver17(r13) /* Do register */
1203 bl dbg4byte /* Print */
1204 lwz r5,saver18(r13) /* Do register */
1205 bl dbg4byte /* Print */
1206 lwz r5,saver19(r13) /* Do register */
1207 bl dbg4byte /* Print */
1208 li r3,0x0A /* Linefeed */
1209 bl dbgDchar /* Send it */
1210 li r3,0x0D /* Carriage return */
1211 bl dbgDchar /* Send it */
1212
1213 li r3,0x20 /* Print eyecatcher */
1214 bl dbgDchar /* Send it */
1215 li r3,0x20 /* Print eyecatcher */
1216 bl dbgDchar /* Send it */
1217 li r3,0x20 /* Print eyecatcher */
1218 bl dbgDchar /* Send it */
1219 li r3,0x20 /* Print eyecatcher */
1220 bl dbgDchar /* Send it */
1221 li r3,0x20 /* Print eyecatcher */
1222 bl dbgDchar /* Send it */
1223 lwz r5,saver20(r13) /* Do register */
1224 bl dbg4byte /* Print */
1225 lwz r5,saver21(r13) /* Do register */
1226 bl dbg4byte /* Print */
1227 lwz r5,saver22(r13) /* Do register */
1228 bl dbg4byte /* Print */
1229 lwz r5,saver23(r13) /* Do register */
1230 bl dbg4byte /* Print */
1231 li r3,0x0A /* Linefeed */
1232 bl dbgDchar /* Send it */
1233 li r3,0x0D /* Carriage return */
1234 bl dbgDchar /* Send it */
1235
1236 li r3,0x20 /* Print eyecatcher */
1237 bl dbgDchar /* Send it */
1238 li r3,0x20 /* Print eyecatcher */
1239 bl dbgDchar /* Send it */
1240 li r3,0x20 /* Print eyecatcher */
1241 bl dbgDchar /* Send it */
1242 li r3,0x20 /* Print eyecatcher */
1243 bl dbgDchar /* Send it */
1244 li r3,0x20 /* Print eyecatcher */
1245 bl dbgDchar /* Send it */
1246 lwz r5,saver24(r13) /* Do register */
1247 bl dbg4byte /* Print */
1248 lwz r5,saver25(r13) /* Do register */
1249 bl dbg4byte /* Print */
1250 lwz r5,saver26(r13) /* Do register */
1251 bl dbg4byte /* Print */
1252 lwz r5,saver27(r13) /* Do register */
1253 bl dbg4byte /* Print */
1254 li r3,0x0A /* Linefeed */
1255 bl dbgDchar /* Send it */
1256 li r3,0x0D /* Carriage return */
1257 bl dbgDchar /* Send it */
1258
1259 li r3,0x20 /* Print eyecatcher */
1260 bl dbgDchar /* Send it */
1261 li r3,0x20 /* Print eyecatcher */
1262 bl dbgDchar /* Send it */
1263 li r3,0x20 /* Print eyecatcher */
1264 bl dbgDchar /* Send it */
1265 li r3,0x20 /* Print eyecatcher */
1266 bl dbgDchar /* Send it */
1267 li r3,0x20 /* Print eyecatcher */
1268 bl dbgDchar /* Send it */
1269 lwz r5,saver28(r13) /* Do register */
1270 bl dbg4byte /* Print */
1271 lwz r5,saver29(r13) /* Do register */
1272 bl dbg4byte /* Print */
1273 lwz r5,saver30(r13) /* Do register */
1274 bl dbg4byte /* Print */
1275 lwz r5,saver31(r13) /* Do register */
1276 bl dbg4byte /* Print */
1277 li r3,0x0A /* Linefeed */
1278 bl dbgDchar /* Send it */
1279 li r3,0x0D /* Carriage return */
1280 bl dbgDchar /* Send it */
1281
1282 /* Segment registers */
1283
1284 li r3,0x53 /* Print eyecatcher */
1285 bl dbgDchar /* Send it */
1286 li r3,0x65 /* Print eyecatcher */
1287 bl dbgDchar /* Send it */
1288 li r3,0x67 /* Print eyecatcher */
1289 bl dbgDchar /* Send it */
1290 li r3,0x73 /* Print eyecatcher */
1291 bl dbgDchar /* Send it */
1292 li r3,0x20 /* Print eyecatcher */
1293 bl dbgDchar /* Send it */
1294
1295 lwz r5,savesr0(r13) /* Do register */
1296 bl dbg4byte /* Print */
1297 lwz r5,savesr1(r13) /* Do register */
1298 bl dbg4byte /* Print */
1299 lwz r5,savesr2(r13) /* Do register */
1300 bl dbg4byte /* Print */
1301 lwz r5,savesr3(r13) /* Do register */
1302 bl dbg4byte /* Print */
1303 li r3,0x0A /* Linefeed */
1304 bl dbgDchar /* Send it */
1305 li r3,0x0D /* Carriage return */
1306 bl dbgDchar /* Send it */
1307
1308 li r3,0x20 /* Print eyecatcher */
1309 bl dbgDchar /* Send it */
1310 li r3,0x20 /* Print eyecatcher */
1311 bl dbgDchar /* Send it */
1312 li r3,0x20 /* Print eyecatcher */
1313 bl dbgDchar /* Send it */
1314 li r3,0x20 /* Print eyecatcher */
1315 bl dbgDchar /* Send it */
1316 li r3,0x20 /* Print eyecatcher */
1317 bl dbgDchar /* Send it */
1318 lwz r5,savesr4(r13) /* Do register */
1319 bl dbg4byte /* Print */
1320 lwz r5,savesr5(r13) /* Do register */
1321 bl dbg4byte /* Print */
1322 lwz r5,savesr6(r13) /* Do register */
1323 bl dbg4byte /* Print */
1324 lwz r5,savesr7(r13) /* Do register */
1325 bl dbg4byte /* Print */
1326 li r3,0x0A /* Linefeed */
1327 bl dbgDchar /* Send it */
1328 li r3,0x0D /* Carriage return */
1329 bl dbgDchar /* Send it */
1330
1331 li r3,0x20 /* Print eyecatcher */
1332 bl dbgDchar /* Send it */
1333 li r3,0x20 /* Print eyecatcher */
1334 bl dbgDchar /* Send it */
1335 li r3,0x20 /* Print eyecatcher */
1336 bl dbgDchar /* Send it */
1337 li r3,0x20 /* Print eyecatcher */
1338 bl dbgDchar /* Send it */
1339 li r3,0x20 /* Print eyecatcher */
1340 bl dbgDchar /* Send it */
1341 lwz r5,savesr8(r13) /* Do register */
1342 bl dbg4byte /* Print */
1343 lwz r5,savesr9(r13) /* Do register */
1344 bl dbg4byte /* Print */
1345 lwz r5,savesr10(r13) /* Do register */
1346 bl dbg4byte /* Print */
1347 lwz r5,savesr11(r13) /* Do register */
1348 bl dbg4byte /* Print */
1349 li r3,0x0A /* Linefeed */
1350 bl dbgDchar /* Send it */
1351 li r3,0x0D /* Carriage return */
1352 bl dbgDchar /* Send it */
1353
1354 li r3,0x20 /* Print eyecatcher */
1355 bl dbgDchar /* Send it */
1356 li r3,0x20 /* Print eyecatcher */
1357 bl dbgDchar /* Send it */
1358 li r3,0x20 /* Print eyecatcher */
1359 bl dbgDchar /* Send it */
1360 li r3,0x20 /* Print eyecatcher */
1361 bl dbgDchar /* Send it */
1362 li r3,0x20 /* Print eyecatcher */
1363 bl dbgDchar /* Send it */
1364 lwz r5,savesr12(r13) /* Do register */
1365 bl dbg4byte /* Print */
1366 lwz r5,savesr13(r13) /* Do register */
1367 bl dbg4byte /* Print */
1368 lwz r5,savesr14(r13) /* Do register */
1369 bl dbg4byte /* Print */
1370 lwz r5,savesr15(r13) /* Do register */
1371 bl dbg4byte /* Print */
1372 li r3,0x0A /* Linefeed */
1373 bl dbgDchar /* Send it */
1374 li r3,0x0D /* Carriage return */
1375 bl dbgDchar /* Send it */
1376
1377 li r3,0x30 /* Print eyecatcher */
1378 bl dbgDchar /* Send it */
1379 li r3,0x31 /* Print eyecatcher */
1380 bl dbgDchar /* Send it */
1381 li r3,0x64 /* Print eyecatcher */
1382 bl dbgDchar /* Send it */
1383 li r3,0x64 /* Print eyecatcher */
1384 bl dbgDchar /* Send it */
1385 li r3,0x20 /* Print eyecatcher */
1386 bl dbgDchar /* Send it */
1387 lwz r5,savesrr0(r13) /* Do register */
1388 bl dbg4byte /* Print */
1389 lwz r5,savesrr1(r13) /* Do register */
1390 bl dbg4byte /* Print */
1391 lwz r5,savedar(r13) /* Do register */
1392 bl dbg4byte /* Print */
1393 lwz r5,savedsisr(r13) /* Do register */
1394 bl dbg4byte /* Print */
1395 li r3,0x0A /* Linefeed */
1396 bl dbgDchar /* Send it */
1397 li r3,0x0D /* Carriage return */
1398 bl dbgDchar /* Send it */
1399
1400 li r3,0x20 /* Print eyecatcher */
1401 bl dbgDchar /* Send it */
1402 li r3,0x6C /* Print eyecatcher */
1403 bl dbgDchar /* Send it */
1404 li r3,0x63 /* Print eyecatcher */
1405 bl dbgDchar /* Send it */
1406 li r3,0x63 /* Print eyecatcher */
1407 bl dbgDchar /* Send it */
1408 li r3,0x20 /* Print eyecatcher */
1409 bl dbgDchar /* Send it */
1410 lwz r5,savelr(r13) /* Do register */
1411 bl dbg4byte /* Print */
1412 lwz r5,savecr(r13) /* Do register */
1413 bl dbg4byte /* Print */
1414 lwz r5,savectr(r13) /* Do register */
1415 bl dbg4byte /* Print */
1416 li r3,0x0A /* Linefeed */
1417 bl dbgDchar /* Send it */
1418 li r3,0x0D /* Carriage return */
1419 bl dbgDchar /* Send it */
1420 mtlr r11 /* Get back the return */
1421 dcbi 0,r10 /* ? */
1422 #if !SIMPLESCC && !NOTQUITEASSIMPLE
1423 li r7,0 /* Get a zero */
1424 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */
1425 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */
1426 #endif
1427 lis r3,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
1428 li r7,0 /* Get a zero */
1429 ori r3,r3,LOW_ADDR(fwdisplock) /* Last part */
1430 stw r7,0(r3) /* Clear display lock */
1431 mtmsr r8 /* Restore the MSR */
1432 isync /* Wait for it */
1433 blr /* Leave... */
1434
1435
1436 /*
1437 * Used for debugging to leave stuff in 0x380-0x3FF (128 bytes).
1438 * Mapping is V=R. Stores and loads are real.
1439 */
1440
1441 ENTRY(dbgCkpt, TAG_NO_FRAME_USED)
1442
1443 mr r12,r0 /* Keep R0 pristene */
1444 lis r0,HIGH_ADDR(dbgCkptCall) /* Top half of dbgCkptCall firmware call number */
1445 ori r0,r0,LOW_ADDR(dbgCkptCall) /* Bottom half */
1446
1447 sc /* Go stash the stuff */
1448
1449 mr r0,r12 /* Restore R0 */
1450 blr /* Return... */
1451
1452 /* Here's the low-level part of dbgCkpt */
1453
1454 ENTRY(dbgCkptLL, TAG_NO_FRAME_USED)
1455
1456 li r12,0x380 /* Point to output area */
1457 li r1,32 /* Get line size */
1458 dcbz 0,r12 /* Make sure we don't fetch a cache line */
1459
1460 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1461
1462 dcbt r1,r3 /* Start in the next line */
1463
1464 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1465 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1466 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1467 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1468 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1469 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1470 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1471
1472 add r3,r3,r1 /* Bump input */
1473
1474 stw r4,0x00(r12) /* Store it */
1475 stw r5,0x04(r12) /* Store it */
1476 stw r6,0x08(r12) /* Store it */
1477 stw r7,0x0C(r12) /* Store it */
1478 stw r8,0x10(r12) /* Store it */
1479 stw r9,0x14(r12) /* Store it */
1480 stw r10,0x18(r12) /* Store it */
1481 stw r11,0x1C(r12) /* Store it */
1482
1483 dcbz r1,r12 /* Clear the next line */
1484 add r12,r12,r1 /* Point to next output line */
1485
1486 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1487 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1488 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1489 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1490 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1491 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1492 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1493 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1494
1495 dcbt r1,r3 /* Touch the next line */
1496 add r3,r3,r1 /* Point to next input line */
1497
1498 stw r4,0x00(r12) /* Store it */
1499 stw r5,0x04(r12) /* Store it */
1500 stw r6,0x08(r12) /* Store it */
1501 stw r7,0x0C(r12) /* Store it */
1502 stw r8,0x10(r12) /* Store it */
1503 stw r9,0x14(r12) /* Store it */
1504 stw r10,0x18(r12) /* Store it */
1505 stw r11,0x1C(r12) /* Store it */
1506
1507 dcbz r1,r12 /* Clear the next line */
1508 add r12,r12,r1 /* Point to next output line */
1509
1510 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1511 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1512 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1513 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1514 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1515 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1516 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1517 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1518
1519 dcbt r1,r3 /* Touch the next line */
1520 add r3,r3,r1 /* Point to next input line */
1521
1522 stw r4,0x00(r12) /* Store it */
1523 stw r5,0x04(r12) /* Store it */
1524 stw r6,0x08(r12) /* Store it */
1525 stw r7,0x0C(r12) /* Store it */
1526 stw r8,0x10(r12) /* Store it */
1527 stw r9,0x14(r12) /* Store it */
1528 stw r10,0x18(r12) /* Store it */
1529 stw r11,0x1C(r12) /* Store it */
1530
1531 dcbz r1,r12 /* Clear the next line */
1532 add r12,r12,r1 /* Point to next output line */
1533
1534 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1535 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1536 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1537 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1538 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1539 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1540 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1541 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1542
1543 stw r4,0x00(r12) /* Store it */
1544 stw r5,0x04(r12) /* Store it */
1545 stw r6,0x08(r12) /* Store it */
1546 stw r7,0x0C(r12) /* Store it */
1547 stw r8,0x10(r12) /* Store it */
1548 stw r9,0x14(r12) /* Store it */
1549 stw r10,0x18(r12) /* Store it */
1550 stw r11,0x1C(r12) /* Store it */
1551
1552 blr
1553
1554
1555 /*
1556 * Do Preemption. Forces a T_PREEMPT trap to allow a preemption to occur.
1557 */
1558
1559 ENTRY(DoPreemptLL, TAG_NO_FRAME_USED)
1560
1561 mfsprg r11,0 /* Get the per_proc address */
1562 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1563 li r3,T_PREEMPT /* Set preemption interrupt value */
1564 mtlr r11 /* Restore the LR */
1565 stw r3,saveexception(r13) /* Modify the exception type to preemption */
1566 blr /* Return to interrupt handler */
1567
1568
1569 /*
1570 * Force 'rupt handler to dispatch with new context
1571 * R3 at the call contains the new savearea.
1572 * R4 at the call contains a return code to pass back in R3.
1573 * Forces a T_CSWITCH
1574 */
1575
1576 ENTRY(SwitchContextLL, TAG_NO_FRAME_USED)
1577
1578 mfsprg r11,0 /* Get the per_proc address */
1579 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1580 li r3,T_CSWITCH /* Set context switch value */
1581 mtlr r11 /* Restore the LR */
1582 stw r3,saveexception(r13) /* Modify the exception type to switch context */
1583 blr /* Return to interrupt handler */
1584
1585
1586 /*
1587 * Create a fake I/O 'rupt.
1588 * Forces a T_INTERRUPT trap to pretend that an actual I/O interrupt occurred.
1589 */
1590
1591 ENTRY(CreateFakeIOLL, TAG_NO_FRAME_USED)
1592
1593 mfsprg r11,0 /* Get the per_proc address */
1594 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1595 li r3,T_INTERRUPT /* Set external interrupt value */
1596 mtlr r11 /* Restore the LR */
1597 stw r3,saveexception(r13) /* Modify the exception type to external */
1598 blr /* Return to interrupt handler */
1599
1600 /*
1601 * Create a shutdown context
1602 * Forces a T_SHUTDOWN trap.
1603 */
1604
1605 ENTRY(CreateShutdownCTXLL, TAG_NO_FRAME_USED)
1606
1607 mfsprg r11,0 /* Get the per_proc address */
1608 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1609 li r3,T_SHUTDOWN /* Set external interrupt value */
1610 mtlr r11 /* Restore the LR */
1611 stw r3,saveexception(r13) /* Modify the exception type to external */
1612 blr /* Return to interrupt handler */
1613
1614 /*
1615 * Create a fake decrementer 'rupt.
1616 * Forces a T_DECREMENTER trap to pretend that an actual decrementer interrupt occurred.
1617 */
1618
1619 ENTRY(CreateFakeDECLL, TAG_NO_FRAME_USED)
1620
1621 mfsprg r11,0 /* Get the per_proc address */
1622 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1623 li r3,T_DECREMENTER /* Set decrementer interrupt value */
1624 mtlr r11 /* Restore the LR */
1625 stw r3,saveexception(r13) /* Modify the exception type to external */
1626 blr /* Return to interrupt handler */
1627
1628 /*
1629 * Choke the system.
1630 */
1631
1632 ENTRY(DoChokeLL, TAG_NO_FRAME_USED)
1633
1634 mfsprg r11,0 ; Get the per_proc address
1635 lwz r11,PP_TEMPWORK1(r11) ; Restore the return address
1636 li r3,T_CHOKE ; Set external interrupt value
1637 mtlr r11 ; Restore the LR
1638 stw r3,saveexception(r13) ; Modify the exception type to external
1639 blr ; Return to interrupt handler
1640
1641 /*
1642 * Set the low level trace flags
1643 */
1644
1645 ENTRY(LLTraceSet, TAG_NO_FRAME_USED)
1646
1647 mfsprg r6,2 ; Get feature flags
1648 mfmsr r12 /* Get the MSR */
1649 mr r4,r3 /* Save the new value */
1650 andi. r3,r12,0x01C0 /* Clear interrupts and translation */
1651 mtcrf 0x04,r6 ; Set the features
1652 bt pfNoMSRirb,ltsNoMSR ; Use MSR...
1653
1654 mtmsr r3 ; Translation and all off
1655 isync ; Toss prefetch
1656 b ltsNoMSRx
1657
1658 ltsNoMSR: li r0,loadMSR ; Get the MSR setter SC
1659 sc ; Set it
1660
1661 ltsNoMSRx:
1662
1663 lis r5,hi16(EXT(trcWork)) ; Get trace area
1664 rlwinm r12,r12,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
1665 ori r5,r5,lo16(EXT(trcWork)) ; again
1666
1667 lwz r3,traceMask(r5) /* Get the old trace flags to pass back */
1668 rlwinm r12,r12,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
1669 stw r4,traceMask(r5) /* Replace with the new ones */
1670
1671 mtmsr r12 /* Restore the MSR */
1672 isync
1673
1674 blr /* Leave... */
1675
1676 #if 1
1677
1678 /*
1679 ; ***************************************************************************
1680 ;
1681 ; ----------------- Grateful Deb ----------------
1682 ;
1683 ; Debugging: direct draw into main screen menu bar
1684 ;
1685 ; Takes R4 value, converts it to hex characters and displays it.
1686 ;
1687 ; Gotta make sure the DCBST is done to force the pixels from the cache.
1688 ;
1689 ; Position is taken as column, row (0 based) from R3.
1690 ; Characters are from hexfont, and are 16x16 pixels.
1691 ;
1692 ; Only works with two processors so far
1693 ;
1694 ;
1695 ; ***************************************************************************
1696 */
1697
1698 #define GDfromright 20
1699 #define GDfontsize 16
1700
1701 ENTRY(GratefulDeb,TAG_NO_FRAME_USED)
1702 mfspr r6,pir /* Get the PIR */
1703 lis r5,HIGH_ADDR(EXT(GratefulDebWork)) /* Point to our work area */
1704 rlwinm r6,r6,8,23,23 /* Get part of the offset to our processors area */
1705 ori r5,r5,LOW_ADDR(EXT(GratefulDebWork)) /* Start building the address */
1706 rlwimi r6,r6,2,21,21 /* Get the rest of the offset to our processors area */
1707 add r6,r6,r5 /* Point at our CPU's work area */
1708 mfmsr r5 /* Get that MSR */
1709 stmw r0,GDsave(r6) /* Save all registers */
1710 lwz r10,GDready(r6) /* See if we're all ready to go */
1711 ori r0,r5,0x2000 /* Turn on the floating point */
1712 mr r31,r6 /* Get a more sane base register */
1713 mr. r10,r10 /* Are we all set? */
1714 mtmsr r0 /* Enable floating point */
1715 isync
1716
1717 stfd f0,GDfp0(r31) /* Save FP */
1718 stfd f1,GDfp1(r31) /* Save FP */
1719 stfd f2,GDfp2(r31) /* Save FP */
1720 stfd f3,GDfp3(r31) /* Save FP */
1721
1722 beq- GDbailout /* Go and bail... */
1723
1724 rlwinm r25,r3,0,16,31 /* Isolate just the row number */
1725 lwz r28,GDtopleft(r31) /* Get the physical address of our line 0 */
1726 rlwinm r3,r3,16,16,31 /* Isolate the column number */
1727 lwz r27,GDrowbytes(r31) /* Get the number of bytes per row */
1728 lwz r9,GDrowchar(r31) /* Get the number of bytes per row of full leaded charactrers */
1729 lwz r26,GDdepth(r31) /* Get the bit depth */
1730 mullw r25,r25,r9 /* get offset to the row to write in bytes */
1731 lwz r24,GDcollgn(r31) /* Get the size of columns in bytes */
1732 add r25,r28,r25 /* Physical address of row */
1733 mullw r3,r3,r24 /* Get byte offset to first output column */
1734
1735 li r9,32 /* Get the initial shift calc */
1736
1737 lis r20,HIGH_ADDR(hexfont) /* Point to the font */
1738
1739 li r18,GDfontsize /* Get the number of rows in the font */
1740 ori r20,r20,LOW_ADDR(hexfont) /* Point to the low part */
1741 add r21,r25,r3 /* Physical address of top left output pixel */
1742 sub r9,r9,r26 /* Get right shift justifier for pixel size */
1743 li r7,32 /* Number of bits per word */
1744
1745 startNybble:
1746 la r6,GDrowbuf1(r31) /* Point to the row buffer */
1747 li r19,8 /* Get the number of characters in a row */
1748
1749 getNybble: rlwinm r10,r4,9,23,26 /* Get the top nybble * 32 */
1750 rlwinm r4,r4,4,0,31 /* Rotate a nybble */
1751 add r10,r20,r10 /* Point to the character in the font */
1752
1753 rlwinm r16,r26,4,0,27 /* Width of row in actual bits */
1754 lhz r15,0(r10) /* Get the next row of the font */
1755
1756 rendrow: rlwinm r17,r15,16,0,0 /* Get the next font pixel in the row */
1757 rlwinm r15,r15,1,16,31 /* Move in the next font pixel */
1758 srawi r17,r17,31 /* Fill with 1s if black and 0s if white (reversed) */
1759
1760 slw r14,r14,r26 /* Make room for our pixel in a register */
1761 srw r17,r17,r9 /* Isolate one pixels worth of black or white */
1762 sub. r7,r7,r26 /* See how may bits are left */
1763 sub r16,r16,r26 /* Count how many bits are left to store for this row */
1764 or r14,r14,r17 /* Put in the pixel */
1765 bne+ notfull /* Finish rendering this word */
1766
1767 not r14,r14 /* Invert to black on white */
1768 stw r14,0(r6) /* Write out the word */
1769 li r7,32 /* Bit per word count */
1770 addi r6,r6,4 /* Point to the next word */
1771
1772 notfull: mr. r16,r16 /* Have we finished the whole character row? */
1773 bne+ rendrow /* Finish rendering the row */
1774
1775 addic. r19,r19,-1 /* Are we finished with a whole display row yet? */
1776 bne+ getNybble /* Not yet... */
1777
1778 la r6,GDrowbuf1(r31) /* Point to the row buffer */
1779 rlwinm r19,r26,31,0,29 /* Number of cache lines (depth/2) */
1780 mr r14,r21 /* Get the frame buffer address */
1781
1782 // BREAKPOINT_TRAP
1783
1784 blitrow: lfd f0,0(r6) /* Load a line */
1785 lfd f1,8(r6)
1786 lfd f2,16(r6)
1787 lfd f3,24(r6)
1788
1789 stfd f0,0(r14) /* Blit a line */
1790 stfd f1,8(r14)
1791 stfd f2,16(r14)
1792 stfd f3,24(r14)
1793
1794 addi r6,r6,32 /* Next buffered line */
1795
1796 dcbst 0,r14 /* Force the line to the screen */
1797 sync /* Make sure the line is on it's way */
1798 eieio /* Make sure we beat the invalidate */
1799 dcbi 0,r14 /* Make sure we leave no paradox */
1800
1801 addic. r19,r19,-1 /* Done all lines yet? */
1802 addi r14,r14,32 /* Point to the next output */
1803 bne+ blitrow /* Nope, do it some more... */
1804
1805 addic. r18,r18,-1 /* Have we done all the rows in character yet? */
1806 addi r20,r20,2 /* Offset the font to the next row */
1807 add r21,r21,r27 /* Point to start of next row */
1808 bne+ startNybble /* Nope, go through the word one more time... */
1809
1810 GDbailout: mr r1,r31 /* Move the workarea base */
1811
1812 lfd f0,GDfp0(r31) /* Restore FP */
1813 lfd f1,GDfp1(r31) /* Restore FP */
1814 lfd f2,GDfp2(r31) /* Restore FP */
1815 lfd f3,GDfp3(r31) /* Restore FP */
1816
1817 mtmsr r5 /* Disable floating point */
1818 isync
1819
1820 lmw r3,GDsave+12(r1) /* Restore most registers */
1821 lwz r0,GDsave(r1) /* Restore R0 */
1822 lwz r1,GDsave+4(r1) /* Finally, R1 */
1823 blr /* Leave... */
1824
1825
1826 /*
1827 * void GratefulDebDisp(unsigned int coord, unsigned int data);
1828 */
1829
1830
1831 ENTRY(GratefulDebDisp,TAG_NO_FRAME_USED)
1832
1833 mfmsr r9 /* Save the current MSR */
1834 mflr r7 /* Save the return */
1835 andi. r8,r9,0x7FCF /* Clear interrupt and translation */
1836 mtmsr r8 /* Turn 'em really off */
1837 isync /* Make sure about the translation part */
1838 bl EXT(GratefulDeb) /* Display it */
1839 mtmsr r9 /* Restore interrupt and translation */
1840 mtlr r7 /* Restore return */
1841 isync /* Make sure */
1842 blr
1843
1844
1845 #endif
1846
1847 /*
1848 * void checkNMI(void);
1849 */
1850
1851
1852 ENTRY(checkNMI,TAG_NO_FRAME_USED)
1853
1854 mfmsr r9 /* Save it */
1855 andi. r8,r9,0x7FCF /* Clear it */
1856 mtmsr r8 /* Disable it */
1857 isync /* Fence it */
1858 lis r7,0xF300 /* Find it */
1859 ori r7,r7,0x0020 /* Find it */
1860 dcbi 0,r7 /* Toss it */
1861 sync /* Sync it */
1862 rlwinm r9,r9,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
1863 eieio /* Get it */
1864 lwz r6,0x000C(r7) /* Check it */
1865 eieio /* Fence it */
1866 dcbi 0,r7 /* Toss it */
1867 rlwinm r9,r9,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
1868 rlwinm. r4,r6,0,19,19 /* Check it */
1869 rlwinm r6,r6,0,20,18 /* Clear it */
1870 sync /* Sync it */
1871 eieio /* Fence it */
1872 beq+ xnonmi /* Branch on it */
1873
1874 stw r6,0x0008(r7) /* Reset it */
1875 sync /* Sync it */
1876 dcbi 0,r6 /* Toss it */
1877 eieio /* Fence it */
1878
1879 mtmsr r9 /* Restore it */
1880 isync /* Hold it */
1881
1882 BREAKPOINT_TRAP /* Kill it */
1883 blr /* Return from it */
1884
1885 xnonmi: /* Label it */
1886 mtmsr r9 /* Restore it */
1887 isync /* Hold it */
1888 blr /* Return from it */
1889
1890
1891 /*
1892 * Early debug code
1893 */
1894
1895 dumpr7: lis r9,HIGH_ADDR(hexTab) /* (TEST/DEBUG) */
1896 li r5,8 /* (TEST/DEBUG) */
1897 ori r9,r9,LOW_ADDR(hexTab) /* (TEST/DEBUG) */
1898
1899 dumpr7n: rlwinm r7,r7,4,0,31 /* (TEST/DEBUG) */
1900 mr r6,r7 /* (TEST/DEBUG) */
1901 andi. r6,r6,15 /* (TEST/DEBUG) */
1902 lbzx r6,r9,r6 /* (TEST/DEBUG) */
1903 lis r10,0xF301 /* (TEST/DEBUG) */
1904 ori r10,r10,0x2000 /* (TEST/DEBUG) */
1905
1906 #if 0
1907 xqrw2: eieio /* (TEST/DEBUG) */
1908 lbz r7,0(r10) /* (TEST/DEBUG) */
1909 dcbi 0,r10 /* (TEST/DEBUG) */
1910 sync /* (TEST/DEBUG) */
1911 andi. r7,r7,0x04 /* (TEST/DEBUG) */
1912 beq xqrw2 /* (TEST/DEBUG) */
1913 #endif
1914
1915 dcbf 0,r10 /* (TEST/DEBUG) */
1916 sync /* (TEST/DEBUG) */
1917 dcbi 0,r10 /* (TEST/DEBUG) */
1918 eieio /* (TEST/DEBUG) */
1919 stb r6,4(r10) /* (TEST/DEBUG) */
1920
1921 lis r6,10 /* (TEST/DEBUG) */
1922 dumpr7d: addi r6,r6,-1 /* (TEST/DEBUG) */
1923 mr. r6,r6 /* (TEST/DEBUG) */
1924 bne- dumpr7d /* (TEST/DEBUG) */
1925 dcbf 0,r10 /* (TEST/DEBUG) */
1926 sync /* (TEST/DEBUG) */
1927 dcbi 0,r10 /* (TEST/DEBUG) */
1928 eieio /* (TEST/DEBUG) */
1929
1930 addic. r5,r5,-1 /* (TEST/DEBUG) */
1931 bne+ dumpr7n /* (TEST/DEBUG) */
1932
1933 blr /* (TEST/DEBUG) */
1934
1935 ;
1936 ; Log a special entry in physical memory.
1937 ; This assumes that memory size has been significantly lowered using
1938 ; the maxmem boot option. The buffer starts just after the end of mem_size.
1939 ;
1940 ; This is absolutely for special tracing cases. Do not ever leave in...
1941 ;
1942
1943 ENTRY(dbgLog,TAG_NO_FRAME_USED)
1944
1945 li r11,0 ; Clear callers callers callers return
1946 li r10,0 ; Clear callers callers callers callers return
1947 li r9,0 ; Clear callers callers callers callers callers return
1948 lwz r2,0(r1) ; Get callers callers stack frame
1949 lis r0,0x4000 ; First invalid address
1950 lwz r12,8(r2) ; Get our callers return
1951 lwz r2,0(r2) ; Back chain
1952
1953 mr. r2,r2 ; End of chain?
1954 cmplw cr1,r2,r0 ; Valid kernel address?
1955 beq- nosavehere ; Yes, end of chain...
1956 bge- cr1,nosavehere ; No...
1957 lwz r11,8(r2) ; Get our callers return
1958 lwz r2,0(r2) ; Back chain
1959
1960 mr. r2,r2 ; End of chain?
1961 cmplw cr1,r2,r0 ; Valid kernel address?
1962 beq- nosavehere ; Yes, end of chain...
1963 bge- cr1,nosavehere ; No...
1964 lwz r10,8(r2) ; Get our callers return
1965 lwz r2,0(r2) ; Back chain
1966
1967 mr. r2,r2 ; End of chain?
1968 cmplw cr1,r2,r0 ; Valid kernel address?
1969 beq- nosavehere ; Yes, end of chain...
1970 bge- cr1,nosavehere ; No...
1971 lwz r9,8(r2) ; Get our callers return
1972
1973 nosavehere: mfmsr r8 ; Get the MSR
1974 lis r2,hi16(EXT(DebugWork)) ; High part of area
1975 lis r7,hi16(EXT(mem_actual)) ; High part of actual
1976 andi. r0,r8,0x7FCF ; Interrupts and translation off
1977 ori r2,r2,lo16(EXT(DebugWork)) ; Get the entry
1978 mtmsr r0 ; Turn stuff off
1979 ori r7,r7,lo16(EXT(mem_actual)) ; Get the actual
1980 isync
1981
1982 lwz r0,4(r2) ; Get the flag
1983 mr. r0,r0 ; Should we log?
1984 lwz r0,0(r7) ; Get the end of memory
1985 lwz r7,0(r2) ; Get the position
1986 bne- waytoofar ; No logging...
1987 mr. r7,r7 ; Is this the first?
1988 bne+ gotspot ; Nope...
1989
1990 lis r7,hi16(EXT(mem_size)) ; High part of defined memory
1991 ori r7,r7,lo16(EXT(mem_size)) ; Low part of defined memory
1992 lwz r7,0(r7) ; Make it end of defined
1993
1994 gotspot: cmplw r7,r0 ; Do we fit in memory
1995 addi r0,r7,0x0020 ; Next slot
1996 bge- waytoofar ; No fit...
1997
1998 stw r0,0(r2) ; Set next time slot
1999 dcbz 0,r7 ; Zap it
2000
2001 stw r3,0(r7) ; First data
2002 li r3,32 ; Disp to next line
2003 stw r4,4(r7) ; Second data
2004 dcbz r3,r7 ; Zap it
2005 stw r5,8(r7) ; Third data
2006 stw r6,12(r7) ; Fourth data
2007
2008 stw r12,16(r7) ; Callers callers
2009 stw r11,20(r7) ; Callers callers caller
2010 stw r10,24(r7) ; Callers callers callers caller
2011 stw r9,28(r7) ; Callers callers callers callers caller
2012
2013 waytoofar: mtmsr r8 ; Back to normal
2014 isync
2015 blr
2016
2017 ;
2018 ; Same as the other, but no traceback and 16 byte entry
2019 ; Trashes R0, R2, R10, R12
2020 ;
2021
2022 .align 5
2023 .globl EXT(dbgLog2)
2024
2025 LEXT(dbgLog2)
2026
2027
2028 mfmsr r10 ; Get the MSR
2029 lis r2,hi16(EXT(DebugWork)) ; High part of area
2030 lis r12,hi16(EXT(mem_actual)) ; High part of actual
2031 andi. r0,r10,0x7FCF ; Interrupts and translation off
2032 ori r2,r2,lo16(EXT(DebugWork)) ; Get the entry
2033 mtmsr r0 ; Turn stuff off
2034 ori r12,r12,lo16(EXT(mem_actual)) ; Get the actual
2035 isync
2036
2037 lwz r0,4(r2) ; Get the flag
2038 mr. r0,r0 ; Should we log?
2039 lwz r0,0(r12) ; Get the end of memory
2040 lwz r12,0(r2) ; Get the position
2041 bne- waytoofar2 ; No logging...
2042 mr. r12,r12 ; Is this the first?
2043 bne+ gotspot2 ; Nope...
2044
2045 lis r12,hi16(EXT(mem_size)) ; High part of defined memory
2046 ori r12,r12,lo16(EXT(mem_size)) ; Low part of defined memory
2047 lwz r12,0(r12) ; Make it end of defined
2048
2049 gotspot2: cmplw cr1,r12,r0 ; Do we fit in memory
2050 rlwinm. r0,r12,0,27,27 ; Are we on a new line?
2051 bge- cr1,waytoofar2 ; No fit...
2052 addi r0,r12,0x0010 ; Next slot
2053
2054 bne+ nonewline ; Not on a new line...
2055 dcbz br0,r12 ; Clear it so we do not fetch it
2056
2057 nonewline: cmplwi r3,68 ; Special place for time stamp?
2058
2059 stw r0,0(r2) ; Set next time slot
2060 bne+ nospcts ; Nope...
2061
2062 lwz r0,0x17C(br0) ; Get special saved time stamp
2063 b nospctt ; Skip...
2064
2065 nospcts: mftb r0 ; Get the current time
2066
2067 nospctt: stw r3,4(r12) ; First data
2068 stw r4,8(r12) ; Second data
2069 stw r5,12(r12) ; Third data
2070 stw r0,0(r12) ; Time stamp
2071
2072 waytoofar2: mtmsr r10 ; Back to normal
2073 isync
2074 blr
2075
2076
2077 ;
2078 ; Saves floating point registers
2079 ;
2080
2081 .align 5
2082 .globl EXT(stFloat)
2083
2084 LEXT(stFloat)
2085
2086 mfmsr r0 ; Save the MSR
2087 rlwinm r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
2088 rlwinm r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
2089 rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
2090 ori r4,r4,lo16(MASK(MSR_FP)) ; Enable floating point
2091 mtmsr r4
2092 isync
2093
2094 stfd f0,0x00(r3)
2095 stfd f1,0x08(r3)
2096 stfd f2,0x10(r3)
2097 stfd f3,0x18(r3)
2098 stfd f4,0x20(r3)
2099 stfd f5,0x28(r3)
2100 stfd f6,0x30(r3)
2101 stfd f7,0x38(r3)
2102 stfd f8,0x40(r3)
2103 stfd f9,0x48(r3)
2104 stfd f10,0x50(r3)
2105 stfd f11,0x58(r3)
2106 stfd f12,0x60(r3)
2107 stfd f13,0x68(r3)
2108 stfd f14,0x70(r3)
2109 stfd f15,0x78(r3)
2110 stfd f16,0x80(r3)
2111 stfd f17,0x88(r3)
2112 stfd f18,0x90(r3)
2113 stfd f19,0x98(r3)
2114 stfd f20,0xA0(r3)
2115 stfd f21,0xA8(r3)
2116 stfd f22,0xB0(r3)
2117 stfd f23,0xB8(r3)
2118 stfd f24,0xC0(r3)
2119 stfd f25,0xC8(r3)
2120 stfd f26,0xD0(r3)
2121 stfd f27,0xD8(r3)
2122 stfd f28,0xE0(r3)
2123 stfd f29,0xE8(r3)
2124 stfd f30,0xF0(r3)
2125 stfd f31,0xF8(r3)
2126 mffs f0
2127 stfd f0,0x100(r3)
2128 lfd f0,0x00(r3)
2129 mtmsr r0
2130 isync
2131 blr
2132
2133
2134 ;
2135 ; Saves vector registers. Returns 0 if non-Altivec machine.
2136 ;
2137
2138 .align 5
2139 .globl EXT(stVectors)
2140
2141 LEXT(stVectors)
2142
2143
2144 mfsprg r6,2 ; Get features
2145 mr r5,r3 ; Save area address
2146 rlwinm. r6,r6,0,pfAltivecb,pfAltivecb ; Do we have Altivec?
2147 li r3,0 ; Assume failure
2148 beqlr- ; No...
2149
2150 mfmsr r0 ; Save the MSR
2151 rlwinm r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
2152 rlwinm r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
2153 rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
2154 oris r4,r4,hi16(MASK(MSR_VEC)) ; Enable vectors
2155 mtmsr r4
2156 isync
2157
2158 stvxl v0,0,r5
2159 addi r5,r5,16
2160 stvxl v1,0,r5
2161 addi r5,r5,16
2162 stvxl v2,0,r5
2163 addi r5,r5,16
2164 stvxl v3,0,r5
2165 addi r5,r5,16
2166 stvxl v4,0,r5
2167 addi r5,r5,16
2168 stvxl v5,0,r5
2169 addi r5,r5,16
2170 stvxl v6,0,r5
2171 addi r5,r5,16
2172 stvxl v7,0,r5
2173 addi r5,r5,16
2174 stvxl v8,0,r5
2175 addi r5,r5,16
2176 stvxl v9,0,r5
2177 addi r5,r5,16
2178 stvxl v10,0,r5
2179 addi r5,r5,16
2180 stvxl v11,0,r5
2181 addi r5,r5,16
2182 stvxl v12,0,r5
2183 addi r5,r5,16
2184 stvxl v13,0,r5
2185 addi r5,r5,16
2186 stvxl v14,0,r5
2187 addi r5,r5,16
2188 stvxl v15,0,r5
2189 addi r5,r5,16
2190 stvxl v16,0,r5
2191 addi r5,r5,16
2192 stvxl v17,0,r5
2193 addi r5,r5,16
2194 stvxl v18,0,r5
2195 addi r5,r5,16
2196 stvxl v19,0,r5
2197 addi r5,r5,16
2198 stvxl v20,0,r5
2199 addi r5,r5,16
2200 stvxl v21,0,r5
2201 addi r5,r5,16
2202 stvxl v22,0,r5
2203 addi r5,r5,16
2204 stvxl v23,0,r5
2205 addi r5,r5,16
2206 stvxl v24,0,r5
2207 addi r5,r5,16
2208 stvxl v25,0,r5
2209 addi r5,r5,16
2210 stvxl v26,0,r5
2211 addi r5,r5,16
2212 stvxl v27,0,r5
2213 addi r5,r5,16
2214 stvxl v28,0,r5
2215 addi r5,r5,16
2216 stvxl v29,0,r5
2217 addi r5,r5,16
2218 stvxl v30,0,r5
2219 addi r5,r5,16
2220 stvxl v31,0,r5
2221 mfvscr v31
2222 addi r6,r5,16
2223 stvxl v31,0,r6
2224 li r3,1
2225 lvxl v31,0,r5
2226 mtmsr r0
2227 isync
2228
2229 blr
2230
2231
2232 ;
2233 ; Saves yet more registers
2234 ;
2235
2236 .align 5
2237 .globl EXT(stSpecrs)
2238
2239 LEXT(stSpecrs)
2240
2241 mfmsr r0 ; Save the MSR
2242 rlwinm r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
2243 rlwinm r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
2244 rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
2245 mtmsr r4
2246 isync
2247
2248 mfpvr r12
2249 stw r12,4(r3)
2250 rlwinm r12,r12,16,16,31
2251
2252 mfdbatu r4,0
2253 mfdbatl r5,0
2254 mfdbatu r6,1
2255 mfdbatl r7,1
2256 mfdbatu r8,2
2257 mfdbatl r9,2
2258 mfdbatu r10,3
2259 mfdbatl r11,3
2260 stw r4,8(r3)
2261 stw r5,12(r3)
2262 stw r6,16(r3)
2263 stw r7,20(r3)
2264 stw r8,24(r3)
2265 stw r9,28(r3)
2266 stw r10,32(r3)
2267 stw r11,36(r3)
2268
2269 mfibatu r4,0
2270 mfibatl r5,0
2271 mfibatu r6,1
2272 mfibatl r7,1
2273 mfibatu r8,2
2274 mfibatl r9,2
2275 mfibatu r10,3
2276 mfibatl r11,3
2277 stw r4,40(r3)
2278 stw r5,44(r3)
2279 stw r6,48(r3)
2280 stw r7,52(r3)
2281 stw r8,56(r3)
2282 stw r9,60(r3)
2283 stw r10,64(r3)
2284 stw r11,68(r3)
2285
2286 mfsprg r4,0
2287 mfsprg r5,1
2288 mfsprg r6,2
2289 mfsprg r7,3
2290 stw r4,72(r3)
2291 stw r5,76(r3)
2292 stw r6,80(r3)
2293 stw r7,84(r3)
2294
2295 mfsdr1 r4
2296 stw r4,88(r3)
2297
2298 la r4,92(r3)
2299 li r5,0
2300
2301 stSnsr: mfsrin r6,r5
2302 addis r5,r5,0x1000
2303 stw r6,0(r4)
2304 mr. r5,r5
2305 addi r4,r4,4
2306 bne+ stSnsr
2307
2308 cmplwi cr1,r12,PROCESSOR_VERSION_604e
2309 cmplwi cr5,r12,PROCESSOR_VERSION_604ev
2310 cror cr1_eq,cr1_eq,cr5_eq ; Set if 604 type
2311 cmplwi r12,PROCESSOR_VERSION_750
2312 mfspr r4,hid0
2313 stw r4,(39*4)(r3)
2314
2315 li r4,0
2316 li r5,0
2317 li r6,0
2318 li r7,0
2319 beq- cr1,before750
2320 blt- before750
2321
2322 mfspr r4,hid1
2323 mfspr r5,l2cr
2324 mfspr r6,msscr0
2325 mfspr r7,msscr1
2326
2327 before750: stw r4,(40*4)(r3)
2328 stw r6,(42*4)(r3)
2329 stw r5,(41*4)(r3)
2330 stw r7,(43*4)(r3)
2331
2332 li r4,0
2333 beq isis750
2334
2335 mfspr r4,pir
2336 isis750: stw r4,0(r3)
2337
2338 li r4,0
2339 li r5,0
2340 li r6,0
2341 li r7,0
2342 beq- cr1,b4750
2343 blt- b4750
2344
2345 mfspr r4,thrm1
2346 mfspr r5,thrm2
2347 mfspr r6,thrm3
2348 mfspr r7,ictc
2349
2350 b4750: stw r4,(44*4)(r3)
2351 stw r5,(45*4)(r3)
2352 stw r6,(46*4)(r3)
2353 stw r7,(47*4)(r3)
2354
2355 li r4,0
2356 cmplwi r12,PROCESSOR_VERSION_7400
2357 bne nnmax
2358
2359 mfpvr r5
2360 rlwinm r5,r5,0,16,31
2361 cmplwi r5,0x1101
2362 beq gnmax
2363 cmplwi r5,0x1102
2364 bne nnmax
2365
2366 gnmax: mfspr r4,1016
2367
2368 nnmax: stw r4,(48*4)(r3)
2369
2370 mtmsr r0
2371 isync
2372
2373 blr
mirror of XNU