osfmk/i386/machine_check.c

   1 /*
   2  * Copyright (c) 2007-2011 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28
  29 #include <kern/kalloc.h>
  30 #include <mach/mach_time.h>
  31 #include <i386/cpu_data.h>
  32 #include <i386/cpuid.h>
  33 #include <i386/cpu_topology.h>
  34 #include <i386/cpu_threads.h>
  35 #include <i386/machine_cpu.h>
  36 #include <i386/machine_check.h>
  37 #include <i386/proc_reg.h>
  38
  39 /*
  40  * At the time of the machine-check exception, all hardware-threads panic.
  41  * Each thread saves the state of its MCA registers to its per-cpu data area.
  42  *
  43  * State reporting is serialized so one thread dumps all valid state for all
  44  * threads to the panic log. This may entail spinning waiting for other
  45  * threads to complete saving state to memory. A timeout applies to this wait
  46  * -- in particular, a 3-strikes timeout may prevent a thread from taking
  47  * part is the affair.
  48  */
  49
  50 #define IF(bool,str)    ((bool) ? (str) : "")
  51
  52 static boolean_t        mca_initialized = FALSE;
  53 static boolean_t        mca_MCE_present = FALSE;
  54 static boolean_t        mca_MCA_present = FALSE;
  55 static uint32_t         mca_family = 0;
  56 static unsigned int     mca_error_bank_count = 0;
  57 static boolean_t        mca_control_MSR_present = FALSE;
  58 static boolean_t        mca_threshold_status_present = FALSE;
  59 static boolean_t        mca_sw_error_recovery_present = FALSE;
  60 static boolean_t        mca_extended_MSRs_present = FALSE;
  61 static unsigned int     mca_extended_MSRs_count = 0;
  62 static boolean_t        mca_cmci_present = FALSE;
  63 static ia32_mcg_cap_t   ia32_mcg_cap;
  64 decl_simple_lock_data(static, mca_lock);
  65
  66 typedef struct {
  67         ia32_mci_ctl_t          mca_mci_ctl;
  68         ia32_mci_status_t       mca_mci_status;
  69         ia32_mci_misc_t         mca_mci_misc;
  70         ia32_mci_addr_t         mca_mci_addr;
  71 } mca_mci_bank_t;
  72
  73 typedef struct mca_state {
  74         boolean_t               mca_is_saved;
  75         boolean_t               mca_is_valid;   /* some state is valid */
  76         ia32_mcg_ctl_t          mca_mcg_ctl;
  77         ia32_mcg_status_t       mca_mcg_status;
  78         mca_mci_bank_t          mca_error_bank[0];
  79 } mca_state_t;
  80
  81 typedef enum {
  82         CLEAR,
  83         DUMPING,
  84         DUMPED
  85 } mca_dump_state_t;
  86 static volatile mca_dump_state_t mca_dump_state = CLEAR;
  87
  88 static void
  89 mca_get_availability(void)
  90 {
  91         uint64_t        features = cpuid_info()->cpuid_features;
  92         uint32_t        family =   cpuid_info()->cpuid_family;
  93         uint32_t        model =    cpuid_info()->cpuid_model;
  94         uint32_t        stepping = cpuid_info()->cpuid_stepping;
  95
  96         if ((model == CPUID_MODEL_HASWELL     && stepping < 3) ||
  97             (model == CPUID_MODEL_HASWELL_ULT && stepping < 1) ||
  98             (model == CPUID_MODEL_CRYSTALWELL && stepping < 1))
  99                 panic("Haswell pre-C0 steppings are not supported");
 100
 101         mca_MCE_present = (features & CPUID_FEATURE_MCE) != 0;
 102         mca_MCA_present = (features & CPUID_FEATURE_MCA) != 0;
 103         mca_family = family;
 104
 105         /*
 106          * If MCA, the number of banks etc is reported by the IA32_MCG_CAP MSR.
 107          */
 108         if (mca_MCA_present) {
 109                 ia32_mcg_cap.u64 = rdmsr64(IA32_MCG_CAP);
 110                 mca_error_bank_count = ia32_mcg_cap.bits.count;
 111                 mca_control_MSR_present = ia32_mcg_cap.bits.mcg_ctl_p;
 112                 mca_threshold_status_present = ia32_mcg_cap.bits.mcg_tes_p;
 113                 mca_sw_error_recovery_present = ia32_mcg_cap.bits.mcg_ser_p;
 114                 mca_cmci_present = ia32_mcg_cap.bits.mcg_ext_corr_err_p;
 115                 if (family == 0x0F) {
 116                         mca_extended_MSRs_present = ia32_mcg_cap.bits.mcg_ext_p;
 117                         mca_extended_MSRs_count = ia32_mcg_cap.bits.mcg_ext_cnt;
 118                 }
 119         }
 120 }
 121
 122 void
 123 mca_cpu_init(void)
 124 {
 125         unsigned int    i;
 126
 127         /*
 128          * The first (boot) processor is responsible for discovering the
 129          * machine check architecture present on this machine.
 130          */
 131         if (!mca_initialized) {
 132                 mca_get_availability();
 133                 mca_initialized = TRUE;
 134                 simple_lock_init(&mca_lock, 0);
 135         }
 136
 137         if (mca_MCA_present) {
 138
 139                 /* Enable all MCA features */
 140                 if (mca_control_MSR_present)
 141                         wrmsr64(IA32_MCG_CTL, IA32_MCG_CTL_ENABLE);
 142
 143                 switch (mca_family) {
 144                 case 0x06:
 145                         /* Enable all but mc0 */
 146                         for (i = 1; i < mca_error_bank_count; i++)
 147                                 wrmsr64(IA32_MCi_CTL(i),0xFFFFFFFFFFFFFFFFULL);
 148
 149                         /* Clear all errors */
 150                         for (i = 0; i < mca_error_bank_count; i++)
 151                                 wrmsr64(IA32_MCi_STATUS(i), 0ULL);
 152                         break;
 153                 case 0x0F:
 154                         /* Enable all banks */
 155                         for (i = 0; i < mca_error_bank_count; i++)
 156                                 wrmsr64(IA32_MCi_CTL(i),0xFFFFFFFFFFFFFFFFULL);
 157
 158                         /* Clear all errors */
 159                         for (i = 0; i < mca_error_bank_count; i++)
 160                                 wrmsr64(IA32_MCi_STATUS(i), 0ULL);
 161                         break;
 162                 }
 163         }
 164
 165         /* Enable machine check exception handling if available */
 166         if (mca_MCE_present) {
 167                 set_cr4(get_cr4()|CR4_MCE);
 168         }
 169 }
 170
 171 boolean_t
 172 mca_is_cmci_present(void)
 173 {
 174         if (!mca_initialized)
 175                 mca_cpu_init();
 176         return mca_cmci_present;
 177 }
 178
 179 void
 180 mca_cpu_alloc(cpu_data_t        *cdp)
 181 {
 182         vm_size_t       mca_state_size;
 183
 184         /*
 185          * Allocate space for an array of error banks.
 186          */
 187         mca_state_size = sizeof(mca_state_t) +
 188                                 sizeof(mca_mci_bank_t) * mca_error_bank_count;
 189         cdp->cpu_mca_state = kalloc(mca_state_size);
 190         if (cdp->cpu_mca_state == NULL) {
 191                 printf("mca_cpu_alloc() failed for cpu %d\n", cdp->cpu_number);
 192                 return;
 193         }
 194         bzero((void *) cdp->cpu_mca_state, mca_state_size);
 195
 196         /*
 197          * If the boot processor is yet have its allocation made,
 198          * do this now.
 199          */
 200         if (cpu_datap(master_cpu)->cpu_mca_state == NULL)
 201                 mca_cpu_alloc(cpu_datap(master_cpu));
 202 }
 203
 204 static void
 205 mca_save_state(mca_state_t *mca_state)
 206 {
 207         mca_mci_bank_t  *bank;
 208         unsigned int    i;
 209
 210         assert(!ml_get_interrupts_enabled() || get_preemption_level() > 0);
 211
 212         if  (mca_state == NULL)
 213                 return;
 214
 215         mca_state->mca_mcg_ctl = mca_control_MSR_present ?
 216                                         rdmsr64(IA32_MCG_CTL) : 0ULL;
 217         mca_state->mca_mcg_status.u64 = rdmsr64(IA32_MCG_STATUS);
 218
 219         bank = (mca_mci_bank_t *) &mca_state->mca_error_bank[0];
 220         for (i = 0; i < mca_error_bank_count; i++, bank++) {
 221                 bank->mca_mci_ctl        = rdmsr64(IA32_MCi_CTL(i));
 222                 bank->mca_mci_status.u64 = rdmsr64(IA32_MCi_STATUS(i));
 223                 if (!bank->mca_mci_status.bits.val)
 224                         continue;
 225                 bank->mca_mci_misc = (bank->mca_mci_status.bits.miscv)?
 226                                         rdmsr64(IA32_MCi_MISC(i)) : 0ULL;
 227                 bank->mca_mci_addr = (bank->mca_mci_status.bits.addrv)?
 228                                         rdmsr64(IA32_MCi_ADDR(i)) : 0ULL;
 229                 mca_state->mca_is_valid = TRUE;
 230         }
 231
 232         /*
 233          * If we're the first thread with MCA state, point our package to it
 234          * and don't care about races
 235          */
 236         if (x86_package()->mca_state == NULL)
 237                         x86_package()->mca_state = mca_state;
 238
 239         mca_state->mca_is_saved = TRUE;
 240 }
 241
 242 void
 243 mca_check_save(void)
 244 {
 245         if (mca_dump_state > CLEAR)
 246                 mca_save_state(current_cpu_datap()->cpu_mca_state);
 247 }
 248
 249 static void mca_dump_64bit_state(void)
 250 {
 251         kdb_printf("Extended Machine Check State:\n");
 252         kdb_printf("  IA32_MCG_RAX:    0x%016qx\n", rdmsr64(IA32_MCG_RAX));
 253         kdb_printf("  IA32_MCG_RBX:    0x%016qx\n", rdmsr64(IA32_MCG_RBX));
 254         kdb_printf("  IA32_MCG_RCX:    0x%016qx\n", rdmsr64(IA32_MCG_RCX));
 255         kdb_printf("  IA32_MCG_RDX:    0x%016qx\n", rdmsr64(IA32_MCG_RDX));
 256         kdb_printf("  IA32_MCG_RSI:    0x%016qx\n", rdmsr64(IA32_MCG_RSI));
 257         kdb_printf("  IA32_MCG_RDI:    0x%016qx\n", rdmsr64(IA32_MCG_RDI));
 258         kdb_printf("  IA32_MCG_RBP:    0x%016qx\n", rdmsr64(IA32_MCG_RBP));
 259         kdb_printf("  IA32_MCG_RSP:    0x%016qx\n", rdmsr64(IA32_MCG_RSP));
 260         kdb_printf("  IA32_MCG_RFLAGS: 0x%016qx\n", rdmsr64(IA32_MCG_RFLAGS));
 261         kdb_printf("  IA32_MCG_RIP:    0x%016qx\n", rdmsr64(IA32_MCG_RIP));
 262         kdb_printf("  IA32_MCG_MISC:   0x%016qx\n", rdmsr64(IA32_MCG_MISC));
 263         kdb_printf("  IA32_MCG_R8:     0x%016qx\n", rdmsr64(IA32_MCG_R8));
 264         kdb_printf("  IA32_MCG_R9:     0x%016qx\n", rdmsr64(IA32_MCG_R9));
 265         kdb_printf("  IA32_MCG_R10:    0x%016qx\n", rdmsr64(IA32_MCG_R10));
 266         kdb_printf("  IA32_MCG_R11:    0x%016qx\n", rdmsr64(IA32_MCG_R11));
 267         kdb_printf("  IA32_MCG_R12:    0x%016qx\n", rdmsr64(IA32_MCG_R12));
 268         kdb_printf("  IA32_MCG_R13:    0x%016qx\n", rdmsr64(IA32_MCG_R13));
 269         kdb_printf("  IA32_MCG_R14:    0x%016qx\n", rdmsr64(IA32_MCG_R14));
 270         kdb_printf("  IA32_MCG_R15:    0x%016qx\n", rdmsr64(IA32_MCG_R15));
 271 }
 272
 273 static void
 274 mca_report_cpu_info(void)
 275 {
 276         i386_cpu_info_t *infop = cpuid_info();
 277
 278         kdb_printf(" family: %d model: %d stepping: %d microcode: %d\n",
 279                 infop->cpuid_family,
 280                 infop->cpuid_model,
 281                 infop->cpuid_stepping,
 282                 infop->cpuid_microcode_version);
 283         kdb_printf(" %s\n", infop->cpuid_brand_string);
 284 }
 285
 286 static const char *mc8_memory_operation[] = {
 287         [MC8_MMM_GENERIC] =             "generic",
 288         [MC8_MMM_READ] =                "read",
 289         [MC8_MMM_WRITE] =               "write",
 290         [MC8_MMM_ADDRESS_COMMAND] =     "address/command",
 291         [MC8_MMM_RESERVED] =            "reserved"
 292 };
 293
 294 static void
 295 mca_dump_bank_mc8(mca_state_t *state, int i)
 296 {
 297         mca_mci_bank_t                  *bank;
 298         ia32_mci_status_t               status;
 299         struct ia32_mc8_specific        mc8;
 300         int                             mmm;
 301
 302         bank = &state->mca_error_bank[i];
 303         status = bank->mca_mci_status;
 304         mc8 = status.bits_mc8;
 305         mmm = MIN(mc8.memory_operation, MC8_MMM_RESERVED);
 306
 307         kdb_printf(
 308                 " IA32_MC%d_STATUS(0x%x): 0x%016qx %svalid\n",
 309                 i, IA32_MCi_STATUS(i), status.u64, IF(!status.bits.val, "in"));
 310         if (!status.bits.val)
 311                 return;
 312
 313         kdb_printf(
 314                 "  Channel number:         %d%s\n"
 315                 "  Memory Operation:       %s\n"
 316                 "  Machine-specific error: %s%s%s%s%s%s%s%s%s\n"
 317                 "  COR_ERR_CNT:            %d\n",
 318                 mc8.channel_number,
 319                 IF(mc8.channel_number == 15, " (unknown)"),
 320                 mc8_memory_operation[mmm],
 321                 IF(mc8.read_ecc,            "Read ECC "),
 322                 IF(mc8.ecc_on_a_scrub,      "ECC on scrub "),
 323                 IF(mc8.write_parity,        "Write parity "),
 324                 IF(mc8.redundant_memory,    "Redundant memory "),
 325                 IF(mc8.sparing,             "Sparing/Resilvering "),
 326                 IF(mc8.access_out_of_range, "Access out of Range "),
 327                 IF(mc8.rtid_out_of_range,   "RTID out of Range "),
 328                 IF(mc8.address_parity,      "Address Parity "),
 329                 IF(mc8.byte_enable_parity,  "Byte Enable Parity "),
 330                 mc8.cor_err_cnt);
 331         kdb_printf(
 332                 "  Status bits:\n%s%s%s%s%s%s",
 333                 IF(status.bits.pcc,         "   Processor context corrupt\n"),
 334                 IF(status.bits.addrv,       "   ADDR register valid\n"),
 335                 IF(status.bits.miscv,       "   MISC register valid\n"),
 336                 IF(status.bits.en,          "   Error enabled\n"),
 337                 IF(status.bits.uc,          "   Uncorrected error\n"),
 338                 IF(status.bits.over,        "   Error overflow\n"));
 339         if (status.bits.addrv)
 340                 kdb_printf(
 341                         " IA32_MC%d_ADDR(0x%x): 0x%016qx\n",
 342                         i, IA32_MCi_ADDR(i), bank->mca_mci_addr);
 343         if (status.bits.miscv) {
 344                 ia32_mc8_misc_t mc8_misc;
 345
 346                 mc8_misc.u64 = bank->mca_mci_misc;
 347                 kdb_printf(
 348                         " IA32_MC%d_MISC(0x%x): 0x%016qx\n"
 349                         "  RTID:     %d\n"
 350                         "  DIMM:     %d\n"
 351                         "  Channel:  %d\n"
 352                         "  Syndrome: 0x%x\n",
 353                         i, IA32_MCi_MISC(i), mc8_misc.u64,
 354                         mc8_misc.bits.rtid,
 355                         mc8_misc.bits.dimm,
 356                         mc8_misc.bits.channel,
 357                         (int) mc8_misc.bits.syndrome);
 358         }
 359 }
 360
 361 static const char *mca_threshold_status[] = {
 362         [THRESHOLD_STATUS_NO_TRACKING] =        "No tracking",
 363         [THRESHOLD_STATUS_GREEN] =              "Green",
 364         [THRESHOLD_STATUS_YELLOW] =             "Yellow",
 365         [THRESHOLD_STATUS_RESERVED] =           "Reserved"
 366 };
 367
 368 static void
 369 mca_dump_bank(mca_state_t *state, int i)
 370 {
 371         mca_mci_bank_t          *bank;
 372         ia32_mci_status_t       status;
 373
 374         bank = &state->mca_error_bank[i];
 375         status = bank->mca_mci_status;
 376         kdb_printf(
 377                 " IA32_MC%d_STATUS(0x%x): 0x%016qx %svalid\n",
 378                 i, IA32_MCi_STATUS(i), status.u64, IF(!status.bits.val, "in"));
 379         if (!status.bits.val)
 380                 return;
 381
 382         kdb_printf(
 383                 "  MCA error code:            0x%04x\n",
 384                 status.bits.mca_error);
 385         kdb_printf(
 386                 "  Model specific error code: 0x%04x\n",
 387                 status.bits.model_specific_error);
 388         if (!mca_threshold_status_present) {
 389                 kdb_printf(
 390                         "  Other information:         0x%08x\n",
 391                         status.bits.other_information);
 392         } else {
 393                 int     threshold = status.bits_tes_p.threshold;
 394                 kdb_printf(
 395                         "  Other information:         0x%08x\n"
 396                         "  Threshold-based status:    %s\n",
 397                         status.bits_tes_p.other_information,
 398                         (status.bits_tes_p.uc == 0) ?
 399                             mca_threshold_status[threshold] :
 400                             "Undefined");
 401         }
 402         if (mca_threshold_status_present &&
 403             mca_sw_error_recovery_present) {
 404                 kdb_printf(
 405                         "  Software Error Recovery:\n%s%s",
 406                         IF(status.bits_tes_p.ar, "   Recovery action reqd\n"),
 407                         IF(status.bits_tes_p.s,  "   Signaling UCR error\n"));
 408         }
 409         kdb_printf(
 410                 "  Status bits:\n%s%s%s%s%s%s",
 411                 IF(status.bits.pcc,   "   Processor context corrupt\n"),
 412                 IF(status.bits.addrv, "   ADDR register valid\n"),
 413                 IF(status.bits.miscv, "   MISC register valid\n"),
 414                 IF(status.bits.en,    "   Error enabled\n"),
 415                 IF(status.bits.uc,    "   Uncorrected error\n"),
 416                 IF(status.bits.over,  "   Error overflow\n"));
 417         if (status.bits.addrv)
 418                 kdb_printf(
 419                         " IA32_MC%d_ADDR(0x%x): 0x%016qx\n",
 420                         i, IA32_MCi_ADDR(i), bank->mca_mci_addr);
 421         if (status.bits.miscv)
 422                 kdb_printf(
 423                         " IA32_MC%d_MISC(0x%x): 0x%016qx\n",
 424                         i, IA32_MCi_MISC(i), bank->mca_mci_misc);
 425 }
 426
 427 static void
 428 mca_cpu_dump_error_banks(mca_state_t *state)
 429 {
 430         unsigned int            i;
 431
 432         if (!state->mca_is_valid)
 433                 return;
 434
 435         kdb_printf("MCA error-reporting registers:\n");
 436         for (i = 0; i < mca_error_bank_count; i++ ) {
 437                 if (i == 8 && state == x86_package()->mca_state) {
 438                         /*
 439                          * Fatal Memory Error
 440                          */
 441
 442                         /* Dump MC8 for this package */
 443                         kdb_printf(" Package %d logged:\n",
 444                                    x86_package()->ppkg_num);
 445                         mca_dump_bank_mc8(state, 8);
 446                         continue;
 447                 }
 448                 mca_dump_bank(state, i);
 449         }
 450 }
 451
 452 void
 453 mca_dump(void)
 454 {
 455         mca_state_t     *mca_state = current_cpu_datap()->cpu_mca_state;
 456         uint64_t        deadline;
 457         unsigned int    i = 0;
 458
 459         /*
 460          * Capture local MCA registers to per-cpu data.
 461          */
 462         mca_save_state(mca_state);
 463
 464         /*
 465          * Serialize: the first caller controls dumping MCA registers,
 466          * other threads spin meantime.
 467          */
 468         simple_lock(&mca_lock);
 469         if (mca_dump_state > CLEAR) {
 470                 simple_unlock(&mca_lock);
 471                 while (mca_dump_state == DUMPING)
 472                         cpu_pause();
 473                 return;
 474         }
 475         mca_dump_state = DUMPING;
 476         simple_unlock(&mca_lock);
 477
 478         /*
 479          * Wait for all other hardware threads to save their state.
 480          * Or timeout.
 481          */
 482         deadline = mach_absolute_time() + LockTimeOut;
 483         while (mach_absolute_time() < deadline && i < real_ncpus) {
 484                 if (!cpu_datap(i)->cpu_mca_state->mca_is_saved) {
 485                         cpu_pause();
 486                         continue;
 487                 }
 488                 i += 1;
 489         }
 490
 491         /*
 492          * Report machine-check capabilities:
 493          */
 494         kdb_printf(
 495                 "Machine-check capabilities 0x%016qx:\n", ia32_mcg_cap.u64);
 496
 497         mca_report_cpu_info();
 498
 499         kdb_printf(
 500                 " %d error-reporting banks\n%s%s%s", mca_error_bank_count,
 501                 IF(mca_control_MSR_present,
 502                    " control MSR present\n"),
 503                 IF(mca_threshold_status_present,
 504                    " threshold-based error status present\n"),
 505                 IF(mca_cmci_present,
 506                    " extended corrected memory error handling present\n"));
 507         if (mca_extended_MSRs_present)
 508                 kdb_printf(
 509                         " %d extended MSRs present\n", mca_extended_MSRs_count);
 510
 511         /*
 512          * Dump all processor state:
 513          */
 514         for (i = 0; i < real_ncpus; i++) {
 515                 mca_state_t             *mcsp = cpu_datap(i)->cpu_mca_state;
 516                 ia32_mcg_status_t       status;
 517
 518                 kdb_printf("Processor %d: ", i);
 519                 if (mcsp == NULL ||
 520                     mcsp->mca_is_saved == FALSE ||
 521                     mcsp->mca_mcg_status.u64 == 0) {
 522                         kdb_printf("no machine-check status reported\n");
 523                         continue;
 524                 }
 525                 if (!mcsp->mca_is_valid) {
 526                         kdb_printf("no valid machine-check state\n");
 527                         continue;
 528                 }
 529                 status = mcsp->mca_mcg_status;
 530                 kdb_printf(
 531                         "machine-check status 0x%016qx:\n%s%s%s", status.u64,
 532                         IF(status.bits.ripv, " restart IP valid\n"),
 533                         IF(status.bits.eipv, " error IP valid\n"),
 534                         IF(status.bits.mcip, " machine-check in progress\n"));
 535
 536                 mca_cpu_dump_error_banks(mcsp);
 537         }
 538
 539         /*
 540          * Dump any extended machine state:
 541          */
 542         if (mca_extended_MSRs_present) {
 543                 mca_dump_64bit_state();
 544         }
 545
 546         /* Update state to release any other threads. */
 547         mca_dump_state = DUMPED;
 548 }
 549
 550
 551 extern void mca_exception_panic(void);
 552 extern void mtrr_lapic_cached(void);
 553 void mca_exception_panic(void)
 554 {
 555 #if DEBUG
 556         mtrr_lapic_cached();
 557 #else
 558         kprintf("mca_exception_panic() requires DEBUG build\n");
 559 #endif
 560 }