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[apple/xnu.git] / osfmk / ppc / chud / chud_cpu.c
1 /*
2 * Copyright (c) 2003-2004 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22 #include <mach/mach_types.h>
23 #include <mach/mach_host.h>
24
25 #include <kern/host.h>
26 #include <kern/processor.h>
27
28 #include <ppc/chud/chud_spr.h>
29 #include <ppc/chud/chud_xnu.h>
30 #include <ppc/chud/chud_cpu_asm.h>
31 #include <ppc/machine_routines.h>
32 #include <ppc/exception.h>
33 #include <ppc/hw_perfmon.h>
34 #include <ppc/Diagnostics.h>
35
36 // the macros in proc_reg.h fail with "expression must be absolute"
37
38 #undef mtsprg
39 #undef mfsprg
40 #define mtsprg(n, reg) __asm__ volatile("mtsprg " # n ", %0" : : "r" (reg))
41 #define mfsprg(reg, n) __asm__ volatile("mfsprg %0, " # n : "=r" (reg))
42
43 #undef mtspr
44 #undef mfspr
45 #define mtspr(spr, reg) __asm__ volatile ("mtspr %0, %1" : : "n" (spr), "r" (reg))
46 #define mfspr(reg, spr) __asm__ volatile("mfspr %0, %1" : "=r" (reg) : "n" (spr));
47
48 #undef mtsr
49 #undef mfsr
50 #define mtsr(sr, reg) __asm__ volatile("sync" "@" "mtsr sr%0, %1 " "@" "isync" : : "i" (sr), "r" (reg));
51 #define mfsr(reg, sr) __asm__ volatile("mfsr %0, sr%1" : "=r" (reg) : "i" (sr));
52
53 #pragma mark **** cpu count ****
54
55 __private_extern__
56 int chudxnu_avail_cpu_count(void)
57 {
58 host_basic_info_data_t hinfo;
59 kern_return_t kr;
60 mach_msg_type_number_t count = HOST_BASIC_INFO_COUNT;
61
62 kr = host_info(host_self(), HOST_BASIC_INFO, (integer_t *)&hinfo, &count);
63 if(kr == KERN_SUCCESS) {
64 return hinfo.avail_cpus;
65 } else {
66 return 0;
67 }
68 }
69
70 __private_extern__
71 int chudxnu_phys_cpu_count(void)
72 {
73 host_basic_info_data_t hinfo;
74 kern_return_t kr;
75 mach_msg_type_number_t count = HOST_BASIC_INFO_COUNT;
76
77 kr = host_info(host_self(), HOST_BASIC_INFO, (integer_t *)&hinfo, &count);
78 if(kr == KERN_SUCCESS) {
79 return hinfo.max_cpus;
80 } else {
81 return 0;
82 }
83 }
84
85 __private_extern__
86 int chudxnu_cpu_number(void)
87 {
88 return cpu_number();
89 }
90
91 #pragma mark **** cpu enable/disable ****
92
93 extern kern_return_t processor_start(processor_t processor); // osfmk/kern/processor.c
94 extern kern_return_t processor_exit(processor_t processor); // osfmk/kern/processor.c
95
96 __private_extern__
97 kern_return_t chudxnu_enable_cpu(int cpu, boolean_t enable)
98 {
99 chudxnu_unbind_thread(current_thread());
100
101 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
102 return KERN_FAILURE;
103 }
104
105 if((PerProcTable[cpu].ppe_vaddr != (struct per_proc_info *)NULL)
106 && cpu != master_cpu) {
107 processor_t processor = cpu_to_processor(cpu);
108
109 if(enable) {
110 return processor_start(processor);
111 } else {
112 return processor_exit(processor);
113 }
114 }
115 return KERN_FAILURE;
116 }
117
118 #pragma mark **** nap ****
119
120 __private_extern__
121 kern_return_t chudxnu_enable_cpu_nap(int cpu, boolean_t enable)
122 {
123 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
124 return KERN_FAILURE;
125 }
126
127 if(PerProcTable[cpu].ppe_vaddr != (struct per_proc_info *)NULL) {
128 ml_enable_nap(cpu, enable);
129 return KERN_SUCCESS;
130 }
131
132 return KERN_FAILURE;
133 }
134
135 __private_extern__
136 boolean_t chudxnu_cpu_nap_enabled(int cpu)
137 {
138 boolean_t prev;
139
140 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
141 cpu = 0;
142 }
143
144 prev = ml_enable_nap(cpu, TRUE);
145 ml_enable_nap(cpu, prev);
146
147 return prev;
148 }
149
150 #pragma mark **** shadowed spr ****
151
152 __private_extern__
153 kern_return_t chudxnu_set_shadowed_spr(int cpu, int spr, uint32_t val)
154 {
155 cpu_subtype_t target_cpu_subtype;
156 uint32_t available;
157 kern_return_t retval = KERN_FAILURE;
158 struct per_proc_info *per_proc;
159 boolean_t didBind = FALSE;
160
161 if(cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
162 return KERN_FAILURE;
163 }
164
165 if(cpu<0) { // cpu<0 means don't bind (current cpu)
166 cpu = chudxnu_cpu_number();
167 didBind = FALSE;
168 } else {
169 chudxnu_bind_thread(current_thread(), cpu);
170 didBind = TRUE;
171 }
172
173 per_proc = PerProcTable[cpu].ppe_vaddr;
174 available = per_proc->pf.Available;
175 target_cpu_subtype = per_proc->cpu_subtype;
176
177 if(spr==chud_750_l2cr) {
178 switch(target_cpu_subtype) {
179 case CPU_SUBTYPE_POWERPC_750:
180 case CPU_SUBTYPE_POWERPC_7400:
181 case CPU_SUBTYPE_POWERPC_7450:
182 if(available & pfL2) {
183 // int enable = (val & 0x80000000) ? TRUE : FALSE;
184 // if(enable) {
185 // per_proc->pf.l2cr = val;
186 // } else {
187 // per_proc->pf.l2cr = 0;
188 // }
189 per_proc->pf.l2cr = val;
190 cacheInit();
191 // mtspr(l2cr, per_proc->pf.l2cr); // XXXXXXX why is this necessary? XXXXXXX
192 retval = KERN_SUCCESS;
193 } else {
194 retval = KERN_FAILURE;
195 }
196 break;
197 default:
198 retval = KERN_INVALID_ARGUMENT;
199 break;
200 }
201 }
202 else if(spr==chud_7450_l3cr) {
203 switch(target_cpu_subtype) {
204 case CPU_SUBTYPE_POWERPC_7450:
205 if(available & pfL3) {
206 int enable = (val & 0x80000000) ? TRUE : FALSE;
207 if(enable) {
208 per_proc->pf.l3cr = val;
209 } else {
210 per_proc->pf.l3cr = 0;
211 }
212 cacheInit();
213 retval = KERN_SUCCESS;
214 } else {
215 retval = KERN_FAILURE;
216 }
217 break;
218 default:
219 retval = KERN_INVALID_ARGUMENT;
220 break;
221 }
222 }
223 else if(spr==chud_750_hid0) {
224 switch(target_cpu_subtype) {
225 case CPU_SUBTYPE_POWERPC_750:
226 cacheInit();
227 cacheDisable(); /* disable caches */
228 mtspr(chud_750_hid0, val);
229 per_proc->pf.pfHID0 = val;
230 cacheInit(); /* reenable caches */
231 retval = KERN_SUCCESS;
232 break;
233 case CPU_SUBTYPE_POWERPC_7400:
234 case CPU_SUBTYPE_POWERPC_7450:
235 mtspr(chud_750_hid0, val);
236 per_proc->pf.pfHID0 = val;
237 retval = KERN_SUCCESS;
238 break;
239 default:
240 retval = KERN_INVALID_ARGUMENT;
241 break;
242 }
243 }
244 else if(spr==chud_750_hid1) {
245 switch(target_cpu_subtype) {
246 case CPU_SUBTYPE_POWERPC_750:
247 case CPU_SUBTYPE_POWERPC_7400:
248 case CPU_SUBTYPE_POWERPC_7450:
249 mtspr(chud_750_hid1, val);
250 per_proc->pf.pfHID1 = val;
251 retval = KERN_SUCCESS;
252 break;
253 default:
254 retval = KERN_INVALID_ARGUMENT;
255 break;
256 }
257 }
258 else if(spr==chud_750fx_hid2 && target_cpu_subtype==CPU_SUBTYPE_POWERPC_750) {
259 mtspr(chud_750fx_hid2, val);
260 per_proc->pf.pfHID2 = val;
261 retval = KERN_SUCCESS;
262 }
263 else if(spr==chud_7400_msscr0 && (target_cpu_subtype==CPU_SUBTYPE_POWERPC_7400 || target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450)) {
264 mtspr(chud_7400_msscr0, val);
265 per_proc->pf.pfMSSCR0 = val;
266 retval = KERN_SUCCESS;
267 }
268 else if(spr==chud_7400_msscr1 && (target_cpu_subtype==CPU_SUBTYPE_POWERPC_7400 || target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450)) { // called msssr0 on 7450
269 mtspr(chud_7400_msscr1, val);
270 per_proc->pf.pfMSSCR1 = val;
271 retval = KERN_SUCCESS;
272 }
273 else if(spr==chud_7450_ldstcr && target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450) {
274 mtspr(chud_7450_ldstcr, val);
275 per_proc->pf.pfLDSTCR = val;
276 retval = KERN_SUCCESS;
277 }
278 else if(spr==chud_7450_ictrl && target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450) {
279 mtspr(chud_7450_ictrl, val);
280 per_proc->pf.pfICTRL = val;
281 retval = KERN_SUCCESS;
282 } else {
283 retval = KERN_INVALID_ARGUMENT;
284 }
285
286 if(didBind) {
287 chudxnu_unbind_thread(current_thread());
288 }
289
290 return retval;
291 }
292
293 __private_extern__
294 kern_return_t chudxnu_set_shadowed_spr64(int cpu, int spr, uint64_t val)
295 {
296 cpu_subtype_t target_cpu_subtype;
297 kern_return_t retval = KERN_FAILURE;
298 struct per_proc_info *per_proc;
299 boolean_t didBind = FALSE;
300
301 if(cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
302 return KERN_FAILURE;
303 }
304
305 if(cpu<0) { // cpu<0 means don't bind (current cpu)
306 cpu = chudxnu_cpu_number();
307 didBind = FALSE;
308 } else {
309 chudxnu_bind_thread(current_thread(), cpu);
310 didBind = TRUE;
311 }
312
313 per_proc = PerProcTable[cpu].ppe_vaddr;
314 target_cpu_subtype = per_proc->cpu_subtype;
315
316 if(spr==chud_970_hid0) {
317 switch(target_cpu_subtype) {
318 case CPU_SUBTYPE_POWERPC_970:
319 mtspr64(chud_970_hid0, &val);
320 per_proc->pf.pfHID0 = val;
321 retval = KERN_SUCCESS;
322 break;
323 default:
324 retval = KERN_INVALID_ARGUMENT;
325 break;
326 }
327 }
328 else if(spr==chud_970_hid1) {
329 switch(target_cpu_subtype) {
330 case CPU_SUBTYPE_POWERPC_970:
331 mtspr64(chud_970_hid1, &val);
332 per_proc->pf.pfHID1 = val;
333 retval = KERN_SUCCESS;
334 break;
335 default:
336 retval = KERN_INVALID_ARGUMENT;
337 break;
338 }
339 }
340 else if(spr==chud_970_hid4) {
341 switch(target_cpu_subtype) {
342 case CPU_SUBTYPE_POWERPC_970:
343 mtspr64(chud_970_hid4, &val);
344 per_proc->pf.pfHID4 = val;
345 retval = KERN_SUCCESS;
346 break;
347 default:
348 retval = KERN_INVALID_ARGUMENT;
349 break;
350 }
351 }
352 else if(spr==chud_970_hid5) {
353 switch(target_cpu_subtype) {
354 case CPU_SUBTYPE_POWERPC_970:
355 mtspr64(chud_970_hid5, &val);
356 per_proc->pf.pfHID5 = val;
357 retval = KERN_SUCCESS;
358 break;
359 default:
360 retval = KERN_INVALID_ARGUMENT;
361 break;
362 }
363 } else {
364 retval = KERN_INVALID_ARGUMENT;
365 }
366
367 if(didBind) {
368 chudxnu_unbind_thread(current_thread());
369 }
370
371 return retval;
372 }
373
374 __private_extern__
375 uint32_t chudxnu_get_orig_cpu_l2cr(int cpu)
376 {
377 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
378 cpu = 0;
379 }
380 return PerProcTable[cpu].ppe_vaddr->pf.l2crOriginal;
381 }
382
383 __private_extern__
384 uint32_t chudxnu_get_orig_cpu_l3cr(int cpu)
385 {
386 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
387 cpu = 0;
388 }
389 return PerProcTable[cpu].ppe_vaddr->pf.l3crOriginal;
390 }
391
392 #pragma mark **** spr ****
393
394 __private_extern__
395 kern_return_t chudxnu_read_spr(int cpu, int spr, uint32_t *val_p)
396 {
397 kern_return_t retval = KERN_SUCCESS;
398 boolean_t oldlevel;
399 uint32_t val = 0xFFFFFFFF;
400
401 /* bind to requested CPU */
402 if(cpu>=0) { // cpu<0 means don't bind
403 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
404 return KERN_INVALID_ARGUMENT;
405 }
406 }
407
408 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
409
410 do {
411 /* PPC SPRs - 32-bit and 64-bit implementations */
412 if(spr==chud_ppc_srr0) { mfspr(val, chud_ppc_srr0); break; }
413 if(spr==chud_ppc_srr1) { mfspr(val, chud_ppc_srr1); break; }
414 if(spr==chud_ppc_dsisr) { mfspr(val, chud_ppc_dsisr); break; }
415 if(spr==chud_ppc_dar) { mfspr(val, chud_ppc_dar); break; }
416 if(spr==chud_ppc_dec) { mfspr(val, chud_ppc_dec); break; }
417 if(spr==chud_ppc_sdr1) { mfspr(val, chud_ppc_sdr1); break; }
418 if(spr==chud_ppc_sprg0) { mfspr(val, chud_ppc_sprg0); break; }
419 if(spr==chud_ppc_sprg1) { mfspr(val, chud_ppc_sprg1); break; }
420 if(spr==chud_ppc_sprg2) { mfspr(val, chud_ppc_sprg2); break; }
421 if(spr==chud_ppc_sprg3) { mfspr(val, chud_ppc_sprg3); break; }
422 if(spr==chud_ppc_ear) { mfspr(val, chud_ppc_ear); break; }
423 if(spr==chud_ppc_tbl) { mfspr(val, 268); break; } /* timebase consists of read registers and write registers */
424 if(spr==chud_ppc_tbu) { mfspr(val, 269); break; }
425 if(spr==chud_ppc_pvr) { mfspr(val, chud_ppc_pvr); break; }
426 if(spr==chud_ppc_ibat0u) { mfspr(val, chud_ppc_ibat0u); break; }
427 if(spr==chud_ppc_ibat0l) { mfspr(val, chud_ppc_ibat0l); break; }
428 if(spr==chud_ppc_ibat1u) { mfspr(val, chud_ppc_ibat1u); break; }
429 if(spr==chud_ppc_ibat1l) { mfspr(val, chud_ppc_ibat1l); break; }
430 if(spr==chud_ppc_ibat2u) { mfspr(val, chud_ppc_ibat2u); break; }
431 if(spr==chud_ppc_ibat2l) { mfspr(val, chud_ppc_ibat2l); break; }
432 if(spr==chud_ppc_ibat3u) { mfspr(val, chud_ppc_ibat3u); break; }
433 if(spr==chud_ppc_ibat3l) { mfspr(val, chud_ppc_ibat3l); break; }
434 if(spr==chud_ppc_dbat0u) { mfspr(val, chud_ppc_dbat0u); break; }
435 if(spr==chud_ppc_dbat0l) { mfspr(val, chud_ppc_dbat0l); break; }
436 if(spr==chud_ppc_dbat1u) { mfspr(val, chud_ppc_dbat1u); break; }
437 if(spr==chud_ppc_dbat1l) { mfspr(val, chud_ppc_dbat1l); break; }
438 if(spr==chud_ppc_dbat2u) { mfspr(val, chud_ppc_dbat2u); break; }
439 if(spr==chud_ppc_dbat2l) { mfspr(val, chud_ppc_dbat2l); break; }
440 if(spr==chud_ppc_dbat3u) { mfspr(val, chud_ppc_dbat3u); break; }
441 if(spr==chud_ppc_dbat3l) { mfspr(val, chud_ppc_dbat3l); break; }
442 if(spr==chud_ppc_dabr) { mfspr(val, chud_ppc_dabr); break; }
443 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
444 struct ppc_thread_state64 state;
445 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
446 kern_return_t kr;
447 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
448 if(KERN_SUCCESS==kr) {
449 val = state.srr1;
450 } else {
451 retval = KERN_FAILURE;
452 }
453 break;
454 }
455
456 /* PPC SPRs - 32-bit implementations */
457 if(spr==chud_ppc32_sr0) { mfsr(val, 0); break; }
458 if(spr==chud_ppc32_sr1) { mfsr(val, 1); break; }
459 if(spr==chud_ppc32_sr2) { mfsr(val, 2); break; }
460 if(spr==chud_ppc32_sr3) { mfsr(val, 3); break; }
461 if(spr==chud_ppc32_sr4) { mfsr(val, 4); break; }
462 if(spr==chud_ppc32_sr5) { mfsr(val, 5); break; }
463 if(spr==chud_ppc32_sr6) { mfsr(val, 6); break; }
464 if(spr==chud_ppc32_sr7) { mfsr(val, 7); break; }
465 if(spr==chud_ppc32_sr8) { mfsr(val, 8); break; }
466 if(spr==chud_ppc32_sr9) { mfsr(val, 9); break; }
467 if(spr==chud_ppc32_sr10) { mfsr(val, 10); break; }
468 if(spr==chud_ppc32_sr11) { mfsr(val, 11); break; }
469 if(spr==chud_ppc32_sr12) { mfsr(val, 12); break; }
470 if(spr==chud_ppc32_sr13) { mfsr(val, 13); break; }
471 if(spr==chud_ppc32_sr14) { mfsr(val, 14); break; }
472 if(spr==chud_ppc32_sr15) { mfsr(val, 15); break; }
473
474 /* PPC SPRs - 64-bit implementations */
475 if(spr==chud_ppc64_ctrl) { mfspr(val, chud_ppc64_ctrl); break; }
476
477 /* Implementation Specific SPRs */
478 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_750) {
479 if(spr==chud_750_mmcr0) { mfspr(val, chud_750_mmcr0); break; }
480 if(spr==chud_750_pmc1) { mfspr(val, chud_750_pmc1); break; }
481 if(spr==chud_750_pmc2) { mfspr(val, chud_750_pmc2); break; }
482 if(spr==chud_750_sia) { mfspr(val, chud_750_sia); break; }
483 if(spr==chud_750_mmcr1) { mfspr(val, chud_750_mmcr1); break; }
484 if(spr==chud_750_pmc3) { mfspr(val, chud_750_pmc3); break; }
485 if(spr==chud_750_pmc4) { mfspr(val, chud_750_pmc4); break; }
486 if(spr==chud_750_hid0) { mfspr(val, chud_750_hid0); break; }
487 if(spr==chud_750_hid1) { mfspr(val, chud_750_hid1); break; }
488 if(spr==chud_750_iabr) { mfspr(val, chud_750_iabr); break; }
489 if(spr==chud_750_ictc) { mfspr(val, chud_750_ictc); break; }
490 if(spr==chud_750_thrm1) { mfspr(val, chud_750_thrm1); break; }
491 if(spr==chud_750_thrm2) { mfspr(val, chud_750_thrm2); break; }
492 if(spr==chud_750_thrm3) { mfspr(val, chud_750_thrm3); break; }
493 if(spr==chud_750_l2cr) { mfspr(val, chud_750_l2cr); break; }
494
495 // 750FX only
496 if(spr==chud_750fx_ibat4u) { mfspr(val, chud_750fx_ibat4u); break; }
497 if(spr==chud_750fx_ibat4l) { mfspr(val, chud_750fx_ibat4l); break; }
498 if(spr==chud_750fx_ibat5u) { mfspr(val, chud_750fx_ibat5u); break; }
499 if(spr==chud_750fx_ibat5l) { mfspr(val, chud_750fx_ibat5l); break; }
500 if(spr==chud_750fx_ibat6u) { mfspr(val, chud_750fx_ibat6u); break; }
501 if(spr==chud_750fx_ibat6l) { mfspr(val, chud_750fx_ibat6l); break; }
502 if(spr==chud_750fx_ibat7u) { mfspr(val, chud_750fx_ibat7u); break; }
503 if(spr==chud_750fx_ibat7l) { mfspr(val, chud_750fx_ibat7l); break; }
504 if(spr==chud_750fx_dbat4u) { mfspr(val, chud_750fx_dbat4u); break; }
505 if(spr==chud_750fx_dbat4l) { mfspr(val, chud_750fx_dbat4l); break; }
506 if(spr==chud_750fx_dbat5u) { mfspr(val, chud_750fx_dbat5u); break; }
507 if(spr==chud_750fx_dbat5l) { mfspr(val, chud_750fx_dbat5l); break; }
508 if(spr==chud_750fx_dbat6u) { mfspr(val, chud_750fx_dbat6u); break; }
509 if(spr==chud_750fx_dbat6l) { mfspr(val, chud_750fx_dbat6l); break; }
510 if(spr==chud_750fx_dbat7u) { mfspr(val, chud_750fx_dbat7u); break; }
511 if(spr==chud_750fx_dbat7l) { mfspr(val, chud_750fx_dbat7l); break; }
512
513 // 750FX >= DDR2.x only
514 if(spr==chud_750fx_hid2) { mfspr(val, chud_750fx_hid2); break; }
515 }
516
517 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7400) {
518 if(spr==chud_7400_mmcr2) { mfspr(val, chud_7400_mmcr2); break; }
519 if(spr==chud_7400_bamr) { mfspr(val, chud_7400_bamr); break; }
520 if(spr==chud_7400_mmcr0) { mfspr(val, chud_7400_mmcr0); break; }
521 if(spr==chud_7400_pmc1) { mfspr(val, chud_7400_pmc1); break; }
522 if(spr==chud_7400_pmc2) { mfspr(val, chud_7400_pmc2); break; }
523 if(spr==chud_7400_siar) { mfspr(val, chud_7400_siar); break; }
524 if(spr==chud_7400_mmcr1) { mfspr(val, chud_7400_mmcr1); break; }
525 if(spr==chud_7400_pmc3) { mfspr(val, chud_7400_pmc3); break; }
526 if(spr==chud_7400_pmc4) { mfspr(val, chud_7400_pmc4); break; }
527 if(spr==chud_7400_hid0) { mfspr(val, chud_7400_hid0); break; }
528 if(spr==chud_7400_hid1) { mfspr(val, chud_7400_hid1); break; }
529 if(spr==chud_7400_iabr) { mfspr(val, chud_7400_iabr); break; }
530 if(spr==chud_7400_msscr0) { mfspr(val, chud_7400_msscr0); break; }
531 if(spr==chud_7400_msscr1) { mfspr(val, chud_7400_msscr1); break; } /* private */
532 if(spr==chud_7400_ictc) { mfspr(val, chud_7400_ictc); break; }
533 if(spr==chud_7400_thrm1) { mfspr(val, chud_7400_thrm1); break; }
534 if(spr==chud_7400_thrm2) { mfspr(val, chud_7400_thrm2); break; }
535 if(spr==chud_7400_thrm3) { mfspr(val, chud_7400_thrm3); break; }
536 if(spr==chud_7400_pir) { mfspr(val, chud_7400_pir); break; }
537 if(spr==chud_7400_l2cr) { mfspr(val, chud_7400_l2cr); break; }
538
539 // 7410 only
540 if(spr==chud_7410_l2pmcr) { mfspr(val, chud_7410_l2pmcr); break; }
541 }
542
543 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7450) {
544 if(spr==chud_7450_mmcr2) { mfspr(val, chud_7450_mmcr2); break; }
545 if(spr==chud_7450_pmc5) { mfspr(val, chud_7450_pmc5); break; }
546 if(spr==chud_7450_pmc6) { mfspr(val, chud_7450_pmc6); break; }
547 if(spr==chud_7450_bamr) { mfspr(val, chud_7450_bamr); break; }
548 if(spr==chud_7450_mmcr0) { mfspr(val, chud_7450_mmcr0); break; }
549 if(spr==chud_7450_pmc1) { mfspr(val, chud_7450_pmc1); break; }
550 if(spr==chud_7450_pmc2) { mfspr(val, chud_7450_pmc2); break; }
551 if(spr==chud_7450_siar) { mfspr(val, chud_7450_siar); break; }
552 if(spr==chud_7450_mmcr1) { mfspr(val, chud_7450_mmcr1); break; }
553 if(spr==chud_7450_pmc3) { mfspr(val, chud_7450_pmc3); break; }
554 if(spr==chud_7450_pmc4) { mfspr(val, chud_7450_pmc4); break; }
555 if(spr==chud_7450_tlbmiss) { mfspr(val, chud_7450_tlbmiss); break; }
556 if(spr==chud_7450_ptehi) { mfspr(val, chud_7450_ptehi); break; }
557 if(spr==chud_7450_ptelo) { mfspr(val, chud_7450_ptelo); break; }
558 if(spr==chud_7450_l3pm) { mfspr(val, chud_7450_l3pm); break; }
559 if(spr==chud_7450_hid0) { mfspr(val, chud_7450_hid0); break; }
560 if(spr==chud_7450_hid1) { mfspr(val, chud_7450_hid1); break; }
561 if(spr==chud_7450_iabr) { mfspr(val, chud_7450_iabr); break; }
562 if(spr==chud_7450_ldstdb) { mfspr(val, chud_7450_ldstdb); break; }
563 if(spr==chud_7450_msscr0) { mfspr(val, chud_7450_msscr0); break; }
564 if(spr==chud_7450_msssr0) { mfspr(val, chud_7450_msssr0); break; }
565 if(spr==chud_7450_ldstcr) { mfspr(val, chud_7450_ldstcr); break; }
566 if(spr==chud_7450_ictc) { mfspr(val, chud_7450_ictc); break; }
567 if(spr==chud_7450_ictrl) { mfspr(val, chud_7450_ictrl); break; }
568 if(spr==chud_7450_thrm1) { mfspr(val, chud_7450_thrm1); break; }
569 if(spr==chud_7450_thrm2) { mfspr(val, chud_7450_thrm2); break; }
570 if(spr==chud_7450_thrm3) { mfspr(val, chud_7450_thrm3); break; }
571 if(spr==chud_7450_pir) { mfspr(val, chud_7450_pir); break; }
572 if(spr==chud_7450_l2cr) { mfspr(val, chud_7450_l2cr); break; }
573 if(spr==chud_7450_l3cr) { mfspr(val, chud_7450_l3cr); break; }
574
575 // 7455/7457 only
576 if(spr==chud_7455_sprg4) { mfspr(val, chud_7455_sprg4); break; }
577 if(spr==chud_7455_sprg5) { mfspr(val, chud_7455_sprg5); break; }
578 if(spr==chud_7455_sprg6) { mfspr(val, chud_7455_sprg6); break; }
579 if(spr==chud_7455_sprg7) { mfspr(val, chud_7455_sprg7); break; }
580 if(spr==chud_7455_ibat4u) { mfspr(val, chud_7455_ibat4u); break; }
581 if(spr==chud_7455_ibat4l) { mfspr(val, chud_7455_ibat4l); break; }
582 if(spr==chud_7455_ibat5u) { mfspr(val, chud_7455_ibat5u); break; }
583 if(spr==chud_7455_ibat5l) { mfspr(val, chud_7455_ibat5l); break; }
584 if(spr==chud_7455_ibat6u) { mfspr(val, chud_7455_ibat6u); break; }
585 if(spr==chud_7455_ibat6l) { mfspr(val, chud_7455_ibat6l); break; }
586 if(spr==chud_7455_ibat7u) { mfspr(val, chud_7455_ibat7u); break; }
587 if(spr==chud_7455_ibat7l) { mfspr(val, chud_7455_ibat7l); break; }
588 if(spr==chud_7455_dbat4u) { mfspr(val, chud_7455_dbat4u); break; }
589 if(spr==chud_7455_dbat4l) { mfspr(val, chud_7455_dbat4l); break; }
590 if(spr==chud_7455_dbat5u) { mfspr(val, chud_7455_dbat5u); break; }
591 if(spr==chud_7455_dbat5l) { mfspr(val, chud_7455_dbat5l); break; }
592 if(spr==chud_7455_dbat6u) { mfspr(val, chud_7455_dbat6u); break; }
593 if(spr==chud_7455_dbat6l) { mfspr(val, chud_7455_dbat6l); break; }
594 if(spr==chud_7455_dbat7u) { mfspr(val, chud_7455_dbat7u); break; }
595 if(spr==chud_7455_dbat7l) { mfspr(val, chud_7455_dbat7l); break; }
596 }
597
598 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
599 if(spr==chud_970_pir) { mfspr(val, chud_970_pir); break; }
600 if(spr==chud_970_pmc1) { mfspr(val, chud_970_pmc1); break; }
601 if(spr==chud_970_pmc2) { mfspr(val, chud_970_pmc2); break; }
602 if(spr==chud_970_pmc3) { mfspr(val, chud_970_pmc3); break; }
603 if(spr==chud_970_pmc4) { mfspr(val, chud_970_pmc4); break; }
604 if(spr==chud_970_pmc5) { mfspr(val, chud_970_pmc5); break; }
605 if(spr==chud_970_pmc6) { mfspr(val, chud_970_pmc6); break; }
606 if(spr==chud_970_pmc7) { mfspr(val, chud_970_pmc7); break; }
607 if(spr==chud_970_pmc8) { mfspr(val, chud_970_pmc8); break; }
608 if(spr==chud_970_hdec) { mfspr(val, chud_970_hdec); break; }
609 }
610
611 /* we only get here if none of the above cases qualify */
612 retval = KERN_INVALID_ARGUMENT;
613 } while(0);
614
615 chudxnu_set_interrupts_enabled(oldlevel); /* enable interrupts */
616
617 if(cpu>=0) { // cpu<0 means don't bind
618 chudxnu_unbind_thread(current_thread());
619 }
620
621 *val_p = val;
622
623 return retval;
624 }
625
626 __private_extern__
627 kern_return_t chudxnu_read_spr64(int cpu, int spr, uint64_t *val_p)
628 {
629 kern_return_t retval = KERN_SUCCESS;
630 boolean_t oldlevel;
631
632 /* bind to requested CPU */
633 if(cpu>=0) { // cpu<0 means don't bind
634 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
635 return KERN_INVALID_ARGUMENT;
636 }
637 }
638
639 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
640
641 do {
642 /* PPC SPRs - 32-bit and 64-bit implementations */
643 if(spr==chud_ppc_srr0) { retval = mfspr64(val_p, chud_ppc_srr0); break; }
644 if(spr==chud_ppc_srr1) { retval = mfspr64(val_p, chud_ppc_srr1); break; }
645 if(spr==chud_ppc_dar) { retval = mfspr64(val_p, chud_ppc_dar); break; }
646 if(spr==chud_ppc_dsisr) { retval = mfspr64(val_p, chud_ppc_dsisr); break; }
647 if(spr==chud_ppc_sdr1) { retval = mfspr64(val_p, chud_ppc_sdr1); break; }
648 if(spr==chud_ppc_sprg0) { retval = mfspr64(val_p, chud_ppc_sprg0); break; }
649 if(spr==chud_ppc_sprg1) { retval = mfspr64(val_p, chud_ppc_sprg1); break; }
650 if(spr==chud_ppc_sprg2) { retval = mfspr64(val_p, chud_ppc_sprg2); break; }
651 if(spr==chud_ppc_sprg3) { retval = mfspr64(val_p, chud_ppc_sprg3); break; }
652 if(spr==chud_ppc_dabr) { retval = mfspr64(val_p, chud_ppc_dabr); break; }
653 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
654 struct ppc_thread_state64 state;
655 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
656 kern_return_t kr;
657 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
658 if(KERN_SUCCESS==kr) {
659 *val_p = state.srr1;
660 } else {
661 retval = KERN_FAILURE;
662 }
663 break;
664 }
665
666 /* PPC SPRs - 64-bit implementations */
667 if(spr==chud_ppc64_asr) { retval = mfspr64(val_p, chud_ppc64_asr); break; }
668 if(spr==chud_ppc64_accr) { retval = mfspr64(val_p, chud_ppc64_accr); break; }
669
670 /* Implementation Specific SPRs */
671 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
672 if(spr==chud_970_hid0) { retval = mfspr64(val_p, chud_970_hid0); break; }
673 if(spr==chud_970_hid1) { retval = mfspr64(val_p, chud_970_hid1); break; }
674 if(spr==chud_970_hid4) { retval = mfspr64(val_p, chud_970_hid4); break; }
675 if(spr==chud_970_hid5) { retval = mfspr64(val_p, chud_970_hid5); break; }
676 if(spr==chud_970_mmcr0) { retval = mfspr64(val_p, chud_970_mmcr0); break; }
677 if(spr==chud_970_mmcr1) { retval = mfspr64(val_p, chud_970_mmcr1); break; }
678 if(spr==chud_970_mmcra) { retval = mfspr64(val_p, chud_970_mmcra); break; }
679 if(spr==chud_970_siar) { retval = mfspr64(val_p, chud_970_siar); break; }
680 if(spr==chud_970_sdar) { retval = mfspr64(val_p, chud_970_sdar); break; }
681 if(spr==chud_970_imc) { retval = mfspr64(val_p, chud_970_imc); break; }
682 if(spr==chud_970_rmor) { retval = mfspr64(val_p, chud_970_rmor); break; }
683 if(spr==chud_970_hrmor) { retval = mfspr64(val_p, chud_970_hrmor); break; }
684 if(spr==chud_970_hior) { retval = mfspr64(val_p, chud_970_hior); break; }
685 if(spr==chud_970_lpidr) { retval = mfspr64(val_p, chud_970_lpidr); break; }
686 if(spr==chud_970_lpcr) { retval = mfspr64(val_p, chud_970_lpcr); break; }
687 if(spr==chud_970_dabrx) { retval = mfspr64(val_p, chud_970_dabrx); break; }
688 if(spr==chud_970_hsprg0) { retval = mfspr64(val_p, chud_970_hsprg0); break; }
689 if(spr==chud_970_hsprg1) { retval = mfspr64(val_p, chud_970_hsprg1); break; }
690 if(spr==chud_970_hsrr0) { retval = mfspr64(val_p, chud_970_hsrr0); break; }
691 if(spr==chud_970_hsrr1) { retval = mfspr64(val_p, chud_970_hsrr1); break; }
692 if(spr==chud_970_hdec) { retval = mfspr64(val_p, chud_970_hdec); break; }
693 if(spr==chud_970_trig0) { retval = mfspr64(val_p, chud_970_trig0); break; }
694 if(spr==chud_970_trig1) { retval = mfspr64(val_p, chud_970_trig1); break; }
695 if(spr==chud_970_trig2) { retval = mfspr64(val_p, chud_970_trig2); break; }
696 if(spr==chud_970_scomc) { retval = mfspr64(val_p, chud_970_scomc); break; }
697 if(spr==chud_970_scomd) { retval = mfspr64(val_p, chud_970_scomd); break; }
698 }
699
700 /* we only get here if none of the above cases qualify */
701 *val_p = 0xFFFFFFFFFFFFFFFFLL;
702 retval = KERN_INVALID_ARGUMENT;
703 } while(0);
704
705 chudxnu_set_interrupts_enabled(oldlevel); /* enable interrupts */
706
707 if(cpu>=0) { // cpu<0 means don't bind
708 chudxnu_unbind_thread(current_thread());
709 }
710
711 return retval;
712 }
713
714 __private_extern__
715 kern_return_t chudxnu_write_spr(int cpu, int spr, uint32_t val)
716 {
717 kern_return_t retval = KERN_SUCCESS;
718 boolean_t oldlevel;
719
720 /* bind to requested CPU */
721 if(cpu>=0) { // cpu<0 means don't bind
722 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
723 return KERN_INVALID_ARGUMENT;
724 }
725 }
726
727 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
728
729 do {
730 /* PPC SPRs - 32-bit and 64-bit implementations */
731 if(spr==chud_ppc_srr0) { mtspr(chud_ppc_srr0, val); break; }
732 if(spr==chud_ppc_srr1) { mtspr(chud_ppc_srr1, val); break; }
733 if(spr==chud_ppc_dsisr) { mtspr(chud_ppc_dsisr, val); break; }
734 if(spr==chud_ppc_dar) { mtspr(chud_ppc_dar, val); break; }
735 if(spr==chud_ppc_dec) { mtspr(chud_ppc_dec, val); break; }
736 if(spr==chud_ppc_sdr1) { mtspr(chud_ppc_sdr1, val); break; }
737 if(spr==chud_ppc_sprg0) { mtspr(chud_ppc_sprg0, val); break; }
738 if(spr==chud_ppc_sprg1) { mtspr(chud_ppc_sprg1, val); break; }
739 if(spr==chud_ppc_sprg2) { mtspr(chud_ppc_sprg2, val); break; }
740 if(spr==chud_ppc_sprg3) { mtspr(chud_ppc_sprg3, val); break; }
741 if(spr==chud_ppc_ear) { mtspr(chud_ppc_ear, val); break; }
742 if(spr==chud_ppc_tbl) { mtspr(284, val); break; } /* timebase consists of read registers and write registers */
743 if(spr==chud_ppc_tbu) { mtspr(285, val); break; }
744 if(spr==chud_ppc_pvr) { mtspr(chud_ppc_pvr, val); break; }
745 if(spr==chud_ppc_ibat0u) { mtspr(chud_ppc_ibat0u, val); break; }
746 if(spr==chud_ppc_ibat0l) { mtspr(chud_ppc_ibat0l, val); break; }
747 if(spr==chud_ppc_ibat1u) { mtspr(chud_ppc_ibat1u, val); break; }
748 if(spr==chud_ppc_ibat1l) { mtspr(chud_ppc_ibat1l, val); break; }
749 if(spr==chud_ppc_ibat2u) { mtspr(chud_ppc_ibat2u, val); break; }
750 if(spr==chud_ppc_ibat2l) { mtspr(chud_ppc_ibat2l, val); break; }
751 if(spr==chud_ppc_ibat3u) { mtspr(chud_ppc_ibat3u, val); break; }
752 if(spr==chud_ppc_ibat3l) { mtspr(chud_ppc_ibat3l, val); break; }
753 if(spr==chud_ppc_dbat0u) { mtspr(chud_ppc_dbat0u, val); break; }
754 if(spr==chud_ppc_dbat0l) { mtspr(chud_ppc_dbat0l, val); break; }
755 if(spr==chud_ppc_dbat1u) { mtspr(chud_ppc_dbat1u, val); break; }
756 if(spr==chud_ppc_dbat1l) { mtspr(chud_ppc_dbat1l, val); break; }
757 if(spr==chud_ppc_dbat2u) { mtspr(chud_ppc_dbat2u, val); break; }
758 if(spr==chud_ppc_dbat2l) { mtspr(chud_ppc_dbat2l, val); break; }
759 if(spr==chud_ppc_dbat3u) { mtspr(chud_ppc_dbat3u, val); break; }
760 if(spr==chud_ppc_dbat3l) { mtspr(chud_ppc_dbat3l, val); break; }
761 if(spr==chud_ppc_dabr) { mtspr(chud_ppc_dabr, val); break; }
762 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
763 struct ppc_thread_state64 state;
764 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
765 kern_return_t kr;
766 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
767 if(KERN_SUCCESS==kr) {
768 state.srr1 = val;
769 kr = chudxnu_thread_set_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, count, TRUE /* user only */);
770 if(KERN_SUCCESS!=kr) {
771 retval = KERN_FAILURE;
772 }
773 } else {
774 retval = KERN_FAILURE;
775 }
776 break;
777 }
778
779 /* PPC SPRs - 32-bit implementations */
780 if(spr==chud_ppc32_sr0) { mtsr(0, val); break; }
781 if(spr==chud_ppc32_sr1) { mtsr(1, val); break; }
782 if(spr==chud_ppc32_sr2) { mtsr(2, val); break; }
783 if(spr==chud_ppc32_sr3) { mtsr(3, val); break; }
784 if(spr==chud_ppc32_sr4) { mtsr(4, val); break; }
785 if(spr==chud_ppc32_sr5) { mtsr(5, val); break; }
786 if(spr==chud_ppc32_sr6) { mtsr(6, val); break; }
787 if(spr==chud_ppc32_sr7) { mtsr(7, val); break; }
788 if(spr==chud_ppc32_sr8) { mtsr(8, val); break; }
789 if(spr==chud_ppc32_sr9) { mtsr(9, val); break; }
790 if(spr==chud_ppc32_sr10) { mtsr(10, val); break; }
791 if(spr==chud_ppc32_sr11) { mtsr(11, val); break; }
792 if(spr==chud_ppc32_sr12) { mtsr(12, val); break; }
793 if(spr==chud_ppc32_sr13) { mtsr(13, val); break; }
794 if(spr==chud_ppc32_sr14) { mtsr(14, val); break; }
795 if(spr==chud_ppc32_sr15) { mtsr(15, val); break; }
796
797 /* Implementation Specific SPRs */
798 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_750) {
799 if(spr==chud_750_mmcr0) { mtspr(chud_750_mmcr0, val); break; }
800 if(spr==chud_750_pmc1) { mtspr(chud_750_pmc1, val); break; }
801 if(spr==chud_750_pmc2) { mtspr(chud_750_pmc2, val); break; }
802 if(spr==chud_750_sia) { mtspr(chud_750_sia, val); break; }
803 if(spr==chud_750_mmcr1) { mtspr(chud_750_mmcr1, val); break; }
804 if(spr==chud_750_pmc3) { mtspr(chud_750_pmc3, val); break; }
805 if(spr==chud_750_pmc4) { mtspr(chud_750_pmc4, val); break; }
806 if(spr==chud_750_iabr) { mtspr(chud_750_iabr, val); break; }
807 if(spr==chud_750_ictc) { mtspr(chud_750_ictc, val); break; }
808 if(spr==chud_750_thrm1) { mtspr(chud_750_thrm1, val); break; }
809 if(spr==chud_750_thrm2) { mtspr(chud_750_thrm2, val); break; }
810 if(spr==chud_750_thrm3) { mtspr(chud_750_thrm3, val); break; }
811 if(spr==chud_750_l2cr) {
812 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
813 break;
814 }
815 if(spr==chud_750_hid0) {
816 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
817 break;
818 }
819 if(spr==chud_750_hid1) {
820 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
821 break;
822 }
823
824 // 750FX only
825 if(spr==chud_750fx_ibat4u) { mtspr(chud_750fx_ibat4u, val); break; }
826 if(spr==chud_750fx_ibat4l) { mtspr(chud_750fx_ibat4l, val); break; }
827 if(spr==chud_750fx_ibat5u) { mtspr(chud_750fx_ibat5u, val); break; }
828 if(spr==chud_750fx_ibat5l) { mtspr(chud_750fx_ibat5l, val); break; }
829 if(spr==chud_750fx_ibat6u) { mtspr(chud_750fx_ibat6u, val); break; }
830 if(spr==chud_750fx_ibat6l) { mtspr(chud_750fx_ibat6l, val); break; }
831 if(spr==chud_750fx_ibat7u) { mtspr(chud_750fx_ibat7u, val); break; }
832 if(spr==chud_750fx_ibat7l) { mtspr(chud_750fx_ibat7l, val); break; }
833 if(spr==chud_750fx_dbat4u) { mtspr(chud_750fx_dbat4u, val); break; }
834 if(spr==chud_750fx_dbat4l) { mtspr(chud_750fx_dbat4l, val); break; }
835 if(spr==chud_750fx_dbat5u) { mtspr(chud_750fx_dbat5u, val); break; }
836 if(spr==chud_750fx_dbat5l) { mtspr(chud_750fx_dbat5l, val); break; }
837 if(spr==chud_750fx_dbat6u) { mtspr(chud_750fx_dbat6u, val); break; }
838 if(spr==chud_750fx_dbat6l) { mtspr(chud_750fx_dbat6l, val); break; }
839 if(spr==chud_750fx_dbat7u) { mtspr(chud_750fx_dbat7u, val); break; }
840 if(spr==chud_750fx_dbat7l) { mtspr(chud_750fx_dbat7l, val); break; }
841
842 // 750FX >= DDR2.x
843 if(spr==chud_750fx_hid2) { mtspr(chud_750fx_hid2, val); break; }
844 }
845
846 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7400) {
847 if(spr==chud_7400_mmcr2) { mtspr(chud_7400_mmcr2, val); break; }
848 if(spr==chud_7400_bamr) { mtspr(chud_7400_bamr, val); break; }
849 if(spr==chud_7400_mmcr0) { mtspr(chud_7400_mmcr0, val); break; }
850 if(spr==chud_7400_pmc1) { mtspr(chud_7400_pmc1, val); break; }
851 if(spr==chud_7400_pmc2) { mtspr(chud_7400_pmc2, val); break; }
852 if(spr==chud_7400_siar) { mtspr(chud_7400_siar, val); break; }
853 if(spr==chud_7400_mmcr1) { mtspr(chud_7400_mmcr1, val); break; }
854 if(spr==chud_7400_pmc3) { mtspr(chud_7400_pmc3, val); break; }
855 if(spr==chud_7400_pmc4) { mtspr(chud_7400_pmc4, val); break; }
856 if(spr==chud_7400_iabr) { mtspr(chud_7400_iabr, val); break; }
857 if(spr==chud_7400_ictc) { mtspr(chud_7400_ictc, val); break; }
858 if(spr==chud_7400_thrm1) { mtspr(chud_7400_thrm1, val); break; }
859 if(spr==chud_7400_thrm2) { mtspr(chud_7400_thrm2, val); break; }
860 if(spr==chud_7400_thrm3) { mtspr(chud_7400_thrm3, val); break; }
861 if(spr==chud_7400_pir) { mtspr(chud_7400_pir, val); break; }
862
863 if(spr==chud_7400_l2cr) {
864 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
865 break;
866 }
867 if(spr==chud_7400_hid0) {
868 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
869 break;
870 }
871 if(spr==chud_7400_hid1) {
872 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
873 break;
874 }
875 if(spr==chud_7400_msscr0) {
876 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
877 break;
878 }
879 if(spr==chud_7400_msscr1) { /* private */
880 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
881 break;
882 }
883
884 // 7410 only
885 if(spr==chud_7410_l2pmcr) { mtspr(chud_7410_l2pmcr, val); break; }
886 }
887
888 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7450) {
889 if(spr==chud_7450_mmcr2) { mtspr(chud_7450_mmcr2, val); break; }
890 if(spr==chud_7450_pmc5) { mtspr(chud_7450_pmc5, val); break; }
891 if(spr==chud_7450_pmc6) { mtspr(chud_7450_pmc6, val); break; }
892 if(spr==chud_7450_bamr) { mtspr(chud_7450_bamr, val); break; }
893 if(spr==chud_7450_mmcr0) { mtspr(chud_7450_mmcr0, val); break; }
894 if(spr==chud_7450_pmc1) { mtspr(chud_7450_pmc1, val); break; }
895 if(spr==chud_7450_pmc2) { mtspr(chud_7450_pmc2, val); break; }
896 if(spr==chud_7450_siar) { mtspr(chud_7450_siar, val); break; }
897 if(spr==chud_7450_mmcr1) { mtspr(chud_7450_mmcr1, val); break; }
898 if(spr==chud_7450_pmc3) { mtspr(chud_7450_pmc3, val); break; }
899 if(spr==chud_7450_pmc4) { mtspr(chud_7450_pmc4, val); break; }
900 if(spr==chud_7450_tlbmiss) { mtspr(chud_7450_tlbmiss, val); break; }
901 if(spr==chud_7450_ptehi) { mtspr(chud_7450_ptehi, val); break; }
902 if(spr==chud_7450_ptelo) { mtspr(chud_7450_ptelo, val); break; }
903 if(spr==chud_7450_l3pm) { mtspr(chud_7450_l3pm, val); break; }
904 if(spr==chud_7450_iabr) { mtspr(chud_7450_iabr, val); break; }
905 if(spr==chud_7450_ldstdb) { mtspr(chud_7450_ldstdb, val); break; }
906 if(spr==chud_7450_ictc) { mtspr(chud_7450_ictc, val); break; }
907 if(spr==chud_7450_thrm1) { mtspr(chud_7450_thrm1, val); break; }
908 if(spr==chud_7450_thrm2) { mtspr(chud_7450_thrm2, val); break; }
909 if(spr==chud_7450_thrm3) { mtspr(chud_7450_thrm3, val); break; }
910 if(spr==chud_7450_pir) { mtspr(chud_7450_pir, val); break; }
911
912 if(spr==chud_7450_l2cr) {
913 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
914 break;
915 }
916
917 if(spr==chud_7450_l3cr) {
918 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
919 break;
920 }
921 if(spr==chud_7450_ldstcr) {
922 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
923 break;
924 }
925 if(spr==chud_7450_hid0) {
926 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
927 break;
928 }
929 if(spr==chud_7450_hid1) {
930 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
931 break;
932 }
933 if(spr==chud_7450_msscr0) {
934 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
935 break;
936 }
937 if(spr==chud_7450_msssr0) {
938 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
939 break;
940 }
941 if(spr==chud_7450_ictrl) {
942 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
943 break;
944 }
945
946 // 7455/7457 only
947 if(spr==chud_7455_sprg4) { mtspr(chud_7455_sprg4, val); break; }
948 if(spr==chud_7455_sprg5) { mtspr(chud_7455_sprg5, val); break; }
949 if(spr==chud_7455_sprg6) { mtspr(chud_7455_sprg6, val); break; }
950 if(spr==chud_7455_sprg7) { mtspr(chud_7455_sprg7, val); break; }
951 if(spr==chud_7455_ibat4u) { mtspr(chud_7455_ibat4u, val); break; }
952 if(spr==chud_7455_ibat4l) { mtspr(chud_7455_ibat4l, val); break; }
953 if(spr==chud_7455_ibat5u) { mtspr(chud_7455_ibat5u, val); break; }
954 if(spr==chud_7455_ibat5l) { mtspr(chud_7455_ibat5l, val); break; }
955 if(spr==chud_7455_ibat6u) { mtspr(chud_7455_ibat6u, val); break; }
956 if(spr==chud_7455_ibat6l) { mtspr(chud_7455_ibat6l, val); break; }
957 if(spr==chud_7455_ibat7u) { mtspr(chud_7455_ibat7u, val); break; }
958 if(spr==chud_7455_ibat7l) { mtspr(chud_7455_ibat7l, val); break; }
959 if(spr==chud_7455_dbat4u) { mtspr(chud_7455_dbat4u, val); break; }
960 if(spr==chud_7455_dbat4l) { mtspr(chud_7455_dbat4l, val); break; }
961 if(spr==chud_7455_dbat5u) { mtspr(chud_7455_dbat5u, val); break; }
962 if(spr==chud_7455_dbat5l) { mtspr(chud_7455_dbat5l, val); break; }
963 if(spr==chud_7455_dbat6u) { mtspr(chud_7455_dbat6u, val); break; }
964 if(spr==chud_7455_dbat6l) { mtspr(chud_7455_dbat6l, val); break; }
965 if(spr==chud_7455_dbat7u) { mtspr(chud_7455_dbat7u, val); break; }
966 if(spr==chud_7455_dbat7l) { mtspr(chud_7455_dbat7l, val); break; }
967 }
968
969 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
970 if(spr==chud_970_pir) { mtspr(chud_970_pir, val); break; }
971 if(spr==chud_970_pmc1) { mtspr(chud_970_pmc1, val); break; }
972 if(spr==chud_970_pmc2) { mtspr(chud_970_pmc2, val); break; }
973 if(spr==chud_970_pmc3) { mtspr(chud_970_pmc3, val); break; }
974 if(spr==chud_970_pmc4) { mtspr(chud_970_pmc4, val); break; }
975 if(spr==chud_970_pmc5) { mtspr(chud_970_pmc5, val); break; }
976 if(spr==chud_970_pmc6) { mtspr(chud_970_pmc6, val); break; }
977 if(spr==chud_970_pmc7) { mtspr(chud_970_pmc7, val); break; }
978 if(spr==chud_970_pmc8) { mtspr(chud_970_pmc8, val); break; }
979 if(spr==chud_970_hdec) { mtspr(chud_970_hdec, val); break; }
980 }
981
982 /* we only get here if none of the above cases qualify */
983 retval = KERN_INVALID_ARGUMENT;
984 } while(0);
985
986 chudxnu_set_interrupts_enabled(oldlevel); /* re-enable interrupts */
987
988 if(cpu>=0) { // cpu<0 means don't bind
989 chudxnu_unbind_thread(current_thread());
990 }
991
992 return retval;
993 }
994
995 __private_extern__
996 kern_return_t chudxnu_write_spr64(int cpu, int spr, uint64_t val)
997 {
998 kern_return_t retval = KERN_SUCCESS;
999 boolean_t oldlevel;
1000 uint64_t *val_p = &val;
1001
1002 /* bind to requested CPU */
1003 if(cpu>=0) { // cpu<0 means don't bind
1004 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
1005 return KERN_INVALID_ARGUMENT;
1006 }
1007 }
1008
1009 oldlevel = ml_set_interrupts_enabled(FALSE); /* disable interrupts */
1010
1011 do {
1012 /* PPC SPRs - 32-bit and 64-bit implementations */
1013 if(spr==chud_ppc_srr0) { retval = mtspr64(chud_ppc_srr0, val_p); break; }
1014 if(spr==chud_ppc_srr1) { retval = mtspr64(chud_ppc_srr1, val_p); break; }
1015 if(spr==chud_ppc_dar) { retval = mtspr64(chud_ppc_dar, val_p); break; }
1016 if(spr==chud_ppc_dsisr) { retval = mtspr64(chud_ppc_dsisr, val_p); break; }
1017 if(spr==chud_ppc_sdr1) { retval = mtspr64(chud_ppc_sdr1, val_p); break; }
1018 if(spr==chud_ppc_sprg0) { retval = mtspr64(chud_ppc_sprg0, val_p); break; }
1019 if(spr==chud_ppc_sprg1) { retval = mtspr64(chud_ppc_sprg1, val_p); break; }
1020 if(spr==chud_ppc_sprg2) { retval = mtspr64(chud_ppc_sprg2, val_p); break; }
1021 if(spr==chud_ppc_sprg3) { retval = mtspr64(chud_ppc_sprg3, val_p); break; }
1022 if(spr==chud_ppc_dabr) { retval = mtspr64(chud_ppc_dabr, val_p); break; }
1023 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
1024 struct ppc_thread_state64 state;
1025 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
1026 kern_return_t kr;
1027 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
1028 if(KERN_SUCCESS==kr) {
1029 state.srr1 = val;
1030 kr = chudxnu_thread_set_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, count, TRUE /* user only */);
1031 if(KERN_SUCCESS!=kr) {
1032 retval = KERN_FAILURE;
1033 }
1034 } else {
1035 retval = KERN_FAILURE;
1036 }
1037 break;
1038 }
1039
1040 /* PPC SPRs - 64-bit implementations */
1041 if(spr==chud_ppc64_asr) { retval = mtspr64(chud_ppc64_asr, val_p); break; }
1042 if(spr==chud_ppc64_accr) { retval = mtspr64(chud_ppc64_accr, val_p); break; }
1043 if(spr==chud_ppc64_ctrl) { retval = mtspr64(chud_ppc64_ctrl, val_p); break; }
1044
1045 /* Implementation Specific SPRs */
1046 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
1047 if(spr==chud_970_hid0) { retval = mtspr64(chud_970_hid0, val_p); break; }
1048 if(spr==chud_970_hid1) { retval = mtspr64(chud_970_hid1, val_p); break; }
1049 if(spr==chud_970_hid4) { retval = mtspr64(chud_970_hid4, val_p); break; }
1050 if(spr==chud_970_hid5) { retval = mtspr64(chud_970_hid5, val_p); break; }
1051 if(spr==chud_970_mmcr0) { retval = mtspr64(chud_970_mmcr0, val_p); break; }
1052 if(spr==chud_970_mmcr1) { retval = mtspr64(chud_970_mmcr1, val_p); break; }
1053 if(spr==chud_970_mmcra) { retval = mtspr64(chud_970_mmcra, val_p); break; }
1054 if(spr==chud_970_siar) { retval = mtspr64(chud_970_siar, val_p); break; }
1055 if(spr==chud_970_sdar) { retval = mtspr64(chud_970_sdar, val_p); break; }
1056 if(spr==chud_970_imc) { retval = mtspr64(chud_970_imc, val_p); break; }
1057
1058 if(spr==chud_970_rmor) { retval = mtspr64(chud_970_rmor, val_p); break; }
1059 if(spr==chud_970_hrmor) { retval = mtspr64(chud_970_hrmor, val_p); break; }
1060 if(spr==chud_970_hior) { retval = mtspr64(chud_970_hior, val_p); break; }
1061 if(spr==chud_970_lpidr) { retval = mtspr64(chud_970_lpidr, val_p); break; }
1062 if(spr==chud_970_lpcr) { retval = mtspr64(chud_970_lpcr, val_p); break; }
1063 if(spr==chud_970_dabrx) { retval = mtspr64(chud_970_dabrx, val_p); break; }
1064
1065 if(spr==chud_970_hsprg0) { retval = mtspr64(chud_970_hsprg0, val_p); break; }
1066 if(spr==chud_970_hsprg1) { retval = mtspr64(chud_970_hsprg1, val_p); break; }
1067 if(spr==chud_970_hsrr0) { retval = mtspr64(chud_970_hsrr0, val_p); break; }
1068 if(spr==chud_970_hsrr1) { retval = mtspr64(chud_970_hsrr1, val_p); break; }
1069 if(spr==chud_970_hdec) { retval = mtspr64(chud_970_hdec, val_p); break; }
1070 if(spr==chud_970_trig0) { retval = mtspr64(chud_970_trig0, val_p); break; }
1071 if(spr==chud_970_trig1) { retval = mtspr64(chud_970_trig1, val_p); break; }
1072 if(spr==chud_970_trig2) { retval = mtspr64(chud_970_trig2, val_p); break; }
1073 if(spr==chud_970_scomc) { retval = mtspr64(chud_970_scomc, val_p); break; }
1074 if(spr==chud_970_scomd) { retval = mtspr64(chud_970_scomd, val_p); break; }
1075
1076 if(spr==chud_970_hid0) {
1077 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1078 break;
1079 }
1080
1081 if(spr==chud_970_hid1) {
1082 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1083 break;
1084 }
1085
1086 if(spr==chud_970_hid4) {
1087 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1088 break;
1089 }
1090
1091 if(spr==chud_970_hid5) {
1092 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1093 break;
1094 }
1095
1096 }
1097
1098 /* we only get here if none of the above cases qualify */
1099 retval = KERN_INVALID_ARGUMENT;
1100 } while(0);
1101
1102 chudxnu_set_interrupts_enabled(oldlevel); /* re-enable interrupts */
1103
1104 if(cpu>=0) { // cpu<0 means don't bind
1105 chudxnu_unbind_thread(current_thread());
1106 }
1107
1108 return retval;
1109 }
1110
1111 #pragma mark **** cache flush ****
1112
1113 __private_extern__
1114 void chudxnu_flush_caches(void)
1115 {
1116 cacheInit();
1117 }
1118
1119 __private_extern__
1120 void chudxnu_enable_caches(boolean_t enable)
1121 {
1122 if(!enable) {
1123 cacheInit();
1124 cacheDisable();
1125 } else {
1126 cacheInit();
1127 }
1128 }
1129
1130 #pragma mark **** perfmon facility ****
1131
1132 __private_extern__
1133 kern_return_t chudxnu_perfmon_acquire_facility(task_t task)
1134 {
1135 return perfmon_acquire_facility(task);
1136 }
1137
1138 __private_extern__
1139 kern_return_t chudxnu_perfmon_release_facility(task_t task)
1140 {
1141 return perfmon_release_facility(task);
1142 }
1143
1144 #pragma mark **** branch trace buffer ****
1145
1146 extern int pc_trace_buf[1024];
1147
1148 __private_extern__
1149 uint32_t * chudxnu_get_branch_trace_buffer(uint32_t *entries)
1150 {
1151 if(entries) {
1152 *entries = sizeof(pc_trace_buf)/sizeof(int);
1153 }
1154 return pc_trace_buf;
1155 }
1156
1157 #pragma mark **** interrupts enable/disable ****
1158
1159 __private_extern__
1160 boolean_t chudxnu_get_interrupts_enabled(void)
1161 {
1162 return ml_get_interrupts_enabled();
1163 }
1164
1165 __private_extern__
1166 boolean_t chudxnu_set_interrupts_enabled(boolean_t enable)
1167 {
1168 return ml_set_interrupts_enabled(enable);
1169 }
1170
1171 __private_extern__
1172 boolean_t chudxnu_at_interrupt_context(void)
1173 {
1174 return ml_at_interrupt_context();
1175 }
1176
1177 __private_extern__
1178 void chudxnu_cause_interrupt(void)
1179 {
1180 ml_cause_interrupt();
1181 }
1182
1183 #pragma mark **** rupt counters ****
1184
1185 __private_extern__
1186 kern_return_t chudxnu_get_cpu_rupt_counters(int cpu, rupt_counters_t *rupts)
1187 {
1188 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
1189 return KERN_FAILURE;
1190 }
1191
1192 if(rupts) {
1193 boolean_t oldlevel = ml_set_interrupts_enabled(FALSE);
1194 struct per_proc_info *per_proc;
1195
1196 per_proc = PerProcTable[cpu].ppe_vaddr;
1197 rupts->hwResets = per_proc->hwCtr.hwResets;
1198 rupts->hwMachineChecks = per_proc->hwCtr.hwMachineChecks;
1199 rupts->hwDSIs = per_proc->hwCtr.hwDSIs;
1200 rupts->hwISIs = per_proc->hwCtr.hwISIs;
1201 rupts->hwExternals = per_proc->hwCtr.hwExternals;
1202 rupts->hwAlignments = per_proc->hwCtr.hwAlignments;
1203 rupts->hwPrograms = per_proc->hwCtr.hwPrograms;
1204 rupts->hwFloatPointUnavailable = per_proc->hwCtr.hwFloatPointUnavailable;
1205 rupts->hwDecrementers = per_proc->hwCtr.hwDecrementers;
1206 rupts->hwIOErrors = per_proc->hwCtr.hwIOErrors;
1207 rupts->hwSystemCalls = per_proc->hwCtr.hwSystemCalls;
1208 rupts->hwTraces = per_proc->hwCtr.hwTraces;
1209 rupts->hwFloatingPointAssists = per_proc->hwCtr.hwFloatingPointAssists;
1210 rupts->hwPerformanceMonitors = per_proc->hwCtr.hwPerformanceMonitors;
1211 rupts->hwAltivecs = per_proc->hwCtr.hwAltivecs;
1212 rupts->hwInstBreakpoints = per_proc->hwCtr.hwInstBreakpoints;
1213 rupts->hwSystemManagements = per_proc->hwCtr.hwSystemManagements;
1214 rupts->hwAltivecAssists = per_proc->hwCtr.hwAltivecAssists;
1215 rupts->hwThermal = per_proc->hwCtr.hwThermal;
1216 rupts->hwSoftPatches = per_proc->hwCtr.hwSoftPatches;
1217 rupts->hwMaintenances = per_proc->hwCtr.hwMaintenances;
1218 rupts->hwInstrumentations = per_proc->hwCtr.hwInstrumentations;
1219
1220 ml_set_interrupts_enabled(oldlevel);
1221 return KERN_SUCCESS;
1222 } else {
1223 return KERN_FAILURE;
1224 }
1225 }
1226
1227 __private_extern__
1228 kern_return_t chudxnu_clear_cpu_rupt_counters(int cpu)
1229 {
1230 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
1231 return KERN_FAILURE;
1232 }
1233
1234 bzero((char *)&(PerProcTable[cpu].ppe_vaddr->hwCtr), sizeof(struct hwCtrs));
1235 return KERN_SUCCESS;
1236 }
1237
1238 #pragma mark **** alignment exceptions ****
1239
1240 __private_extern__
1241 kern_return_t chudxnu_passup_alignment_exceptions(boolean_t enable)
1242 {
1243 if(enable) {
1244 dgWork.dgFlags |= enaNotifyEM;
1245 } else {
1246 dgWork.dgFlags &= ~enaNotifyEM;
1247 }
1248 return KERN_SUCCESS;
1249 }
1250
1251 #pragma mark **** scom ****
1252 kern_return_t chudxnu_scom_read(uint32_t reg, uint64_t *data)
1253 {
1254 ml_scom_read(reg, data);
1255 return KERN_SUCCESS;
1256 }
1257
1258 kern_return_t chudxnu_scom_write(uint32_t reg, uint64_t data)
1259 {
1260 ml_scom_write(reg, data);
1261 return KERN_SUCCESS;
1262 }
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