osfmk/i386/machine_check.h

   1 /*
   2  * Copyright (c) 2007 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 #ifdef KERNEL_PRIVATE
  29 #ifndef _I386_MACHINE_CHECK_H_
  30 #define _I386_MACHINE_CHECK_H_
  31
  32 /*
  33  * This header defines the machine check architecture for Pentium4 and Xeon.
  34  */
  35
  36 /*
  37  * Macro BITS(n,m) returns the number of bits between bit(n) and bit(m),
  38  * where (n>m). Macro BIT1(n) is cosmetic and returns 1.
  39  */
  40 #define BITS(n,m)       ((n)-(m)+1)
  41 #define BIT1(n)         (1)
  42
  43 /*
  44  * IA32 SDM 14.3.1 Machine-Check Global Control MSRs:
  45  */
  46 #define IA32_MCG_CAP            (0x179)
  47 typedef union {
  48      struct {
  49         uint64_t        count                   :BITS(7,0);
  50         uint64_t        mcg_ctl_p               :BIT1(8);
  51         uint64_t        mcg_ext_p               :BIT1(9);
  52         uint64_t        reserved1               :BIT1(10);
  53         uint64_t        mcg_tes_p               :BIT1(11);
  54         uint64_t        reserved2               :BITS(15,12);
  55         uint64_t        mcg_ext_cnt             :BITS(23,16);
  56         uint64_t        reserved3               :BITS(63,24);
  57      }          bits;
  58      uint64_t   u64;
  59 } ia32_mcg_cap_t;
  60
  61 #define IA32_MCG_STATUS         (0x17A)
  62 typedef union {
  63      struct {
  64         uint64_t        ripv                    :BIT1(0);
  65         uint64_t        eipv                    :BIT1(1);
  66         uint64_t        mcip                    :BIT1(2);
  67         uint64_t        reserved                :BITS(61,3);
  68      }          bits;
  69      uint64_t   u64;
  70 } ia32_mcg_status_t;
  71
  72 #define IA32_MCG_CTL            (0x17B)
  73 typedef uint64_t        ia32_mcg_ctl_t;
  74 #define IA32_MCG_CTL_ENABLE     (0xFFFFFFFFFFFFFFFFULL)
  75 #define IA32_MCG_CTL_DISABLE    (0x0ULL)
  76
  77
  78 /*
  79  * IA32 SDM 14.3.2 Error-Reporting Register Banks:
  80  */
  81 #define IA32_MCi_CTL(i)         (0x400 + 4*(i))
  82 #define IA32_MCi_STATUS(i)      (0x401 + 4*(i))
  83 #define IA32_MCi_ADDR(i)        (0x402 + 4*(i))
  84 #define IA32_MCi_MISC(i)        (0x403 + 4*(i))
  85
  86 #define IA32_MC0_CTL            IA32_MCi_CTL(0)
  87 #define IA32_MC0_STATUS         IA32_MCi_STATUS(0)
  88 #define IA32_MC0_ADDR           IA32_MCi_ADDR(0)
  89 #define IA32_MC0_MISC           IA32_MCi_MISC(0)
  90
  91 #define IA32_MC1_CTL            IA32_MCi_CTL(1)
  92 #define IA32_MC1_STATUS         IA32_MCi_STATUS(1)
  93 #define IA32_MC1_ADDR           IA32_MCi_ADDR(1)
  94 #define IA32_MC1_MISC           IA32_MCi_MISC(1)
  95
  96 #define IA32_MC2_CTL            IA32_MCi_CTL(2)
  97 #define IA32_MC2_STATUS         IA32_MCi_STATUS(2)
  98 #define IA32_MC2_ADDR           IA32_MCi_ADDR(2)
  99 #define IA32_MC2_MISC           IA32_MCi_MISC(2)
 100
 101 #define IA32_MC3_CTL            IA32_MCi_CTL(3)
 102 #define IA32_MC3_STATUS         IA32_MCi_STATUS(3)
 103 #define IA32_MC3_ADDR           IA32_MCi_ADDR(3)
 104 #define IA32_MC3_MISC           IA32_MCi_MISC(3)
 105
 106 #define IA32_MC4_CTL            IA32_MCi_CTL(4)
 107 #define IA32_MC4_STATUS         IA32_MCi_STATUS(4)
 108 #define IA32_MC4_ADDR           IA32_MCi_ADDR(4)
 109 #define IA32_MC4_MISC           IA32_MCi_MISC(4)
 110
 111 typedef uint64_t        ia32_mci_ctl_t;
 112 #define IA32_MCi_CTL_EE(j)      (0x1ULL << (j))
 113 #define IA32_MCi_CTL_ENABLE_ALL (0xFFFFFFFFFFFFFFFFULL)
 114
 115 typedef union {
 116      struct {
 117         uint64_t        mca_error               :BITS(15,0);
 118         uint64_t        model_specific_error    :BITS(31,16);
 119         uint64_t        other_information       :BITS(56,32);
 120         uint64_t        pcc                     :BIT1(57);
 121         uint64_t        addrv                   :BIT1(58);
 122         uint64_t        miscv                   :BIT1(59);
 123         uint64_t        en                      :BIT1(60);
 124         uint64_t        uc                      :BIT1(61);
 125         uint64_t        over                    :BIT1(62);
 126         uint64_t        val                     :BIT1(63);
 127      }          bits;
 128      struct {           /* Variant if threshold-based error status present: */
 129         uint64_t        mca_error               :BITS(15,0);
 130         uint64_t        model_specific_error    :BITS(31,16);
 131         uint64_t        other_information       :BITS(52,32);
 132         uint64_t        threshold               :BITS(54,53);
 133         uint64_t        reserved                :BITS(56,55);
 134         uint64_t        pcc                     :BIT1(57);
 135         uint64_t        addrv                   :BIT1(58);
 136         uint64_t        miscv                   :BIT1(59);
 137         uint64_t        en                      :BIT1(60);
 138         uint64_t        uc                      :BIT1(61);
 139         uint64_t        over                    :BIT1(62);
 140         uint64_t        val                     :BIT1(63);
 141      }          bits_tes_p;
 142      uint64_t   u64;
 143 } ia32_mci_status_t;
 144
 145 /* Values for threshold_status if mcg_tes_p == 1 and uc == 0 */
 146 #define THRESHOLD_STATUS_NO_TRACKING    0
 147 #define THRESHOLD_STATUS_GREEN          1
 148 #define THRESHOLD_STATUS_YELLOW         2
 149 #define THRESHOLD_STATUS_RESERVED       3
 150
 151 typedef uint64_t        ia32_mci_addr_t;
 152 typedef uint64_t        ia32_mci_misc_t;
 153
 154
 155 #define IA32_MCG_EAX            (0x180)
 156 #define IA32_MCG_EBX            (0x181)
 157 #define IA32_MCG_ECX            (0x182)
 158 #define IA32_MCG_EDX            (0x183)
 159 #define IA32_MCG_ESI            (0x184)
 160 #define IA32_MCG_EDI            (0x185)
 161 #define IA32_MCG_EBP            (0x186)
 162 #define IA32_MCG_ESP            (0x187)
 163 #define IA32_MCG_EFLAGS         (0x188)
 164 #define IA32_MCG_EIP            (0x189)
 165 #define IA32_MCG_MISC           (0x18A)
 166
 167 #define IA32_MCG_RAX            (0x180)
 168 #define IA32_MCG_RBX            (0x181)
 169 #define IA32_MCG_RCX            (0x182)
 170 #define IA32_MCG_RDX            (0x183)
 171 #define IA32_MCG_RSI            (0x184)
 172 #define IA32_MCG_RDI            (0x185)
 173 #define IA32_MCG_RBP            (0x186)
 174 #define IA32_MCG_RSP            (0x187)
 175 #define IA32_MCG_RFLAGS         (0x188)
 176 #define IA32_MCG_RIP            (0x189)
 177 #define IA32_MCG_MISC           (0x18A)
 178 #define IA32_MCG_RESERVED1      (0x18B)
 179 #define IA32_MCG_RESERVED2      (0x18C)
 180 #define IA32_MCG_RESERVED3      (0x18D)
 181 #define IA32_MCG_RESERVED4      (0x18E)
 182 #define IA32_MCG_RESERVED5      (0x18F)
 183 #define IA32_MCG_R8             (0x190)
 184 #define IA32_MCG_R9             (0x191)
 185 #define IA32_MCG_R10            (0x192)
 186 #define IA32_MCG_R11            (0x193)
 187 #define IA32_MCG_R12            (0x194)
 188 #define IA32_MCG_R13            (0x195)
 189 #define IA32_MCG_R14            (0x196)
 190 #define IA32_MCG_R15            (0x197)
 191
 192 extern void     mca_cpu_alloc(cpu_data_t *cdp);
 193 extern void     mca_cpu_init(void);
 194 extern void     mca_dump(void);
 195 extern void     mca_check_save(void);
 196
 197 #endif  /* _I386_MACHINE_CHECK_H_ */
 198 #endif  /* KERNEL_PRIVATE */