osfmk/i386/AT386/rtc.h

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * The contents of this file constitute Original Code as defined in and
   7  * are subject to the Apple Public Source License Version 1.1 (the
   8  * "License").  You may not use this file except in compliance with the
   9  * License.  Please obtain a copy of the License at
  10  * http://www.apple.com/publicsource and read it before using this file.
  11  *
  12  * This Original Code and all software distributed under the License are
  13  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  14  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  15  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
  17  * License for the specific language governing rights and limitations
  18  * under the License.
  19  *
  20  * @APPLE_LICENSE_HEADER_END@
  21  */
  22 /*
  23  * @OSF_COPYRIGHT@
  24  */
  25 /*
  26  * HISTORY
  27  *
  28  * Revision 1.1.1.1  1998/09/22 21:05:39  wsanchez
  29  * Import of Mac OS X kernel (~semeria)
  30  *
  31  * Revision 1.1.1.1  1998/03/07 02:25:40  wsanchez
  32  * Import of OSF Mach kernel (~mburg)
  33  *
  34  * Revision 1.1.6.1  1994/09/23  01:47:30  ezf
  35  *      change marker to not FREE
  36  *      [1994/09/22  21:20:22  ezf]
  37  *
  38  * Revision 1.1.2.3  1993/08/09  19:39:04  dswartz
  39  *      Add ANSI prototypes - CR#9523
  40  *      [1993/08/06  17:51:17  dswartz]
  41  *
  42  * Revision 1.1.2.2  1993/06/02  23:21:32  jeffc
  43  *      Added to OSF/1 R1.3 from NMK15.0.
  44  *      [1993/06/02  21:03:17  jeffc]
  45  *
  46  * Revision 1.1  1992/09/30  02:27:20  robert
  47  *      Initial revision
  48  *
  49  * $EndLog$
  50  */
  51 /* CMU_HIST */
  52 /*
  53  * Revision 2.7  91/05/14  16:30:03  mrt
  54  *      Correcting copyright
  55  *
  56  * Revision 2.6  91/03/16  14:47:03  rpd
  57  *      Fixed ioctl definitions for ANSI C.
  58  *      [91/02/20            rpd]
  59  *
  60  * Revision 2.5  91/02/05  17:20:25  mrt
  61  *      Changed to new Mach copyright
  62  *      [91/02/01  17:47:16  mrt]
  63  *
  64  * Revision 2.4  90/11/26  14:51:02  rvb
  65  *      jsb bet me to XMK34, sigh ...
  66  *      [90/11/26            rvb]
  67  *      Synched 2.5 & 3.0 at I386q (r1.5.1.3) & XMK35 (r2.4)
  68  *      [90/11/15            rvb]
  69  *
  70  * Revision 1.5.1.2  90/07/27  11:27:06  rvb
  71  *      Fix Intel Copyright as per B. Davies authorization.
  72  *      [90/07/27            rvb]
  73  *
  74  * Revision 2.2  90/05/03  15:46:11  dbg
  75  *      First checkin.
  76  *
  77  * Revision 1.5.1.1  90/01/08  13:29:46  rvb
  78  *      Add Intel copyright.
  79  *      [90/01/08            rvb]
  80  *
  81  * Revision 1.5  89/09/25  12:27:37  rvb
  82  *      File was provided by Intel 9/18/89.
  83  *      [89/09/23            rvb]
  84  *
  85  */
  86 /* CMU_ENDHIST */
  87 /*
  88  * Mach Operating System
  89  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
  90  * All Rights Reserved.
  91  *
  92  * Permission to use, copy, modify and distribute this software and its
  93  * documentation is hereby granted, provided that both the copyright
  94  * notice and this permission notice appear in all copies of the
  95  * software, derivative works or modified versions, and any portions
  96  * thereof, and that both notices appear in supporting documentation.
  97  *
  98  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  99  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
 100  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 101  *
 102  * Carnegie Mellon requests users of this software to return to
 103  *
 104  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 105  *  School of Computer Science
 106  *  Carnegie Mellon University
 107  *  Pittsburgh PA 15213-3890
 108  *
 109  * any improvements or extensions that they make and grant Carnegie Mellon
 110  * the rights to redistribute these changes.
 111  */
 112 /*
 113  */
 114
 115 /*
 116  *   Copyright 1988, 1989 by Intel Corporation, Santa Clara, California.
 117  *
 118  *              All Rights Reserved
 119  *
 120  * Permission to use, copy, modify, and distribute this software and
 121  * its documentation for any purpose and without fee is hereby
 122  * granted, provided that the above copyright notice appears in all
 123  * copies and that both the copyright notice and this permission notice
 124  * appear in supporting documentation, and that the name of Intel
 125  * not be used in advertising or publicity pertaining to distribution
 126  * of the software without specific, written prior permission.
 127  *
 128  * INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
 129  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
 130  * IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
 131  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
 132  * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
 133  * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
 134  * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 135  */
 136
 137 #define RTC_ADDR        0x70    /* I/O port address for register select */
 138 #define RTC_DATA        0x71    /* I/O port address for data read/write */
 139
 140 /*
 141  * Register A definitions
 142  */
 143 #define RTC_A           0x0a    /* register A address */
 144 #define RTC_UIP         0x80    /* Update in progress bit */
 145 #define RTC_DIV0        0x00    /* Time base of 4.194304 MHz */
 146 #define RTC_DIV1        0x10    /* Time base of 1.048576 MHz */
 147 #define RTC_DIV2        0x20    /* Time base of 32.768 KHz */
 148 #define RTC_RATE6       0x06    /* interrupt rate of 976.562 */
 149
 150 /*
 151  * Register B definitions
 152  */
 153 #define RTC_B           0x0b    /* register B address */
 154 #define RTC_SET         0x80    /* stop updates for time set */
 155 #define RTC_PIE         0x40    /* Periodic interrupt enable */
 156 #define RTC_AIE         0x20    /* Alarm interrupt enable */
 157 #define RTC_UIE         0x10    /* Update ended interrupt enable */
 158 #define RTC_SQWE        0x08    /* Square wave enable */
 159 #define RTC_DM          0x04    /* Date mode, 1 = binary, 0 = BCD */
 160 #define RTC_HM          0x02    /* hour mode, 1 = 24 hour, 0 = 12 hour */
 161 #define RTC_DSE         0x01    /* Daylight savings enable */
 162
 163 /*
 164  * Register C definitions
 165  */
 166 #define RTC_C           0x0c    /* register C address */
 167 #define RTC_IRQF        0x80    /* IRQ flag */
 168 #define RTC_PF          0x40    /* PF flag bit */
 169 #define RTC_AF          0x20    /* AF flag bit */
 170 #define RTC_UF          0x10    /* UF flag bit */
 171
 172 /*
 173  * Register D definitions
 174  */
 175 #define RTC_D           0x0d    /* register D address */
 176 #define RTC_VRT         0x80    /* Valid RAM and time bit */
 177
 178 #define RTC_NREG        0x0e    /* number of RTC registers */
 179 #define RTC_NREGP       0x0a    /* number of RTC registers to set time */
 180
 181 #define RTCRTIME        _IOR('c', 0x01, struct rtc_st) /* Read time from RTC */
 182 #define RTCSTIME        _IOW('c', 0x02, struct rtc_st) /* Set time into RTC */
 183
 184 struct rtc_st {
 185         char    rtc_sec;
 186         char    rtc_asec;
 187         char    rtc_min;
 188         char    rtc_amin;
 189         char    rtc_hr;
 190         char    rtc_ahr;
 191         char    rtc_dow;
 192         char    rtc_dom;
 193         char    rtc_mon;
 194         char    rtc_yr;
 195         char    rtc_statusa;
 196         char    rtc_statusb;
 197         char    rtc_statusc;
 198         char    rtc_statusd;
 199 };
 200
 201 /*
 202  * this macro reads contents of real time clock to specified buffer
 203  */
 204 #define load_rtc(regs) \
 205 {\
 206         register int i; \
 207         \
 208         for (i = 0; i < RTC_NREG; i++) { \
 209                 outb(RTC_ADDR, i); \
 210                 (regs)[i] = inb(RTC_DATA); \
 211         } \
 212 }
 213
 214 /*
 215  * this macro writes contents of specified buffer to real time clock
 216  */
 217 #define save_rtc(regs) \
 218 { \
 219         register int i; \
 220         for (i = 0; i < RTC_NREGP; i++) { \
 221                 outb(RTC_ADDR, i); \
 222                 outb(RTC_DATA, (regs)[i]);\
 223         } \
 224 }
 225
 226