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[apple/xnu.git] / iokit / Drivers / scsi / drvSymbios8xx / Sym8xxRegs.h
1 /*
2 * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22
23 /*
24 * Copyright (c) 1998 Apple Computer Inc.
25 *
26 * Symbios8xx Controller.
27 *
28 */
29
30 /* SymBios 8xx register addressing definitions */
31
32 #define SCNTL0_SIZE 0x01
33 #define SCNTL0 0x00000000
34 #define SCNTL0_INIT 0xCA /* Scsi control 0 */
35 /* ARB1 1 */
36 /* ARB0 1 : Full arbitration */
37 /* START 0 : Start sequence */
38 /* WATN 0 : Select with ATN */
39 /* EPC 1 : enable SCSI bus parity checking */
40 /* RES */
41 /* AAP 1 : Assert ATN on SCSI parity error */
42 /* TRG 0 : Target mode. 720 is Initiator */
43
44 #define SCNTL1_SIZE 0x01
45 #define SCNTL1 0x00000001
46 #define SCNTL1_INIT 0x00 /* Scsi control 1 */
47 /* EXC 0 : Extra clock cycle data setup (Sdtr) */
48 /* ADB 0 : Assert SCSI data bus */
49 /* DHP 0 : Target only Disable halt parity error */
50 /* CON 0 : 820 connected to SCSI bus */
51 /* RST 0 : Assert SCSI RST signal */
52 /* AESP 0 : Force bad parity */
53 /* IARB 0 : Immediate arbitration */
54 /* SST 0 : Start SCSI transfer */
55
56 #define SCNTL1_SCSI_RST 0x08 /* force scsi reset in scntl1 reg */
57
58 #define SCNTL2_SIZE 0x01
59 #define SCNTL2 0x00000002
60 #define SCNTL2_INIT 0x00 /* Scsi control 2 */
61 #define SDU 0x80 /* SDU 0 : SCSI Disconnect Unexpected */
62 #define CHM 0x40 /* CHM 0 : Chained mode */
63 #define SLPMD 0x40 /* SLPMD 0 : SLPAR Mode Bit */
64 #define SLPHBEN 0x40 /* SLPHBEN : SLPAR High Byte Enable */
65 #define WSS 0x08 /* WSS 0 : Wide Scsi Send */
66 #define VUE0 0x40 /* VUE0 : Vendor Uniq Enhancements Bit 0 */
67 #define VUE1 0x40 /* VUE1 : Vendor Uniq Enhancements Bit 1 */
68 #define WSR 0x01 /* WSR 0 : Wide Scsi Receive */
69
70 #define SCNTL3_SIZE 0x01
71 #define SCNTL3 0x00000003
72 #define SCNTL3_INIT 0x03 /* Scsi control 3 for 40Mhz sys clock */
73 #define SCNTL3_INIT_875 0x05 /* Scsi control 3 for 80Mhz sys clock */
74 #define SCNTL3_INIT_875_ULTRA 0x95 /* Scsi control 3 for 80Mhz sys clock */
75 #define SCNTL3_INIT_875_FAST 0x35 /* Scsi control 3 for 80Mhz sys clock */
76 #define SCNTL3_INIT_875_SLOW 0x55 /* Scsi control 3 for 80Mhz sys clock */
77 /* RES */
78 #define SCF 0x70 /* SCF 0 : Sync clock conversion factor 0-2 */
79 #define EWS 0x08 /* EWS 0 : Enable Wide SCSI (wdtr) */
80 #define CCF 0x07 /* CCF 0 : Async clock conversion factor 0-2 */
81
82 #define SCID_SIZE 0x01
83 #define SCID 0x00000004
84 #define SCID_INIT 0x40 /* Scsi chip Id */
85 /* RES */
86 /* RRE 1 : Enable response to reselection */
87 /* SRE 0 : Disable response to selection */
88 /* RES */
89 /* ID3 0 */
90 /* ID2 0 */
91 /* ID1 0 */
92 /* ID0 0 : Encoded 53825 chip SCSI Id */
93
94 #define SXFER_SIZE 0x01
95 #define SXFER 0x00000005
96 #define SXFER_INIT 0x00 /* Scsi Transfer */
97 /* TP2 0 */
98 /* TP1 0 */
99 /* TP0 0 : Scsi sync Transfer Period (4)(Sdtr) */
100 /* RES */
101 /* MO3 0 */
102 /* MO2 0 */
103 /* MO1 0 */
104 /* MO0 0 : Max Scsi Sync ReqAck offset (async) (Sdtr) */
105
106 #define SDID_SIZE 0x01
107 #define SDID 0x00000006
108 #define SDID_INIT 0x00 /* Scsi destination Id */
109 /* RES */
110 /* RES */
111 /* RES */
112 /* RES */
113 /* ID3 0 */
114 /* ID2 0 */
115 /* ID1 0 */
116 /* ID0 0 : Encoded destination Scsi Id */
117
118 #define GPREG_SIZE 0x01
119 #define GPREG 0x00000007
120 #define GPREG_INIT 0x00 /* Read/write general purpose */
121 #define GPIO3 0x08 /* GPIO bit 3 */
122 /* RES */
123 /* RES */
124 /* RES */
125 /* GPO 0 : General purpose output */
126 /* GPI3 0 */
127 /* GPI2 0 */
128 /* GPI1 0 */
129 /* GPI0 0 : General purpose inputs */
130
131 #define SFBR_SIZE 0x01
132 #define SFBR 0x00000008
133 #define SFBR_INIT 0x00
134 /* SCSI First Byte Received */
135
136 #define SOCL_SIZE 0x01
137 #define SOCL 0x00000009
138 #define SOCL_INIT 0x00
139 #define SREQ 0x80 /* REQ 0 : Assert SCSI REQ signal */
140 #define SACK 0x40 /* ACK 0 : ACK */
141 #define SBSY 0x20 /* BSY 0 : BSY */
142 #define SSEL 0x10 /* SEL 0 : SEL */
143 #define SATN 0x08 /* ATN 0 : ATN */
144 #define SMSG 0x04 /* MSG 0 : MSG */
145 #define SC_D 0x02 /* C/D 0 : C/D */
146 #define SI_O 0x01 /* I/O 0 : I/O */
147
148 #define SSID_SIZE 0x01
149 #define SSID 0x0000000A /* Read Only */
150 /* VAL Scsi Valid Bit */
151 /* RES */
152 /* RES */
153 /* RES */
154 /* ID3 */
155 /* ID2 */
156 /* ID1 */
157 /* ID0 Encoded Destination Scsi Id */
158
159 #define SBCL_SIZE 0x01
160 #define SBCL 0x0000000B /* Scsi Bus Control Lines Read only */
161 /* REQ */
162 /* ACK */
163 /* BSY */
164 /* SEL */
165 /* ATN */
166 /* MSG */
167 /* C/D */
168 /* I/O */
169
170 #define DSTAT_SIZE 0x01
171 #define DSTAT 0x0000000C /* DMA status Read only */
172 #define DFE 0x80 /* DSTAT DMA FIFO Empty */
173 #define MDPE 0x40 /* Master Data Parity Error */
174 #define BF 0x20 /* Bus Fault */
175 #define DABRT 0x10 /* Abort occurred */
176 #define SSI 0x08 /* Script Step Interrupt */
177 #define SIR 0x04 /* Script Interrupt Inst Received */
178 #ifdef notdef
179 #define WTD 0x02 /* was watchdog timer, now reserved */
180 #endif /* notdef */
181 #define IID 0x01 /* Illegal Instruction Detected */
182
183 #define SSTAT0_SIZE 0x01
184 #define SSTAT0 0x0000000D /* SCSI status zero Read only */
185 #define ILF 0x80 /* ILF SIDL least significant byte full */
186 #define ORF 0x40 /* ORF SODR least significant byte full */
187 #define OLF 0x20 /* OLF SODL least significant byte full */
188 #define AIP 0x10 /* AIP Arbitration in progress */
189 #define LOA 0x08 /* LOA Lost arbitration */
190 #define WOA 0x04 /* WOA Won arbitration */
191 #define RSTB 0x02 /* RST Scsi reset signal */
192 #define SDP0 0x01 /* SDP0 Scsi SDP0 parity signal */
193
194 #define SSTAT1_SIZE 0x01
195 #define SSTAT1 0x0000000E /* SCSI status one Read only */
196 /* FF3-0 Bytes or word in the Scsi FIFO */
197 /* SDP Latched Scsi parity */
198 /* MSG Scsi phase status */
199 /* C/D */
200 /* I/O */
201
202 #define SSTAT2_SIZE 0x01
203 #define SSTAT2 0x0000000F /* Scsi status two Read only */
204 #define ILF1 0x80 /* ILF1 SIDL most significant byte full */
205 #define ORF1 0x40 /* ORF1 SODR " " " " */
206 #define OLF1 0x20 /* OLF1 SODL " " " " */
207 /* RES */
208 #define SPL1 0x08 /* SPL1 Latched Scsi parity for SIDL15-8 */
209 #define FF4 0x04 /* FIFO Flags Bit 4 */
210 #define LDSC 0x02 /* LDSC Last disconnect */
211 #define SDP1 0x01 /* SDP1 Scsi SDP1 Signal */
212
213 #define DSA_SIZE 0x04
214 #define DSA 0x00000010
215 #define DSA_INIT 0x00000000 /* Data structure address */
216
217 #define ISTAT_SIZE 0x01
218 #define ISTAT 0x00000014
219 #define ISTAT_INIT 0x00 /* Interrupt Status */
220 #define ABRT 0x80 /* Abort Operation */
221 #define RST 0x40 /* Software reset */
222 #define SIGP 0x20 /* Signal process */
223 #define SEM 0x10 /* Semaphore */
224 #define ISTAT_CON 0X08 /* Connected to target. */
225 #define INTF 0x04 /* Interrupt on the fly */
226 #define SIP 0x02 /* SCSI Interrupt Pending */
227 #define DIP 0x01 /* DMA Interrupt Pending */
228
229 #define CTEST0_SIZE 0x01
230 #define CTEST0 0x00000018
231 #define CTEST0_INIT 0x00 /* Chip test zero (now general purpose, rph) */
232
233 #define CTEST1_SIZE 0x01
234 #define CTEST1 0x00000019 /* Chip test one Read only */
235 /* FMT3-0 0 : Byte empty in DMA FIFO */
236 /* FFL3-0 0 : Byte full in DMA FIFO */
237
238 #define CTEST2_SIZE 0x01
239 #define CTEST2 0x0000001A /* Chip test two Read only */
240 /* DDIR Data transfer direction (1 : Scsi bus -> host) */
241 /* SIGP Signal process (Clear SIGP ISTAT when read) */
242 /* CIO (read-only, indicates chip configured as I/O space) */
243 /* CM (read-only, indicates configured as memory space) */
244 /* RES */
245 /* TEOP Scsi true end of process */
246 /* DREQ Data request status */
247 /* DACK Data acknowledge status */
248
249 #define CTEST3_SIZE 0x01
250 #define CTEST3 0x0000001B
251 #define CTEST3_INIT 0x04 /* Chip test three */
252 #define CTEST3_INIT_A 0x05 /* Chip test three for 'A' part */
253
254 #define VERS 0xf0 /* V3-0 0 : Chip revision level */
255 #define FLF 0x08 /* FLF 0 : Flush DMA Fifo */
256 #define CLF 0x04 /* CLF 1 : Clear DMA FIFO */
257 #define FM 0x02 /* FM 0 : Fetch pin mode */
258 #define WRIE 0x01 /* WRIE 1 : Write and Invalidate Enable, for 825A only!!! */
259
260 #define TEMP_SIZE 0x04
261 #define TEMP 0x0000001C
262 #define TEMP_INIT 0x00000000 /* Tempory stack */
263
264 #define DFIFO_SIZE 0x01
265 #define DFIFO 0x00000020
266 #define DFIFO_INIT 0x00 /* DMA FIFO */
267 /* upper bit used for 825 'A' part when using large fifo */
268 /* BO6-0 0: Byte offset counter */
269
270 #define CTEST4_SIZE 0x01
271 #define CTEST4 0x00000021 /* Chip test four */
272 // #define CTEST4_INIT 0x80 /* Chip test four DISABLE BURST!! */
273 #define CTEST4_INIT 0x00 /* Chip test four */
274 /* BDIS 0 : set for Burst Disable, reset allows burst on data moves */
275 /* ZMOD High impedance mode */
276 /* ZSD Scsi high impedance mode */
277 /* SRTM Shadow register test mode */
278 /* NOT for bandit!!!! yes for NEW rev of Dumbarton LATER on, not initial!!! */
279 /* MPEE 0 : Master Parity Error Enable Do we want this set???? rph */
280 /* FBL2-0 Fifo byte control */
281
282 #define CTEST5_SIZE 0x01
283 #define CTEST5 0x00000022
284 #define CTEST5_INIT 0x00 /* Chip test five */
285 #define CTEST5_INIT_A 0x00 /* Chip test five 'A' part, upper burst OFF */
286 #define CTEST5_INIT_A_revB 0x24 /* Chip test five 'A' part, upper burst OFF
287 * also Enable 536 byte fifo */
288 #define ADCK 0x80 /* ADCK 0 : Clock address incrementor */
289 #define BBCK 0x40 /* BBCK 0 : Clock byte counter */
290 #define DFS 0x20 /* DFS 0 : fifo size - 0=88 1=536 bytes */
291 #define MASR 0x10 /* MASR 0 : Master control for set reset pulses */
292 #define DDIR 0x08 /* DDIR 0 : DMA direction */
293 #define BL2 0x04 /* BL2 0 : see DMODE bits 6,7 */
294 #define BO89 0x03 /* BO89 0 : upper bits of DFIFO count */
295
296 #define CTEST6_SIZE 0x01
297 #define CTEST6 0x00000023
298 #define CTEST6_INIT 0x00 /* chip test six */
299 /* 7-0 0 : DMA Fifo */
300
301 #define DBC_SIZE 0x04
302 #define DBC 0x00000024
303 #define DBC_INIT 0x000000 /* DMA Byte Counter */
304
305 #define DCMD_SIZE 0x01
306 #define DCMD 0x00000027
307 #define DCMD_INIT 0x00 /* DMA command */
308
309 #define DNAD_SIZE 0x04
310 #define DNAD 0x00000028
311 #define DNAD_INIT 0x00000000 /* DMA Next Data Address */
312
313 #define DSP_SIZE 0x04
314 #define DSP 0x0000002C
315 #define DSP_INIT 0x00000000 /* DMA script pointer */
316
317 #define DSPS_SIZE 0x04
318 #define DSPS 0x00000030
319 #define DSPS_INIT 0x00000000 /* DMA SCRIPTS Pointer Save */
320
321 #define SCRATCHA_SIZE 0x04
322 #define SCRATCHA 0x00000034
323 #define SCRATCHA0 0x00000034
324 #define SCRATCHA1 0x00000035
325 #define SCRATCHA2 0x00000036
326 #define SCRATCHA3 0x00000037
327 #define SCRATCHA_INIT 0x04030201 /* general purpose register */
328
329 #define DMODE_SIZE 0x01
330 #define DMODE 0x00000038
331 /* 825 bug!!!!! 8 is max!!!!!!! rph 8-23-94
332 */
333 #define DMODE_INIT 0x82 /* DMA mode 8 burst xfers + instruc fetch */
334 #define DMODE_INIT_A 0x0A /* DMA mode 32 burst xfers + instruc fetch */
335 /* BL1 1 : Burst length, burst size is '8' transfers (4 bytes per) */
336 /* BL0 0 : Burst length */
337 /* SIOM 0 : Source I/O-Memory Enable (Memory space is default) */
338 /* DIOM 0 : Destination I/O-Memory Enable (Memory space is default) */
339 /* ER 1 : Enable Read Line Command, set for 825'A' part */
340 /* ERM 0 : */
341 /* BOF 1 : Burst Op Code Fetch Enable, only for 825!!! rph */
342 /* MAN 0 : Manual start mode (leave 0 for auto-start with DSP write */
343
344 #define DIEN_SIZE 0x01
345 #define DIEN 0x00000039
346 #define DIEN_INIT 0x7D /* No mask on DMA interrupt */
347 /* RES */
348 /* MDPE 1 : Master Data Parity Error */
349 /* BF 1 : Bus fault */
350 /* ABRT 1 : Aborted */
351 /* SSI 1 : Script step interrupt */
352 /* SIR 1 : Script interrupt instruction received */
353 /* RES */
354 /* IID 1 : Illegal instruction detected */
355
356 #define DWT_SIZE 0x01
357 #define DWT 0x0000003A
358 #define DWT_INIT 0xD0 /* DMA watchdog timer to 0xD0*32*BCLK ns*/
359
360 #define DCNTL_SIZE 0x01
361 #define DCNTL 0x0000003B
362 #define DCNTL_INIT 0x01 /* DMA Control register */
363 #define DCNTL_INIT_A 0xA1 /* DMA Control register, 'A' part */
364 /* CLE 7: Cache Line Size Enable for 'A' part */
365 /* PFF 6: pre-fetch flush bit for 'A' part */
366 /* PFEN 5: pre-fetch Enable bit for 'A' part */
367 /* RES */
368 /* RES */
369 #define SSM 0x10 /* 0 : Single step mode */
370 /* IRQM 0 : HW driver type for IRQ pin, default is open drain, ask HW rph*/
371 #define STD 0x04 /* 0 : start DMA operation */
372 /* IRQ 1: IRQ disable for 'A' part */
373 /* COM 1 : No Compatibility 700 */
374
375 #define ADDER_SIZE 0x04
376 #define ADDER 0x0000003C /* Adder sum output Read only */
377
378 #define SIEN_SIZE 0x02
379 #define SIEN 0x00000040
380 #define SIEN_INIT_RST_OFF 0x048D /* SCSI Interrupt enable SIEN0-1 rph */
381 #define SIEN_INIT 0x048F /* SCSI Interrupt enable SIEN0-1 rph */
382 /* SIEN0 */
383 /* M/A 1 : Scsi phase mismatch */
384 /* CMP 0 : Function complete */
385 /* SEL 0 : Selected */
386 /* RSL 0 : Reselected */
387 /* SGE 1 : Scsi Gross error */
388 /* UDC 1 : Unexpected disconnect */
389 /* RST 1 : Scsi Reset condition */
390 /* PAR 1 : Scsi Parity error */
391
392 /* RES */
393 /* RES */
394 /* RES */
395 /* RES */
396 /* RES */
397 /* STO 1 : (Re)Selection timeout */
398 /* GEM 0 : General purpose timeout*/
399 /* HTH 0 : Handshake timeout */
400
401 #define SIST_SIZE 0x02
402 #define SIST 0x00000042 /* Scsi interrupt status Read only */
403 /* idem SIEN reg */
404 #define STO 0x0400
405 #define GEN 0x0200
406 #define HTH 0x0100
407
408 #define MA 0x0080
409 #define CMP 0x0040
410 #define SEL 0x0020
411 #define RSL 0x0010
412 #define SGE 0x0008
413 #define UDC 0x0004
414 #define RSTI 0x0002
415 #define PAR 0x0001
416
417 #define SLPAR_SIZE 0x01
418 #define SLPAR 0x00000044
419 #define SLPAR_INIT 0x00 /* SCSI longitudinal parity */
420
421 #define SWIDE_SIZE 0x01
422 #define SWIDE 0x00000045 /* Scsi wide residue data Read only */
423
424 #define MACNTL_SIZE 0x01
425 #define MACNTL 0x00000046
426 #define MACNTL_INIT 0x00 /* memory access control */
427 /* TYP3-0 : Chip Type (read-only) */
428 /* DataWr 0 : Data write Far memory */
429 /* DataRd 0 : Data read far memory */
430 /* Pointer to script fetch 0 : far memory */
431 /* Script fetch 0 : far memory */
432
433 #define GPCNTL_SIZE 0x01
434 #define GPCNTL 0x00000047
435 #define GPCNTL_INIT 0x0F /* General purpose control Cf appendum ?? */
436 // #define GPCNTL_INIT 0xCF /* General purpose control Cf appendum ?? */
437 /* ME : 0 Master Enable */
438 /* FE : 0 Fetch Enable */
439 /* RES */
440 /* GPI/O_en4 : 0 GPREG input or output */
441 /* GPI/O_en3 : 1 */
442 /* GPI/O_en2 : 1 */
443 /* GPI/O_en1 : 1 */
444 /* GPI/O_en0 : 1 */
445
446 #define STIME0_SIZE 0x01
447 #define STIME0 0x00000048
448 #define STIME0_INIT 0x0C /* Scsi timer register 0 */
449 /* HTH3 */
450 /* HTH2 */
451 /* HTH1 0 */
452 /* HTH0 0 : Handshake timer period (disabled) */
453 /* SEL3 1 */
454 /* SEL2 1 */
455 /* SEL1 0 */
456 /* SEL0 0 : Selection timeout period (204.8ms) */
457
458 #define STIME1_SIZE 0x01
459 #define STIME1 0x00000049
460 #define STIME1_INIT 0x00 /* Scsi timer register one */
461 /* RES */
462 /* RES */
463 /* RES */
464 /* RES */
465 /* GEN3 0 */
466 /* GEN2 0 */
467 /* GEN1 0 */
468 /* GEN0 0 : General purpose timer period (disabled) */
469
470 #define RESPID0_SIZE 0x01
471 #define RESPID0 0x0000004A
472 #define RESPID0_INIT 0x00 /* Response Id zero */
473 /* ID7 - ID0 */
474
475 #define RESPID1_SIZE 0x01
476 #define RESPID1 0x0000004B
477 #define RESPID1_INIT 0x00 /* Response ID one */
478 /* ID15 - ID8 */
479
480 #define STEST0_SIZE 0x01
481 #define STEST0 0x0000004C /* Scsi test register zero Read only */
482 /* RES */
483 /* RES */
484 /* RES */
485 /* RES */
486 /* SLT Selection response Logic test */
487 /* ART Arbitration priority encoder test */
488 /* SOZ Scsi synchronous offset zero */
489 /* SOM Scsi synchronous offset maximum */
490
491 #define STEST1_SIZE 0x01
492 #define STEST1 0x0000004D /* Scsi test register one Read/Write */
493 #define STEST1_INIT 0x00
494 #define SCLK 0x80 /* SCLK 0 : 1 = Use PCI Clock 0 = Use SCLK input */
495 #define SISIO 0x40 /* SISIO 0 : SCSI Isolation Mode */
496 /* 0 : */
497 /* 0 : */
498 #define DBLEN 0x08 /* DBLEN 0 : SCLK Doubler Enable */
499 #define DBLSEL 0x04 /* DBLSEL 0 : SCLK Doubler Select */
500 /* 0 : */
501 /* 0 : */
502
503 #define STEST2_SIZE 0x01
504 #define STEST2 0x0000004E
505 #define STEST2_INIT 0x00 /* Scsi Test register two */
506 #define STEST2_DIFF_INIT 0x20 /* Scsi Test register two */
507 #define SCE 0x80 /* SCE 0 : Scsi control enable */
508 #define ROF 0x40 /* ROF 0 : Reset Scsi offset */
509 #define DIF 0x20 /* DIF 0/1 : SCSI differential mode, set if we detect differential card */
510 #define SLB 0x10 /* SLB 0 : Scsi loopback mode */
511 #define SZM 0x08 /* SZM 0 : SCSI high impedance mode */
512 #define AWS 0x04 /* AWS 0 : Always wide SCSI */
513 #define EXT 0x02 /* EXT 0 : Extend REQ/ACK filtering NEVER want SET for 'fast'!!! */
514 #define LOW 0x01 /* LOW 0 : Scsi low level mode */
515
516 #define STEST3_SIZE 0x01
517 #define STEST3 0x0000004F
518 #define STEST3_INIT 0x92 /* Scsi test register 3 */
519 #define EAN 0x80 /* EAN 1 : Enable active negation */
520 #define STR 0x40 /* STR 0 : Scsi FIFO test read */
521 #define HSC 0x20 /* HSC 0 : Halt Scsi Clock */
522 #define DSI 0x10 /* DSI 1 : Disable single initiator response */
523 /* RES */
524 #define TTM 0x04 /* TTM 0 : Timer test mode */
525 #define CSF 0x02 /* CSF 1 : Clear SCSI FIFO */
526 #define STW 0x01 /* STW 0 : SCSI FIFO test write */
527
528 #define SSIDL_SIZE 0x02
529 #define SSIDL 0x00000050 /* SCSI input data latch Read only */
530
531 #define SODL_SIZE 0x02
532 #define SODL 0x00000054
533 #define SODL_INIT 0x0000 /* SCSI Output Data Latch */
534
535 #define SBDL_SIZE 0x02
536 #define SBDL 0x00000058 /* SCSI bus data line Read only */
537
538 #define SCRATCHB_SIZE 0x04
539 #define SCRATCHB 0x0000005C
540 #define SCRATCHB0 0x0000005C
541 #define SCRATCHB1 0x0000005D
542 #define SCRATCHB2 0x0000005E
543 #define SCRATCHB3 0x0000005F
544 #define SCRATCHB_INIT 0x00000000 /* general purpose register */
545
546 /* ************************* */
547
548 /* Miscellaneous defines */
549 #define CLK_40MHz 40
550 #define CLK_80MHz 80
551 #define kResetRecoveryTimeMS 5000
552
553 #define kChipIdSym875 0x000f
554 #define kChipIdSym895 0x000c
555 #define kChipIdSym896 0x000b
556 #define kChipIdSym1010 0x0020
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