iokit/Drivers/network/drvMaceEnet/MaceEnetRegisters.h

   1 /*
   2  * Copyright (c) 1998-2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * The contents of this file constitute Original Code as defined in and
   7  * are subject to the Apple Public Source License Version 1.1 (the
   8  * "License").  You may not use this file except in compliance with the
   9  * License.  Please obtain a copy of the License at
  10  * http://www.apple.com/publicsource and read it before using this file.
  11  *
  12  * This Original Code and all software distributed under the License are
  13  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  14  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  15  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
  17  * License for the specific language governing rights and limitations
  18  * under the License.
  19  *
  20  * @APPLE_LICENSE_HEADER_END@
  21  */
  22 /*
  23  * Copyright (c) 1995-1996 NeXT Software, Inc.
  24  *
  25  * Interface definition for the Mace Ethernet controller.
  26  *
  27  * HISTORY
  28  *
  29  * 04-Nov-97
  30  *      Created.
  31  */
  32
  33 #ifndef _MACEENETREGISTERS_H
  34 #define _MACEENETREGISTERS_H
  35
  36 // ---------------------------------------------------------------------------------------------
  37 //      Mace and GC I/O Addresses
  38 // ---------------------------------------------------------------------------------------------
  39 #define kTxDMABaseOffset                0x08200                 // offset from I/O Space Base address
  40 #define kRxDMABaseOffset                0x08300
  41 #define kControllerBaseOffset           0x11000
  42 #define kControllerROMOffset            0x19000
  43
  44
  45 // ---------------------------------------------------------------------------------------------
  46 //      Mace Register Numbers & Bit Assignments
  47 // ---------------------------------------------------------------------------------------------
  48 /*
  49  * Chip Revisions..
  50  */
  51
  52 #define kMaceRevisionB0         0x0940
  53 #define kMaceRevisionA2         0x0941
  54
  55 /* xmtfc */
  56 #define kXmtFC                  0x0020                  /* Transmit Frame Control               */
  57 #define kXmtFCDRtry             0X80                    /* - Disable Retry                      */
  58 #define kXmtFCDXmtFCS           0x08                    /* - Disable Transmit FCS               */
  59 #define kXmtFCAPadXmt           0x01                    /* - Auto PAD Transmit                  */
  60
  61 /* xmtfs */
  62 #define kXmtFS                  0x0030                  /* Transmit Frame Status                */
  63 #define kXmtFSXmtSV             0x80                    /* - Transmit Status Valid              */
  64 #define kXmtFSUFlo              0x40                    /* - Transmit Underflow                 */
  65 #define kXmtFSLCol              0x20                    /* - Transmit late collision            */
  66 #define kXmtFSMore              0x10                    /* - Transmit < 1 retry                 */
  67 #define kXmtFSOne               0x08                    /* - Transmit single retry              */
  68 #define kXmtFSDefer             0x04                    /* - Transmit deferred                  */
  69 #define kXmtFSLCar              0x02                    /* - Transmit lost carrier              */
  70 #define kXmtFSRtry              0x01                    /* - Transmit Unsuccessful              */
  71
  72 /* xmtrc */
  73 #define kXmtRC                  0x0040                  /* Transmit Retry Count                 */
  74 #define kXmtRCExDef             0x80                    /* - ?                                  */
  75 #define kXmtRCXmrRC             0x0F                    /* - Transmit retry count               */
  76
  77 /* rcvfc */
  78 #define kRcvFC                  0x0050                  /* Receive Frame Control                */
  79 #define kRcvFCLLRcv             0x08                    /* - ?                                  */
  80 #define kRcvFCMR                0x04                    /* - Match/Reject (not implemented)     */
  81 #define kRcvFCAStrpRcv          0x01                    /* - Auto Strip Receive Enable          */
  82
  83 /* rcvfs */
  84 #define kRcvFS0                 0x0060                  /* Receive Frame Status - Byte 0        */
  85 #define kRcvFS0RcvCnt           0xFF                    /* - Receive Msg Byte Count (7:0)       */
  86
  87 #define kRcvFS1                 0x0060                  /* Receive Frame Status - Byte 1        */
  88 #define kRcvFS1OFlo             0x80                    /* - Receive Overflow                   */
  89 #define kRcvFS1Clsn             0x40                    /* - Receive Collision                  */
  90 #define kRcvFS1Fram             0x20                    /* - Receive Framming Error             */
  91 #define kRcvFS1FCS              0x10                    /* - Receive Frame Check Error          */
  92 #define kRcvFS1RcvCnt           0x0f                    /* - Receive Msg Byte Count (11:8)      */
  93
  94
  95 #define kRcvFS2                 0x0060                  /* Receive Frame Status - Byte 2        */
  96 #define kRcvFS2RntPC            0xFF                    /* - Runt Packet Count                  */
  97
  98 #define kRcvFS3                 0x0060                  /* Receive Frame Status - Byte 3        */
  99 #define kRcvFS3RcvCC            0xFF                    /* Receive Collision Count              */
 100
 101 /* fifofc */
 102 #define kFifoFC                 0x0070                  /* FIFO Frame Count                     */
 103 #define kFifoFCXFW              0xc0                    /* - ?                                  */
 104 #define kFifoFCXFW8             0x00                    /* - ?                                  */
 105 #define kFifoFCXFW16            0x40                    /* - ?                                  */
 106 #define kFifoFCXFW32            0x80                    /* - ?                                  */
 107
 108 #define kFifoFCRFW              0x30                    /* - ?                                  */
 109 #define kFifoFCRFW16            0x00                    /* - ?                                  */
 110 #define kFifoFCRFW32            0x10                    /* - ?                                  */
 111 #define kFifoFCRFW64            0x20                    /* - ?                                  */
 112 #define kFifoFCXFWU             0x08                    /* - ?                                  */
 113 #define kFifoFCRFWU             0x04                    /* - ?                                  */
 114 #define kFifoFCXBRst            0x02                    /* - ?                                  */
 115 #define kFifoFCRBRst            0x01                    /* - ?                                  */
 116
 117
 118 /* ir */
 119 #define kIntReg                 0x0080                  /* Interrupt Register                   */
 120 #define kIntRegJab              0x80                    /* - Jabber Error                       */
 121 #define kIntRegBabl             0x40                    /* - Babble Error                       */
 122 #define kIntRegCErr             0x20                    /* - Collision Error                    */
 123 #define kIntRegRcvCCO           0x10                    /* - Receive Collision Count Overflow   */
 124 #define kIntRegRntPCO           0x08                    /* - Runt Packet Count Overflow         */
 125 #define kIntRegMPCO             0x04                    /* - Missed Packet Count Overflow       */
 126 #define kIntRegRcvInt           0x02                    /* - Receive Interrupt                  */
 127 #define kIntRegXmtInt           0x01                    /* - Transmit Interrupt                 */
 128
 129 /* imr */
 130 #define kIntMask                0x0090                  /* Interrupt Mask Register              */
 131 #define kIntMaskJab             0x80                    /* - Mask Jabber Error Int              */
 132 #define kIntMaskBabl            0x40                    /* - Mask Babble Error Int              */
 133 #define kIntMaskCErr            0x20                    /* - Mask Collision Error Int           */
 134 #define kIntMaskRcvCCO          0x10                    /* - Mask Rcv Coll Ctr Overflow Int     */
 135 #define kIntMaskRntPCO          0x08                    /* - Mask Runt Packet Ctr Overflow Int  */
 136 #define kIntMaskMPCO            0x04                    /* - Mask Missed Pkt Ctr Overflow Int   */
 137 #define kIntMaskRcvInt          0x02                    /* - Mask Receive Int                   */
 138 #define kIntMaskXmtInt          0x01                    /* - Mask Transmit Int                  */
 139
 140 /* pr */
 141 #define kPollReg                0x00A0                  /* Poll Register                        */
 142 #define kPollRegXmtSV           0x80                    /* - Transmit Status Valid              */
 143 #define kPollRegTDTReq          0x40                    /* - Transmit Data Transfer Request     */
 144 #define kPollRegRDTReq          0x20                    /* - Receive Data Transfer Request      */
 145
 146 /* biucc */
 147 #define kBIUCC                  0x00B0                  /* BUI Configuration Control            */
 148 #define kBIUCCBSwp              0x40                    /* - Byte Swap Enable                   */
 149 #define kBIUCCXmtSP             0x30                    /* - Transmit Start Point:              */
 150 #define kBIUCCXmtSP04           0x00                    /* - 00b = 4 Bytes                      */
 151 #define kBIUCCXmtSP16           0x10                    /* - 01b = 16 Bytes                     */
 152 #define kBIUCCXmtSP64           0x20                    /* - 10b = 64 Bytes                     */
 153 #define kBIUCCXmtSP112          0x30                    /* - 11b = 112 Bytes                    */
 154 #define kBIUCCSWRst             0x01                    /* Software Reset                       */
 155
 156 /* fifocc */
 157 #define kFifoCC                 0x00C0                  /* FIFO Configuration Control           */
 158 #define kFifoCCXmtFW            0xC0                    /* - Transmit FIFO Watermark:           */
 159 #define kFifoCCXmtFW08          0x00                    /* - 00b = 8 Write Cycles               */
 160 #define kFifoCCXmtFW16          0x40                    /* - 01b = 16 Write Cycles              */
 161 #define kFifoCCXmtFW32          0x80                    /* - 10b = 32 Write Cycles              */
 162
 163 #define kFifoCCRcvFW            0x30                    /* - Receive FIFO Watermark:            */
 164 #define kFifoCCRcvFW16          0x00                    /* - 00b = 16 Bytes                     */
 165 #define kFifoCCRcvFW32          0x10                    /* - 01b = 32 Bytes                     */
 166 #define kFifoCCRcvFW64          0x20                    /* - 10b = 64 Bytes                     */
 167
 168 #define kFifoCCXmtFWRst         0x08                    /* - Transmit FIFO Watermark Reset      */
 169 #define kFifoCCRcvFWRst         0x04                    /* - Receive FIFO Watermark Reset       */
 170 #define kFifoCCXmtBRst          0x02                    /* - Transmit Burst Enable              */
 171 #define kFifoCCRcvBRst          0x01                    /* - Receive Burst Enable               */
 172
 173 /* maccc */
 174 #define kMacCC                  0x00D0                  /* MAC Configuration Control            */
 175 #define kMacCCProm              0x80                    /* - Promiscuous Mode Enable            */
 176 #define kMacCCDXmt2PD           0x40                    /* - Disable Transmit Two Part Deferral */
 177 #define kMacCCEMBA              0x20                    /* - Enable Modified Backoff Algorithm  */
 178 #define kMacCCDRcvPA            0x08                    /* - ?                                  */
 179 #define kMacCCDRcvBC            0x04                    /* - ?                                  */
 180 #define kMacCCEnXmt             0x02                    /* - Transmit Enable                    */
 181 #define kMacCCEnRcv             0x01                    /* - Receive Enable                     */
 182
 183 /* plscc */
 184 #define kPLSCC                  0x00E0                  /* PLS Configuration Control            */
 185 #define kPLSCCXmtSel            0x08                    /* - Transmit Mode Select               */
 186 #define kPLSCCPortSel           0x06                    /* - Port Select:                       */
 187 #define kPLSCCPortSelAUI        0x00                    /* - 00b = AUI                          */
 188 #define kPLSCCPortSelTenBase    0x02                    /* - 01b = 10BaseT                      */
 189 #define kPLSCCPortSelDAI        0x04                    /* - 10b = DAI                          */
 190 #define kPLSCCPortSelGPSI       0x06                    /* - 11b = GPSI                         */
 191 #define kPLSCCEnSts             0x01                    /* - Enable Status                      */
 192
 193 /* phycc */
 194 #define kPHYCC                  0x00F0                  /* PHY Configuration Control            */
 195 #define kPHYCCLnkFL             0x80                    /* - ?                                  */
 196 #define kPHYCCDLnkTst           0x40                    /* - ?                                  */
 197 #define kPHYCCRcvPol            0x20                    /* - ?                                  */
 198 #define kPHYCCDAPC              0x10                    /* - ?                                  */
 199 #define kPHYCCLRT               0x08                    /* - ?                                  */
 200 #define kPHYCCASel              0x04                    /* - ?                                  */
 201 #define kPHYCCRWake             0x02                    /* - ?                                  */
 202 #define kPHYCCAWake             0x01                    /* - ?                                  */
 203
 204 #define kMaceChipId0            0x0100                  /* MACE Chip ID Register (7:0)          */
 205 #define kMaceChipId1            0x0110                  /* MACE Chip ID Register (15:8)         */
 206
 207 /* iac */
 208 #define kIAC                    0x0120                  /* Internal Address Configuration       */
 209 #define kIACAddrChg             0x80                    /* - ?                                  */
 210 #define kIACPhyAddr             0x04                    /* - Physical Address Reset             */
 211 #define kIACLogAddr             0x02                    /* - Logical Address Reset              */
 212
 213
 214 /* ladrf */
 215 #define kLADRF                  0x0140                  /* Logical Address Filter - 8 Bytes     */
 216
 217 /* padr */
 218 #define kPADR                   0x0150                  /* Physical Address Filter - 6 Bytes    */
 219
 220 /* kMPC */
 221 #define kMPC                    0x0180                  /* Missed Packet Count                  */
 222
 223 /* utr */
 224 #define kUTR                    0x01D0                  /* User Test Register                   */
 225 #define kUTRRTRE                0x80                    /* - Reserved Test Register Enable      */
 226 #define kUTRRTRD                0x40                    /* - Reserved Test Register Disable     */
 227 #define kUTRRPA                 0x20                    /* - Runt Packet Accept                 */
 228 #define kUTRFColl               0x10                    /* - Force Collision                    */
 229 #define kUTRRcvFCS              0x08                    /* - Receive FCS Enable                 */
 230
 231 #define kUTRLoop                0x06                    /* - Loopback Control:                  */
 232 #define kUTRLoopNone            0x00                    /* - 00b = None                         */
 233 #define kUTRLoopExt             0x02                    /* - 01b = External                     */
 234 #define kUTRLoopInt             0x04                    /* - 10b = Internal (excludes MENDEC)   */
 235 #define kUTRLoopIntM            0x06                    /* - 11b = Internal (includes MENDEC)   */
 236
 237
 238 #define TX_RING_LENGTH          (32+1)
 239 #define RX_RING_LENGTH          (32+1)
 240
 241 #define NETWORK_BUFSIZE         (ETHERMAXPACKET + ETHERCRC + 8)
 242 #define TRANSMIT_QUEUE_SIZE             128
 243
 244 #define WATCHDOG_TIMER_MS       500
 245 #define TX_KDB_TIMEOUT          1000
 246
 247 #define TRANSMIT_QUIESCE_uS     200
 248 #define RECEIVE_QUIESCE_uS      1500
 249
 250 enum
 251 {
 252     kIRQEnetDev   = 0,
 253     kIRQEnetTxDMA = 1,
 254     kIRQEnetRxDMA = 2
 255 };
 256
 257 enum
 258 {
 259         MEMORY_MAP_ENET_INDEX   = 0,
 260         MEMORY_MAP_TXDMA_INDEX  = 1,
 261         MEMORY_MAP_RXDMA_INDEX  = 2,
 262         MEMORY_MAP_COUNT                = 3
 263 };
 264
 265 #endif /* !_MACEENETREGISTERS_H */