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1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22 /*
23 * @OSF_FREE_COPYRIGHT@
24 */
25 /*
26 * @APPLE_FREE_COPYRIGHT@
27 */
28
29 /*
30 Firmware.s
31
32 Handle things that should be treated as an extension of the hardware
33
34 Lovingly crafted by Bill Angell using traditional methods and only natural or recycled materials.
35 No animal products are used other than rendered otter bile and deep fried pork lard.
36
37 */
38
39 #include <cpus.h>
40 #include <ppc/asm.h>
41 #include <ppc/proc_reg.h>
42 #include <ppc/POWERMAC/mp/MPPlugIn.h>
43 #include <ppc/exception.h>
44 #include <mach/machine/vm_param.h>
45 #include <assym.s>
46
47
48 /*
49 * Here we generate the table of supported firmware calls
50 */
51
52
53
54 .data
55 .align 5 /* Line up on cache line */
56
57 .globl EXT(FWtable)
58
59 EXT(FWtable):
60
61 .globl CutTrace /* Let everyone know 'bout it */
62 .set CutTrace,(.-EXT(FWtable))/4|0x80000000 /* Call number for CutTrace */
63 .long callUnimp /* This was already handled in lowmem_vectors */
64
65 #include <ppc/FirmwareCalls.h>
66
67 .set EXT(FirmwareCnt), (.-EXT(FWtable))/4 /* Get the top number */
68
69 .text
70
71 #define SIMPLESCC 1
72 #define NOTQUITEASSIMPLE 1
73 /*
74 * This routine handles the firmware call routine. It must be entered with IR and DR off,
75 * interruptions disabled, and in supervisor state.
76 *
77 * When we enter, we expect R0 to have call number, and LR
78 * to point to the return. Also, all registers saved in savearea in R13.
79 * R3 is as passed in by the user. All others must be gotten from the save area
80 */
81
82 ENTRY(FirmwareCall, TAG_NO_FRAME_USED)
83
84 rlwinm r1,r0,2,1,29 /* Clear out bit 0 and multiply by 4 */
85 lis r12,HIGH_ADDR(EXT(FWtable)) /* Get the high part of the firmware call table */
86 cmplwi r1,EXT(FirmwareCnt)*4 /* Is it a valid firmware call number */
87 mflr r11 /* Save the return */
88 ori r12,r12,LOW_ADDR(EXT(FWtable)) /* Now the low part */
89 ble+ goodCall /* Yeah, it is... */
90
91 li r3,T_SYSTEM_CALL /* Tell the vector handler that we know nothing */
92 blr /* Return for errors... */
93
94 goodCall: mfsprg r10,0 /* Make sure about the per_proc block */
95 lwzx r1,r1,r12 /* Pick up the address of the routine */
96 lwz r4,saver4(r13) /* Pass in caller's R4 */
97 lwz r5,saver5(r13) /* Pass in caller's R5 */
98 rlwinm. r1,r1,0,0,29 /* Make sure the flag bits are clear */
99 stw r11,PP_TEMPWORK1(r10) /* Save our return point */
100
101 mtlr r1 /* Put it in the LR */
102 beq- callUnimp /* This one was unimplimented... */
103
104 blrl /* Call the routine... */
105
106 mfsprg r10,0 /* Make sure about the per_proc again */
107 stw r3,saver3(r13) /* Pass back the return code to caller */
108 lwz r11,PP_TEMPWORK1(r10) /* Get our return point */
109 li r3,T_IN_VAIN /* Tell the vector handler that we took care of it */
110 mtlr r11 /* Set the return */
111 blr /* Bye, dudes... */
112
113 callUnimp: lwz r11,PP_TEMPWORK1(r10) /* Restore the return address */
114 li r3,T_SYSTEM_CALL /* Tell the vector handler that we know nothing */
115 mtlr r11 /* Restore the LR */
116 blr /* Return for errors... */
117
118 /*
119 * This routine is used to store using a real address. It stores parmeter1 at parameter2.
120 */
121
122 ENTRY(StoreReal, TAG_NO_FRAME_USED)
123
124 lis r0,HIGH_ADDR(StoreRealCall) /* Get the top part of the SC number */
125 ori r0,r0,LOW_ADDR(StoreRealCall) /* and the bottom part */
126 sc /* Do it to it */
127 blr /* Bye bye, Birdie... */
128
129 ENTRY(StoreRealLL, TAG_NO_FRAME_USED)
130
131 stw r3,0(r4) /* Store the word */
132 blr /* Leave... */
133
134 /*
135 * This routine is used to clear a range of physical pages.
136 */
137
138 ENTRY(ClearReal, TAG_NO_FRAME_USED)
139
140 lis r0,HIGH_ADDR(ClearRealCall) /* Get the top part of the SC number */
141 ori r0,r0,LOW_ADDR(ClearRealCall) /* and the bottom part */
142 sc /* Do it to it */
143 blr /* Bye bye, Birdie... */
144
145 ENTRY(ClearRealLL, TAG_NO_FRAME_USED)
146
147 /*
148 * We take the first parameter as a physical address. The second is the length in bytes.
149 * Being crazy, I'll round the address down, and the length up. We could end up clearing
150 * an extra page at the start and one at the end, but we don't really care. If someone
151 * is stupid enough to give me unaligned addresses and lengths, I am just arrogant enough
152 * to take them at their word and to hell with them.
153 */
154
155 neg r5,r3 /* Negate the address */
156 addi r4,r4,4095 /* Round length up */
157 rlwinm r5,r5,0,20,31 /* Save extra length */
158 rlwinm r3,r3,0,0,19 /* Round the page on down */
159 add r4,r4,r5 /* Add up all extra lengths */
160 li r6,32 /* Get a displacement */
161 rlwinm r4,r4,0,0,19 /* Round the length back down */
162
163 clrloop: subi r4,r4,32 /* Back off a cache line */
164 dcbz 0,r3 /* Do the even line */
165 sub. r4,r4,r6 /* Back off a second time (we only do this to generate a CR */
166 dcbz r6,r3 /* Clear the even line */
167 addi r3,r3,64 /* Move up to every other line */
168 bgt+ clrloop /* Go until we've done it all... */
169
170 blr /* Leave... */
171 /*
172 * This routine will read in 32 byte of real storage.
173 */
174
175 ENTRY(ReadReal, TAG_NO_FRAME_USED)
176
177 mfmsr r0 /* Get the MSR */
178 rlwinm r5,r0,0,28,26 /* Clear DR bit */
179 rlwinm r5,r5,0,17,15 /* Clear EE bit */
180 mtmsr r5 /* Disable EE and DR */
181 isync /* Just make sure about it */
182
183 lwz r5,0(r3) /* Get word 0 */
184 lwz r6,4(r3) /* Get word 1 */
185 lwz r7,8(r3) /* Get word 2 */
186 lwz r8,12(r3) /* Get word 3 */
187 lwz r9,16(r3) /* Get word 4 */
188 lwz r10,20(r3) /* Get word 5 */
189 lwz r11,24(r3) /* Get word 6 */
190 lwz r12,28(r3) /* Get word 7 */
191
192 mtmsr r0 /* Restore original machine state */
193 isync /* Insure goodness */
194
195 stw r5,0(r4) /* Set word 0 */
196 stw r6,4(r4) /* Set word 1 */
197 stw r7,8(r4) /* Set word 2 */
198 stw r8,12(r4) /* Set word 3 */
199 stw r9,16(r4) /* Set word 4 */
200 stw r10,20(r4) /* Set word 5 */
201 stw r11,24(r4) /* Set word 6 */
202 stw r12,28(r4) /* Set word 7 */
203
204 blr
205
206
207 /*
208 * This routine is used to load all 4 DBATs.
209 */
210
211 ENTRY(LoadDBATs, TAG_NO_FRAME_USED)
212
213 lis r0,HIGH_ADDR(LoadDBATsCall) /* Top half of LoadDBATsCall firmware call number */
214 ori r0,r0,LOW_ADDR(LoadDBATsCall) /* Bottom half */
215 sc /* Do it to it */
216
217 blr /* Bye bye, Birdie... */
218
219 ENTRY(xLoadDBATsLL, TAG_NO_FRAME_USED)
220
221 lwz r4,0(r3) /* Get DBAT 0 high */
222 lwz r5,4(r3) /* Get DBAT 0 low */
223 lwz r6,8(r3) /* Get DBAT 1 high */
224 lwz r7,12(r3) /* Get DBAT 1 low */
225 lwz r8,16(r3) /* Get DBAT 2 high */
226 lwz r9,20(r3) /* Get DBAT 2 low */
227 lwz r10,24(r3) /* Get DBAT 3 high */
228 lwz r11,28(r3) /* Get DBAT 3 low */
229
230 sync /* Common decency and the state law require you to wash your hands */
231 mtdbatu 0,r4 /* Load DBAT 0 high */
232 mtdbatl 0,r5 /* Load DBAT 0 low */
233 mtdbatu 1,r6 /* Load DBAT 1 high */
234 mtdbatl 1,r7 /* Load DBAT 1 low */
235 mtdbatu 2,r8 /* Load DBAT 2 high */
236 mtdbatl 2,r9 /* Load DBAT 2 low */
237 mtdbatu 3,r10 /* Load DBAT 3 high */
238 mtdbatl 3,r11 /* Load DBAT 3 low */
239 sync /* Make sure it's done */
240 isync /* Toss out anything new */
241
242 blr /* Leave... */
243
244 /*
245 * This routine is used to load all 4 IBATs.
246 */
247
248 ENTRY(LoadIBATs, TAG_NO_FRAME_USED)
249
250 lis r0,HIGH_ADDR(LoadIBATsCall) /* Top half of CreateFakeIO firmware call number */
251 ori r0,r0,LOW_ADDR(LoadIBATsCall) /* Bottom half */
252 sc /* Do it to it */
253 blr /* Bye bye, Birdie... */
254
255 ENTRY(xLoadIBATsLL, TAG_NO_FRAME_USED)
256
257 lwz r4,0(r3) /* Get IBAT 0 high */
258 lwz r5,4(r3) /* Get IBAT 0 low */
259 lwz r6,8(r3) /* Get IBAT 1 high */
260 lwz r7,12(r3) /* Get IBAT 1 low */
261 lwz r8,16(r3) /* Get IBAT 2 high */
262 lwz r9,20(r3) /* Get IBAT 2 low */
263 lwz r10,24(r3) /* Get IBAT 3 high */
264 lwz r11,28(r3) /* Get IBAT 3 low */
265
266 sync /* Common decency and the state law require you to wash your hands */
267 mtibatu 0,r4 /* Load IBAT 0 high */
268 mtibatl 0,r5 /* Load IBAT 0 low */
269 mtibatu 1,r6 /* Load IBAT 1 high */
270 mtibatl 1,r7 /* Load IBAT 1 low */
271 mtibatu 2,r8 /* Load IBAT 2 high */
272 mtibatl 2,r9 /* Load IBAT 2 low */
273 mtibatu 3,r10 /* Load IBAT 3 high */
274 mtibatl 3,r11 /* Load IBAT 3 low */
275 sync /* Make sure it's done */
276 isync /* Toss out anything new */
277
278 blr /* Leave... */
279
280
281 /*
282 * This is the glue to call the CutTrace firmware call
283 */
284
285 ENTRY(dbgTrace, TAG_NO_FRAME_USED)
286
287 lis r0,HIGH_ADDR(CutTrace) /* Top half of CreateFakeIO firmware call number */
288 ori r0,r0,LOW_ADDR(CutTrace) /* Bottom half */
289 sc /* Do it to it */
290 blr /* Bye bye, Birdie... */
291
292 /*
293 * This is the glue to create a fake I/O interruption
294 */
295
296 ENTRY(CreateFakeIO, TAG_NO_FRAME_USED)
297
298 lis r0,HIGH_ADDR(CreateFakeIOCall) /* Top half of CreateFakeIO firmware call number */
299 ori r0,r0,LOW_ADDR(CreateFakeIOCall) /* Bottom half */
300 sc /* Do it to it */
301 blr /* Bye bye, Birdie... */
302
303 /*
304 * This is the glue to create a fake Dec interruption
305 */
306
307 ENTRY(CreateFakeDEC, TAG_NO_FRAME_USED)
308
309 lis r0,HIGH_ADDR(CreateFakeDECCall) /* Top half of CreateFakeDEC firmware call number */
310 ori r0,r0,LOW_ADDR(CreateFakeDECCall) /* Bottom half */
311 sc /* Do it to it */
312 blr /* Bye bye, Birdie... */
313
314
315 /*
316 * This is the glue to create a shutdown context
317 */
318
319 ENTRY(CreateShutdownCTX, TAG_NO_FRAME_USED)
320
321 lis r0,HIGH_ADDR(CreateShutdownCTXCall) /* Top half of CreateFakeIO firmware call number */
322 ori r0,r0,LOW_ADDR(CreateShutdownCTXCall) /* Bottom half */
323 sc /* Do it to it */
324 blr /* Bye bye, Birdie... */
325
326 /*
327 * This is the glue to choke system
328 */
329
330 ENTRY(ChokeSys, TAG_NO_FRAME_USED)
331
332 lis r0,HIGH_ADDR(Choke) /* Top half of Choke firmware call number */
333 ori r0,r0,LOW_ADDR(Choke) /* Bottom half */
334 sc /* Do it to it */
335 blr /* Bye bye, Birdie... */
336
337 /*
338 * Used to initialize the SCC for debugging output
339 */
340
341
342 ENTRY(fwSCCinit, TAG_NO_FRAME_USED)
343
344 mfmsr r8 /* Save the MSR */
345 mr. r3,r3 /* See if printer or modem */
346 rlwinm r12,r8,0,28,25 /* Turn off translation */
347 lis r10,0xF301 /* Set the top part */
348 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
349 #if 0
350 mtmsr r12 /* Smash the MSR */
351 isync /* Make it clean */
352 #endif
353
354 ori r10,r10,0x2000 /* Assume the printer (this is the normal one) */
355 beq+ fwSCCprnt /* It sure are... */
356 ori r10,r10,0x0002 /* Move it over to the modem port */
357
358 fwSCCprnt: dcbf 0,r10 /* Insure it is out */
359 sync
360 eieio
361 dcbi 0,r10 /* Toss it */
362 sync
363
364
365 li r7,0x09 /* Set the register */
366 stb r7,0(r10) /* Set the register */
367 dcbf 0,r10 /* Force it out */
368 sync /* Make sure it's out there */
369 dcbi 0,r10
370 eieio
371
372 li r7,0x80 /* Reset channel A */
373 stb r7,0(r10) /* Set the register */
374 dcbf 0,r10 /* Force it out */
375 sync /* Make sure it's out there */
376 dcbi 0,r10
377 eieio
378
379 li r7,0x04 /* Set the register */
380 stb r7,0(r10) /* Set the register */
381 dcbf 0,r10 /* Force it out */
382 sync /* Make sure it's out there */
383 dcbi 0,r10
384 eieio
385
386 li r7,0x44 /* x16 clock, 1 stop bit */
387 stb r7,0(r10) /* Set the register */
388 dcbf 0,r10 /* Force it out */
389 sync /* Make sure it's out there */
390 dcbi 0,r10
391 eieio
392
393 li r7,0x03 /* Set the register */
394 stb r7,0(r10) /* Set the register */
395 dcbf 0,r10 /* Force it out */
396 sync /* Make sure it's out there */
397 dcbi 0,r10
398 eieio
399
400 li r7,0xC0 /* 8 bits per char */
401 stb r7,0(r10) /* Set the register */
402 dcbf 0,r10 /* Force it out */
403 sync /* Make sure it's out there */
404 dcbi 0,r10
405 eieio
406
407 li r7,0x05 /* Set the register */
408 stb r7,0(r10) /* Set the register */
409 dcbf 0,r10 /* Force it out */
410 sync /* Make sure it's out there */
411 dcbi 0,r10
412 eieio
413
414 li r7,0xE2 /* DTR mode, 8bit/char */
415 stb r7,0(r10) /* Set the register */
416 dcbf 0,r10 /* Force it out */
417 sync /* Make sure it's out there */
418 dcbi 0,r10
419 eieio
420
421 li r7,0x02 /* Set the register */
422 stb r7,0(r10) /* Set the register */
423 dcbf 0,r10 /* Force it out */
424 sync /* Make sure it's out there */
425 dcbi 0,r10
426 eieio
427
428 li r7,0x00 /* Vector 0 */
429 stb r7,0(r10) /* Set the register */
430 dcbf 0,r10 /* Force it out */
431 sync /* Make sure it's out there */
432 dcbi 0,r10
433 eieio
434
435 li r7,0x0A /* Set the register */
436 stb r7,0(r10) /* Set the register */
437 dcbf 0,r10 /* Force it out */
438 sync /* Make sure it's out there */
439 dcbi 0,r10
440 eieio
441
442 li r7,0x00 /* Clear misc controls */
443 stb r7,0(r10) /* Set the register */
444 dcbf 0,r10 /* Force it out */
445 sync /* Make sure it's out there */
446 dcbi 0,r10
447 eieio
448
449 li r7,0x0B /* Set the register */
450 stb r7,0(r10) /* Set the register */
451 dcbf 0,r10 /* Force it out */
452 sync /* Make sure it's out there */
453 dcbi 0,r10
454 eieio
455
456 li r7,0x50 /* B/R gen T/R */
457 stb r7,0(r10) /* Set the register */
458 dcbf 0,r10 /* Force it out */
459 sync /* Make sure it's out there */
460 dcbi 0,r10
461 eieio
462
463 li r7,0x0C /* Set the register */
464 stb r7,0(r10) /* Set the register */
465 dcbf 0,r10 /* Force it out */
466 sync /* Make sure it's out there */
467 dcbi 0,r10
468 eieio
469
470 li r7,0x0A /* 9600 baud low */
471 stb r7,0(r10) /* Set the register */
472 dcbf 0,r10 /* Force it out */
473 sync /* Make sure it's out there */
474 dcbi 0,r10
475 eieio
476
477 li r7,0x0D /* Set the register */
478 stb r7,0(r10) /* Set the register */
479 dcbf 0,r10 /* Force it out */
480 sync /* Make sure it's out there */
481 dcbi 0,r10
482 eieio
483
484 li r7,0x00 /* 9600 baud high */
485 stb r7,0(r10) /* Set the register */
486 dcbf 0,r10 /* Force it out */
487 sync /* Make sure it's out there */
488 dcbi 0,r10
489 eieio
490
491 li r7,0x03 /* Set the register */
492 stb r7,0(r10) /* Set the register */
493 dcbf 0,r10 /* Force it out */
494 sync /* Make sure it's out there */
495 dcbi 0,r10
496 eieio
497
498 li r7,0xC1 /* 8 bits/char, Rx enable */
499 stb r7,0(r10) /* Set the register */
500 dcbf 0,r10 /* Force it out */
501 sync /* Make sure it's out there */
502 dcbi 0,r10
503 eieio
504
505 li r7,0x05 /* Set the register */
506 stb r7,0(r10) /* Set the register */
507 dcbf 0,r10 /* Force it out */
508 sync /* Make sure it's out there */
509 dcbi 0,r10
510 eieio
511
512 li r7,0xEA /* 8 bits/char, Tx enable */
513 stb r7,0(r10) /* Set the register */
514 dcbf 0,r10 /* Force it out */
515 sync /* Make sure it's out there */
516 dcbi 0,r10
517 eieio
518
519 li r7,0x0E /* Set the register */
520 stb r7,0(r10) /* Set the register */
521 dcbf 0,r10 /* Force it out */
522 sync /* Make sure it's out there */
523 dcbi 0,r10
524 eieio
525
526 li r7,0x01 /* BR rate gen enable */
527 stb r7,0(r10) /* Set the register */
528 dcbf 0,r10 /* Force it out */
529 sync /* Make sure it's out there */
530 dcbi 0,r10
531 eieio
532
533 li r7,0x0F /* Set the register */
534 stb r7,0(r10) /* Set the register */
535 dcbf 0,r10 /* Force it out */
536 sync /* Make sure it's out there */
537 dcbi 0,r10
538 eieio
539
540 li r7,0x00 /* ints off */
541 stb r7,0(r10) /* Set the register */
542 dcbf 0,r10 /* Force it out */
543 sync /* Make sure it's out there */
544 dcbi 0,r10
545 eieio
546
547 li r7,0x10 /* Reset ext/stat ints */
548 stb r7,0(r10) /* Set the register */
549 dcbf 0,r10 /* Force it out */
550 sync /* Make sure it's out there */
551 dcbi 0,r10
552 eieio
553
554 li r7,0x10 /* Reset ext/stat ints */
555 stb r7,0(r10) /* Set the register */
556 dcbf 0,r10 /* Force it out */
557 sync /* Make sure it's out there */
558 dcbi 0,r10
559 eieio
560
561 li r7,0x01 /* Set the register */
562 stb r7,0(r10) /* Set the register */
563 dcbf 0,r10 /* Force it out */
564 sync /* Make sure it's out there */
565 dcbi 0,r10
566 eieio
567
568 li r7,0x10 /* int on Rx, no Tx int enable */
569 stb r7,0(r10) /* Set the register */
570 dcbf 0,r10 /* Force it out */
571 sync /* Make sure it's out there */
572 dcbi 0,r10
573 eieio
574
575 li r7,0x09 /* Set the register */
576 stb r7,0(r10) /* Set the register */
577 dcbf 0,r10 /* Force it out */
578 sync /* Make sure it's out there */
579 dcbi 0,r10
580 eieio
581
582 li r7,0x0A /* int on Rx, Tx int enable */
583 stb r7,0(r10) /* Set the register */
584 dcbf 0,r10 /* Force it out */
585 sync /* Master enable, no vector */
586 dcbi 0,r10
587 eieio
588
589 li r7,0x09 /* Set the register */
590 stb r7,0(r10) /* Set the register */
591 dcbf 0,r10 /* Force it out */
592 sync /* Make sure it's out there */
593 dcbi 0,r10
594 eieio
595
596 li r7,0x02 /* No vector */
597 stb r7,0(r10) /* Set the register */
598 dcbf 0,r10 /* Force it out */
599 sync /* Master enable, no vector */
600 dcbi 0,r10
601 eieio
602
603 lbz r7,0(r10) /* Clear interrupts */
604 sync /* Master enable, no vector */
605 dcbi 0,r10
606 eieio
607
608 wSCCrdy: eieio /* Barricade it */
609 lbz r7,0(r10) /* Get current status */
610 dcbi 0,r10
611 sync
612 andi. r7,r7,0x04 /* Is transmitter empty? */
613 beq wSCCrdy /* Nope... */
614
615 eieio
616
617 #if 0
618 mtmsr r8 /* Restore 'rupts and TR */
619 isync
620 #endif
621 blr /* Leave... */
622
623 /*
624 * This routine is used to write debug output to either the modem or printer port.
625 * parm 1 is printer (0) or modem (1); parm 2 is ID (printed directly); parm 3 converted to hex
626 */
627
628 ENTRY(dbgDisp, TAG_NO_FRAME_USED)
629
630 mr r12,r0 /* Keep R0 pristene */
631 lis r0,HIGH_ADDR(dbgDispCall) /* Top half of dbgDispCall firmware call number */
632 ori r0,r0,LOW_ADDR(dbgDispCall) /* Bottom half */
633
634 sc /* Go display the stuff */
635
636 mr r0,r12 /* Restore R0 */
637 blr /* Return... */
638
639 /* Here's the low-level part of dbgDisp */
640
641 ENTRY(dbgDispLL, TAG_NO_FRAME_USED)
642
643 dbgDispInt: mfmsr r8 /* Save the MSR */
644
645 #if 0
646 lis r10,0xF301 /* (TEST/DEBUG) */
647 ori r10,r10,0x2002 /* (TEST/DEBUG) */
648 dcbf 0,r10 /* (TEST/DEBUG) */
649 sync /* (TEST/DEBUG) */
650 dcbi 0,r10 /* (TEST/DEBUG) */
651 eieio /* (TEST/DEBUG) */
652 li r7,0x35 /* (TEST/DEBUG) */
653 stb r7,4(r10) /* (TEST/DEBUG) */
654
655 lis r7,10 /* (TEST/DEBUG) */
656 spw6: addi r7,r7,-1 /* (TEST/DEBUG) */
657 mr. r7,r7 /* (TEST/DEBUG) */
658 bne- spw6 /* (TEST/DEBUG) */
659 dcbf 0,r10 /* (TEST/DEBUG) */
660 sync /* (TEST/DEBUG) */
661 dcbi 0,r10 /* (TEST/DEBUG) */
662 eieio /* (TEST/DEBUG) */
663 #endif
664
665 rlwinm r12,r8,0,28,25 /* Turn off translation */
666 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
667
668 mflr r11 /* Save the link register */
669
670 #if 0
671 mr r7,r12 /* (TEST/DEBUG) */
672 bl dumpr7 /* (TEST/DEBUG) */
673 #endif
674
675 mr. r3,r3 /* See if printer or modem */
676 lis r10,0xF301 /* Set the top part */
677 mr r3,r4 /* Copy the ID parameter */
678
679 #if 0
680 mr r9,r12 /* (TEST/DEBUG) */
681
682 mtmsr r12 /* (TEST/DEBUG) */
683 isync /* (TEST/DEBUG) */
684
685 #if 0
686 mtmsr r8 /* (TEST/DEBUG) */
687 isync /* (TEST/DEBUG) */
688 #endif
689
690 lis r12,0xF301 /* (TEST/DEBUG) */
691 ori r12,r12,0x2002 /* (TEST/DEBUG) */
692 #if 1
693 dcbf 0,r12 /* (TEST/DEBUG) */
694 sync /* (TEST/DEBUG) */
695 dcbi 0,r12 /* (TEST/DEBUG) */
696 #endif
697
698 xqrw1: eieio /* (TEST/DEBUG) */
699 lbz r7,0(r12) /* (TEST/DEBUG) */
700 dcbi 0,r12 /* (TEST/DEBUG) */
701 sync /* (TEST/DEBUG) */
702 andi. r7,r7,0x04 /* (TEST/DEBUG) */
703 beq xqrw1 /* (TEST/DEBUG) */
704
705 eieio /* (TEST/DEBUG) */
706 li r7,0x36 /* (TEST/DEBUG) */
707 stb r7,4(r12) /* (TEST/DEBUG) */
708 eieio
709 dcbf 0,r12 /* (TEST/DEBUG) */
710 sync /* (TEST/DEBUG) */
711 dcbi 0,r12 /* (TEST/DEBUG) */
712 eieio /* (TEST/DEBUG) */
713
714
715 lis r7,10 /* (TEST/DEBUG) */
716 spw7: addi r7,r7,-1 /* (TEST/DEBUG) */
717 mr. r7,r7 /* (TEST/DEBUG) */
718 bne- spw7 /* (TEST/DEBUG) */
719 dcbf 0,r12 /* (TEST/DEBUG) */
720 sync /* (TEST/DEBUG) */
721 dcbi 0,r12 /* (TEST/DEBUG) */
722 eieio /* (TEST/DEBUG) */
723 mr r12,r9 /* (TEST/DEBUG) */
724 #endif
725
726 mtmsr r12 /* Smash the MSR */
727 isync /* Make it clean */
728
729
730 #if SIMPLESCC && !NOTQUITEASSIMPLE
731 ori r10,r10,0x3010 /* Assume the printer (this is the normal one) */
732 #else
733 ori r10,r10,0x2000 /* Assume the printer (this is the normal one) */
734 #endif
735 beq+ dbgDprintr /* It sure are... */
736 #if SIMPLESCC && !NOTQUITEASSIMPLE
737 ori r10,r10,0x0020 /* Move it over to the modem port */
738 #else
739 ori r10,r10,0x0002 /* Move it over to the modem port */
740
741 #if !NOTQUITEASSIMPLE
742 lis r7,0xF300 /* Address of SCC rounded to 128k */
743 ori r7,r7,0x0032 /* Make it cache inhibited */
744 mtdbatl 3,r7 /* Load DBAT 3 low */
745 lis r7,0xF300 /* Address of SCC rounded to 128k */
746 ori r7,r7,0x0002 /* Make it supervisor only */
747 mtdbatu 3,r7 /* Load DBAT 3 high */
748 ori r12,r12,0x0010 /* Turn on DR */
749 mtmsr r12 /* Smash the MSR */
750 isync /* Make it clean */
751
752 #endif
753 #endif
754
755 dbgDprintr: sync
756 #if 0
757 mr r7,r10 /* (TEST/DEBUG) */
758 bl dumpr7 /* (TEST/DEBUG) */
759 #endif
760
761 dcbi 0,r10 /* Toss it */
762 eieio
763
764 #if 0
765 lis r12,0xF301 /* (TEST/DEBUG) */
766 ori r12,r12,0x2002 /* (TEST/DEBUG) */
767 dcbf 0,r12 /* (TEST/DEBUG) */
768 sync /* (TEST/DEBUG) */
769 dcbi 0,r12 /* (TEST/DEBUG) */
770 eieio /* (TEST/DEBUG) */
771 li r7,0x37 /* (TEST/DEBUG) */
772 stb r7,4(r12) /* (TEST/DEBUG) */
773
774 lis r7,12 /* (TEST/DEBUG) */
775 spw8: addi r7,r7,-1 /* (TEST/DEBUG) */
776 mr. r7,r7 /* (TEST/DEBUG) */
777 bne- spw8 /* (TEST/DEBUG) */
778 dcbf 0,r12 /* (TEST/DEBUG) */
779 sync /* (TEST/DEBUG) */
780 dcbi 0,r12 /* (TEST/DEBUG) */
781 eieio /* (TEST/DEBUG) */
782 #endif
783
784
785 /* Print the ID parameter */
786
787 lis r12,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
788 ori r12,r12,LOW_ADDR(fwdisplock) /* Last part */
789
790 lwarx r7,0,r12 ; ?
791
792 ddwait0: lwarx r7,0,r12 /* Get the lock */
793 mr. r7,r7 /* Is it locked? */
794 bne- ddwait0 /* Yup... */
795 stwcx. r12,0,r12 /* Try to get it */
796 bne- ddwait0 /* Nope, start all over... */
797
798 #if 0
799 dcbf 0,r10 /* (TEST/DEBUG) */
800 sync /* (TEST/DEBUG) */
801 dcbi 0,r10 /* (TEST/DEBUG) */
802 eieio /* (TEST/DEBUG) */
803 li r7,0x38 /* (TEST/DEBUG) */
804 stb r7,6(r10) /* (TEST/DEBUG) */
805
806 lis r7,10 /* (TEST/DEBUG) */
807 spwa: addi r7,r7,-1 /* (TEST/DEBUG) */
808 mr. r7,r7 /* (TEST/DEBUG) */
809 bne- spwa /* (TEST/DEBUG) */
810 dcbf 0,r10 /* (TEST/DEBUG) */
811 sync /* (TEST/DEBUG) */
812 dcbi 0,r10 /* (TEST/DEBUG) */
813 eieio /* (TEST/DEBUG) */
814 #endif
815
816 rlwinm r3,r3,8,0,31 /* Get the first character */
817 bl dbgDchar /* Print it */
818 rlwinm r3,r3,8,0,31 /* Get the second character */
819 bl dbgDchar /* Print it */
820 rlwinm r3,r3,8,0,31 /* Get the third character */
821 bl dbgDchar /* Print it */
822 rlwinm r3,r3,8,0,31 /* Get the fourth character */
823 bl dbgDchar /* Print it */
824
825 li r3,0x20 /* Get a space for a separator */
826 bl dbgDchar /* Print it */
827 bl dbg4byte /* Print register 5 in hex */
828
829 li r3,0x0A /* Linefeed */
830 bl dbgDchar /* Send it */
831 li r3,0x0D /* Carriage return */
832 bl dbgDchar /* Send it */
833
834 mtlr r11 /* Get back the return */
835 #if !SIMPLESCC && !NOTQUITEASSIMPLE
836 li r7,0 /* Get a zero */
837 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */
838 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */
839 #endif
840 lis r12,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
841 li r7,0 /* Get a zero */
842 ori r12,r12,LOW_ADDR(fwdisplock) /* Last part */
843 dcbi 0,r10 /* ? */
844 stw r7,0(r12) /* Release the display lock */
845 mtmsr r8 /* Restore the MSR */
846 isync /* Wait for it */
847 blr /* Leave... */
848
849
850 dbg4byte: mflr r12 /* Save the return */
851
852 lis r4,HIGH_ADDR(hexTab) /* Point to the top of table */
853 li r6,8 /* Set number of hex digits to dump */
854 ori r4,r4,LOW_ADDR(hexTab) /* Point to the bottom of table */
855
856 dbgDnext: rlwinm r5,r5,4,0,31 /* Rotate a nybble */
857 subi r6,r6,1 /* Back down the count */
858 rlwinm r3,r5,0,28,31 /* Isolate the last nybble */
859 lbzx r3,r4,r3 /* Convert to ascii */
860 bl dbgDchar /* Print it */
861 mr. r6,r6 /* Any more? */
862 bne+ dbgDnext /* Convert 'em all... */
863
864 li r3,0x20 /* Space */
865 bl dbgDchar /* Send it */
866 mtlr r12 /* Restore LR */
867 blr /* Return... */
868
869 /* Write to whichever serial port. Try to leave it clean, but not too hard (this is a hack) */
870
871 dbgDchar:
872 #if SIMPLESCC && !NOTQUITEASSIMPLE
873 stb r3,0(r10) /* ? */
874 dcbf 0,r10 /* Force it out */
875 sync /* Make sure it's out there */
876
877 lis r7,3 /* Get enough for about 1ms */
878
879 dbgDchar0: addi r7,r7,-1 /* Count down */
880 mr. r7,r7 /* Waited long enough? */
881 bgt+ dbgDchar0 /* Nope... */
882 #endif
883 #if NOTQUITEASSIMPLE
884 #if 0
885 li r7,0x01 /* ? */
886 stb r7,0(r10) /* ? */
887 dcbf 0,r10 /* Force it out */
888 sync /* Make sure it's out there */
889 dcbi 0,r10
890 eieio
891
892 lbz r7,0(r10) /* ? */
893 dcbi 0,r10 /* Force it out */
894 sync /* kill it off */
895 eieio
896
897 li r7,0x00 /* ? */
898 stb r7,0(r10) /* ? */
899 dcbf 0,r10 /* Force it out */
900 sync /* Make sure it's out there */
901 dcbi 0,r10
902 eieio
903
904 lbz r7,0(r10) /* ? */
905 dcbi 0,r10 /* Force it out */
906 sync /* kill it off */
907 eieio
908 #endif
909
910 qrw1: eieio /* Barricade it */
911 lbz r7,0(r10) /* ? */
912 dcbi 0,r10
913 sync
914 andi. r7,r7,0x04 /* ? */
915 beq qrw1 /* Nope... */
916
917 eieio
918
919 stb r3,4(r10) /* ? */
920 dcbf 0,r10 /* Force it out */
921 sync /* Make sure it's out there */
922 dcbi 0,r10
923 eieio
924
925 qrw2: eieio /* Barricade it */
926 lbz r7,0(r10) /* ? */
927 dcbi 0,r10
928 sync
929 andi. r7,r7,0x04 /* ? */
930 beq qrw2 /* Nope... */
931
932 #if 0
933 eieio
934 li r7,0x10 /* ? */
935 stb r7,0(r10) /* ? */
936 dcbf 0,r10 /* Force it out */
937 sync /* Make sure it's out there */
938 dcbi 0,r10
939 eieio
940
941 lbz r7,0(r10) /* ? */
942 dcbi 0,r10 /* Force it out */
943 sync /* kill it off */
944 eieio
945 #endif
946
947 lis r7,0x0080 /* ? */
948 lis r9,0xF300 /* ? */
949 ori r7,r7,0x010F /* ? */
950 stw r7,0x28(r9) /* ? */
951 dcbf 0,r10 /* Force it out */
952 sync /* Make sure it's out there */
953 dcbi 0,r10
954 eieio
955
956 #endif
957 #if !SIMPLESCC && !NOTQUITEASSIMPLE
958 rlwinm r9,r10,0,0,29 /* Get channel a */
959 eieio /* Barricade it */
960
961 li r7,0x03 /* ? */
962 stb r7,0(r9) /* ? */
963 eieio /* Barricade it */
964
965 lbz r7,0(r9) /* ? */
966
967 eieio /* Barricade it */
968 lbz r7,0(r9) /* ? */
969
970 dchrw1: eieio /* Barricade it */
971 lbz r7,0(r10) /* ? */
972 andi. r7,r7,0x04 /* ? */
973 beq dchrw1 /* Nope... */
974
975 stb r3,4(r10) /* ? */
976 sync /* Make sure it's there */
977 eieio /* Don't get confused */
978
979 dchrw2: eieio /* Barricade it */
980 lbz r7,0(r10) /* ? */
981 andi. r7,r7,0x04 /* ? */
982 beq dchrw2 /* Nope... */
983
984 eieio /* Avoid confusion */
985 lbz r7,0(r10) /* ? */
986 andi. r7,r7,0x40 /* ? */
987 beq+ nounder /* Nope... */
988
989 eieio /* Avoid confusion */
990 li r7,0xC0 /* ? */
991 stb r7,0(r10) /* ? */
992
993 nounder: eieio /* Avoid confusion */
994 li r7,0x10 /* ? */
995 stb r7,0(r10) /* ? */
996
997 eieio /* Avoid confusion */
998 li r7,0x38 /* ? */
999 stb r7,0(r9) /* ? */
1000
1001 eieio /* Avoid confusion */
1002 li r7,0x30 /* ? */
1003 stb r7,0(r10) /* ? */
1004
1005 eieio /* Avoid confusion */
1006 li r7,0x20 /* ? */
1007 stb r7,0(r10) /* ? */
1008 eieio /* Avoid confusion */
1009 sync
1010
1011 #endif
1012 blr /* Return */
1013
1014 .globl hexTab
1015
1016 hexTab: STRINGD "0123456789ABCDEF" /* Convert hex numbers to printable hex */
1017
1018
1019 /*
1020 * Dumps all the registers in the savearea in R13
1021 */
1022
1023
1024 ENTRY(dbgRegsLL, TAG_NO_FRAME_USED)
1025
1026 li r3,0 /* ? */
1027 bl dbgRegsCm /* Join on up... */
1028
1029 /*
1030 * Note that we bypass the normal return 'cause we don't wanna mess up R3
1031 */
1032 mfsprg r11,0 /* Get the per_proc */
1033 lwz r11,PP_TEMPWORK1(r11) /* Get our return point */
1034 li r3,T_IN_VAIN /* Tell the vector handler that we took care of it */
1035 mtlr r11 /* Set the return */
1036 blr /* Bye, dudes... */
1037
1038 ENTRY(dbgRegs, TAG_NO_FRAME_USED)
1039
1040 dbgRegsCm: mfmsr r8 /* Save the MSR */
1041 mr. r3,r3 /* ? */
1042 rlwinm r12,r8,0,28,25 /* Turn off translation */
1043 lis r10,0xF301 /* Set the top part */
1044 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
1045 mtmsr r12 /* Smash the MSR */
1046 isync /* Make it clean */
1047 #if SIMPLESCC && !NOTQUITEASSIMPLE
1048 ori r10,r10,0x3010 /* ? */
1049 #else
1050 ori r10,r10,0x2000 /* ? */
1051 #endif
1052 mflr r11 /* Save the link register */
1053 beq+ dbgDprints /* It sure are... */
1054 #if SIMPLESCC && !NOTQUITEASSIMPLE
1055 ori r10,r10,0x0020 /* ? */
1056 #else
1057 ori r10,r10,0x0002 /* ? */
1058
1059 dcbf 0,r10 /* Insure it is out */
1060 sync
1061 dcbi 0,r10 /* Toss it */
1062 #if !NOTQUITEASSIMPLE
1063 lis r7,0xF300 /* ? */
1064 ori r7,r7,0x0032 /* ? */
1065 mtdbatl 3,r7 /* ? */
1066 lis r7,0xF300 /* ? */
1067 ori r7,r7,0x0002 /* ? */
1068 mtdbatu 3,r7 /* ? */
1069 ori r12,r12,0x0010 /* ? */
1070 mtmsr r12 /* ? */
1071 isync /* ? */
1072 #endif
1073 #endif
1074
1075 dbgDprints:
1076 lis r3,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
1077 ori r3,r3,LOW_ADDR(fwdisplock) /* Last part */
1078
1079 lwarx r5,0,r3 ; ?
1080 ddwait1: lwarx r5,0,r3 /* Get the lock */
1081 mr. r5,r5 /* Is it locked? */
1082 bne- ddwait1 /* Yup... */
1083 stwcx. r3,0,r3 /* Try to get it */
1084 bne- ddwait1 /* Nope, start all over... */
1085
1086 li r3,0x52 /* Print eyecatcher */
1087 bl dbgDchar /* Send it */
1088 li r3,0x65 /* Print eyecatcher */
1089 bl dbgDchar /* Send it */
1090 li r3,0x67 /* Print eyecatcher */
1091 bl dbgDchar /* Send it */
1092 li r3,0x73 /* Print eyecatcher */
1093 bl dbgDchar /* Send it */
1094 li r3,0x20 /* Print eyecatcher */
1095 bl dbgDchar /* Send it */
1096
1097 lwz r5,saver0(r13) /* Do register */
1098 bl dbg4byte /* Print */
1099 lwz r5,saver1(r13) /* Do register */
1100 bl dbg4byte /* Print */
1101 lwz r5,saver2(r13) /* Do register */
1102 bl dbg4byte /* Print */
1103 lwz r5,saver3(r13) /* Do register */
1104 bl dbg4byte /* Print */
1105 li r3,0x0A /* Linefeed */
1106 bl dbgDchar /* Send it */
1107 li r3,0x0D /* Carriage return */
1108 bl dbgDchar /* Send it */
1109
1110 li r3,0x20 /* Print eyecatcher */
1111 bl dbgDchar /* Send it */
1112 li r3,0x20 /* Print eyecatcher */
1113 bl dbgDchar /* Send it */
1114 li r3,0x20 /* Print eyecatcher */
1115 bl dbgDchar /* Send it */
1116 li r3,0x20 /* Print eyecatcher */
1117 bl dbgDchar /* Send it */
1118 li r3,0x20 /* Print eyecatcher */
1119 bl dbgDchar /* Send it */
1120 lwz r5,saver4(r13) /* Do register */
1121 bl dbg4byte /* Print */
1122 lwz r5,saver5(r13) /* Do register */
1123 bl dbg4byte /* Print */
1124 lwz r5,saver6(r13) /* Do register */
1125 bl dbg4byte /* Print */
1126 lwz r5,saver7(r13) /* Do register */
1127 bl dbg4byte /* Print */
1128 li r3,0x0A /* Linefeed */
1129 bl dbgDchar /* Send it */
1130 li r3,0x0D /* Carriage return */
1131 bl dbgDchar /* Send it */
1132
1133 li r3,0x20 /* Print eyecatcher */
1134 bl dbgDchar /* Send it */
1135 li r3,0x20 /* Print eyecatcher */
1136 bl dbgDchar /* Send it */
1137 li r3,0x20 /* Print eyecatcher */
1138 bl dbgDchar /* Send it */
1139 li r3,0x20 /* Print eyecatcher */
1140 bl dbgDchar /* Send it */
1141 li r3,0x20 /* Print eyecatcher */
1142 bl dbgDchar /* Send it */
1143 lwz r5,saver8(r13) /* Do register */
1144 bl dbg4byte /* Print */
1145 lwz r5,saver9(r13) /* Do register */
1146 bl dbg4byte /* Print */
1147 lwz r5,saver10(r13) /* Do register */
1148 bl dbg4byte /* Print */
1149 lwz r5,saver11(r13) /* Do register */
1150 bl dbg4byte /* Print */
1151 li r3,0x0A /* Linefeed */
1152 bl dbgDchar /* Send it */
1153 li r3,0x0D /* Carriage return */
1154 bl dbgDchar /* Send it */
1155
1156 li r3,0x20 /* Print eyecatcher */
1157 bl dbgDchar /* Send it */
1158 li r3,0x20 /* Print eyecatcher */
1159 bl dbgDchar /* Send it */
1160 li r3,0x20 /* Print eyecatcher */
1161 bl dbgDchar /* Send it */
1162 li r3,0x20 /* Print eyecatcher */
1163 bl dbgDchar /* Send it */
1164 li r3,0x20 /* Print eyecatcher */
1165 bl dbgDchar /* Send it */
1166 lwz r5,saver12(r13) /* Do register */
1167 bl dbg4byte /* Print */
1168 lwz r5,saver13(r13) /* Do register */
1169 bl dbg4byte /* Print */
1170 lwz r5,saver14(r13) /* Do register */
1171 bl dbg4byte /* Print */
1172 lwz r5,saver15(r13) /* Do register */
1173 bl dbg4byte /* Print */
1174 li r3,0x0A /* Linefeed */
1175 bl dbgDchar /* Send it */
1176 li r3,0x0D /* Carriage return */
1177 bl dbgDchar /* Send it */
1178
1179 li r3,0x20 /* Print eyecatcher */
1180 bl dbgDchar /* Send it */
1181 li r3,0x20 /* Print eyecatcher */
1182 bl dbgDchar /* Send it */
1183 li r3,0x20 /* Print eyecatcher */
1184 bl dbgDchar /* Send it */
1185 li r3,0x20 /* Print eyecatcher */
1186 bl dbgDchar /* Send it */
1187 li r3,0x20 /* Print eyecatcher */
1188 bl dbgDchar /* Send it */
1189 lwz r5,saver16(r13) /* Do register */
1190 bl dbg4byte /* Print */
1191 lwz r5,saver17(r13) /* Do register */
1192 bl dbg4byte /* Print */
1193 lwz r5,saver18(r13) /* Do register */
1194 bl dbg4byte /* Print */
1195 lwz r5,saver19(r13) /* Do register */
1196 bl dbg4byte /* Print */
1197 li r3,0x0A /* Linefeed */
1198 bl dbgDchar /* Send it */
1199 li r3,0x0D /* Carriage return */
1200 bl dbgDchar /* Send it */
1201
1202 li r3,0x20 /* Print eyecatcher */
1203 bl dbgDchar /* Send it */
1204 li r3,0x20 /* Print eyecatcher */
1205 bl dbgDchar /* Send it */
1206 li r3,0x20 /* Print eyecatcher */
1207 bl dbgDchar /* Send it */
1208 li r3,0x20 /* Print eyecatcher */
1209 bl dbgDchar /* Send it */
1210 li r3,0x20 /* Print eyecatcher */
1211 bl dbgDchar /* Send it */
1212 lwz r5,saver20(r13) /* Do register */
1213 bl dbg4byte /* Print */
1214 lwz r5,saver21(r13) /* Do register */
1215 bl dbg4byte /* Print */
1216 lwz r5,saver22(r13) /* Do register */
1217 bl dbg4byte /* Print */
1218 lwz r5,saver23(r13) /* Do register */
1219 bl dbg4byte /* Print */
1220 li r3,0x0A /* Linefeed */
1221 bl dbgDchar /* Send it */
1222 li r3,0x0D /* Carriage return */
1223 bl dbgDchar /* Send it */
1224
1225 li r3,0x20 /* Print eyecatcher */
1226 bl dbgDchar /* Send it */
1227 li r3,0x20 /* Print eyecatcher */
1228 bl dbgDchar /* Send it */
1229 li r3,0x20 /* Print eyecatcher */
1230 bl dbgDchar /* Send it */
1231 li r3,0x20 /* Print eyecatcher */
1232 bl dbgDchar /* Send it */
1233 li r3,0x20 /* Print eyecatcher */
1234 bl dbgDchar /* Send it */
1235 lwz r5,saver24(r13) /* Do register */
1236 bl dbg4byte /* Print */
1237 lwz r5,saver25(r13) /* Do register */
1238 bl dbg4byte /* Print */
1239 lwz r5,saver26(r13) /* Do register */
1240 bl dbg4byte /* Print */
1241 lwz r5,saver27(r13) /* Do register */
1242 bl dbg4byte /* Print */
1243 li r3,0x0A /* Linefeed */
1244 bl dbgDchar /* Send it */
1245 li r3,0x0D /* Carriage return */
1246 bl dbgDchar /* Send it */
1247
1248 li r3,0x20 /* Print eyecatcher */
1249 bl dbgDchar /* Send it */
1250 li r3,0x20 /* Print eyecatcher */
1251 bl dbgDchar /* Send it */
1252 li r3,0x20 /* Print eyecatcher */
1253 bl dbgDchar /* Send it */
1254 li r3,0x20 /* Print eyecatcher */
1255 bl dbgDchar /* Send it */
1256 li r3,0x20 /* Print eyecatcher */
1257 bl dbgDchar /* Send it */
1258 lwz r5,saver28(r13) /* Do register */
1259 bl dbg4byte /* Print */
1260 lwz r5,saver29(r13) /* Do register */
1261 bl dbg4byte /* Print */
1262 lwz r5,saver30(r13) /* Do register */
1263 bl dbg4byte /* Print */
1264 lwz r5,saver31(r13) /* Do register */
1265 bl dbg4byte /* Print */
1266 li r3,0x0A /* Linefeed */
1267 bl dbgDchar /* Send it */
1268 li r3,0x0D /* Carriage return */
1269 bl dbgDchar /* Send it */
1270
1271 /* Segment registers */
1272
1273 li r3,0x53 /* Print eyecatcher */
1274 bl dbgDchar /* Send it */
1275 li r3,0x65 /* Print eyecatcher */
1276 bl dbgDchar /* Send it */
1277 li r3,0x67 /* Print eyecatcher */
1278 bl dbgDchar /* Send it */
1279 li r3,0x73 /* Print eyecatcher */
1280 bl dbgDchar /* Send it */
1281 li r3,0x20 /* Print eyecatcher */
1282 bl dbgDchar /* Send it */
1283
1284 lwz r5,savesr0(r13) /* Do register */
1285 bl dbg4byte /* Print */
1286 lwz r5,savesr1(r13) /* Do register */
1287 bl dbg4byte /* Print */
1288 lwz r5,savesr2(r13) /* Do register */
1289 bl dbg4byte /* Print */
1290 lwz r5,savesr3(r13) /* Do register */
1291 bl dbg4byte /* Print */
1292 li r3,0x0A /* Linefeed */
1293 bl dbgDchar /* Send it */
1294 li r3,0x0D /* Carriage return */
1295 bl dbgDchar /* Send it */
1296
1297 li r3,0x20 /* Print eyecatcher */
1298 bl dbgDchar /* Send it */
1299 li r3,0x20 /* Print eyecatcher */
1300 bl dbgDchar /* Send it */
1301 li r3,0x20 /* Print eyecatcher */
1302 bl dbgDchar /* Send it */
1303 li r3,0x20 /* Print eyecatcher */
1304 bl dbgDchar /* Send it */
1305 li r3,0x20 /* Print eyecatcher */
1306 bl dbgDchar /* Send it */
1307 lwz r5,savesr4(r13) /* Do register */
1308 bl dbg4byte /* Print */
1309 lwz r5,savesr5(r13) /* Do register */
1310 bl dbg4byte /* Print */
1311 lwz r5,savesr6(r13) /* Do register */
1312 bl dbg4byte /* Print */
1313 lwz r5,savesr7(r13) /* Do register */
1314 bl dbg4byte /* Print */
1315 li r3,0x0A /* Linefeed */
1316 bl dbgDchar /* Send it */
1317 li r3,0x0D /* Carriage return */
1318 bl dbgDchar /* Send it */
1319
1320 li r3,0x20 /* Print eyecatcher */
1321 bl dbgDchar /* Send it */
1322 li r3,0x20 /* Print eyecatcher */
1323 bl dbgDchar /* Send it */
1324 li r3,0x20 /* Print eyecatcher */
1325 bl dbgDchar /* Send it */
1326 li r3,0x20 /* Print eyecatcher */
1327 bl dbgDchar /* Send it */
1328 li r3,0x20 /* Print eyecatcher */
1329 bl dbgDchar /* Send it */
1330 lwz r5,savesr8(r13) /* Do register */
1331 bl dbg4byte /* Print */
1332 lwz r5,savesr9(r13) /* Do register */
1333 bl dbg4byte /* Print */
1334 lwz r5,savesr10(r13) /* Do register */
1335 bl dbg4byte /* Print */
1336 lwz r5,savesr11(r13) /* Do register */
1337 bl dbg4byte /* Print */
1338 li r3,0x0A /* Linefeed */
1339 bl dbgDchar /* Send it */
1340 li r3,0x0D /* Carriage return */
1341 bl dbgDchar /* Send it */
1342
1343 li r3,0x20 /* Print eyecatcher */
1344 bl dbgDchar /* Send it */
1345 li r3,0x20 /* Print eyecatcher */
1346 bl dbgDchar /* Send it */
1347 li r3,0x20 /* Print eyecatcher */
1348 bl dbgDchar /* Send it */
1349 li r3,0x20 /* Print eyecatcher */
1350 bl dbgDchar /* Send it */
1351 li r3,0x20 /* Print eyecatcher */
1352 bl dbgDchar /* Send it */
1353 lwz r5,savesr12(r13) /* Do register */
1354 bl dbg4byte /* Print */
1355 lwz r5,savesr13(r13) /* Do register */
1356 bl dbg4byte /* Print */
1357 lwz r5,savesr14(r13) /* Do register */
1358 bl dbg4byte /* Print */
1359 lwz r5,savesr15(r13) /* Do register */
1360 bl dbg4byte /* Print */
1361 li r3,0x0A /* Linefeed */
1362 bl dbgDchar /* Send it */
1363 li r3,0x0D /* Carriage return */
1364 bl dbgDchar /* Send it */
1365
1366 li r3,0x30 /* Print eyecatcher */
1367 bl dbgDchar /* Send it */
1368 li r3,0x31 /* Print eyecatcher */
1369 bl dbgDchar /* Send it */
1370 li r3,0x64 /* Print eyecatcher */
1371 bl dbgDchar /* Send it */
1372 li r3,0x64 /* Print eyecatcher */
1373 bl dbgDchar /* Send it */
1374 li r3,0x20 /* Print eyecatcher */
1375 bl dbgDchar /* Send it */
1376 lwz r5,savesrr0(r13) /* Do register */
1377 bl dbg4byte /* Print */
1378 lwz r5,savesrr1(r13) /* Do register */
1379 bl dbg4byte /* Print */
1380 lwz r5,savedar(r13) /* Do register */
1381 bl dbg4byte /* Print */
1382 lwz r5,savedsisr(r13) /* Do register */
1383 bl dbg4byte /* Print */
1384 li r3,0x0A /* Linefeed */
1385 bl dbgDchar /* Send it */
1386 li r3,0x0D /* Carriage return */
1387 bl dbgDchar /* Send it */
1388
1389 li r3,0x20 /* Print eyecatcher */
1390 bl dbgDchar /* Send it */
1391 li r3,0x6C /* Print eyecatcher */
1392 bl dbgDchar /* Send it */
1393 li r3,0x63 /* Print eyecatcher */
1394 bl dbgDchar /* Send it */
1395 li r3,0x63 /* Print eyecatcher */
1396 bl dbgDchar /* Send it */
1397 li r3,0x20 /* Print eyecatcher */
1398 bl dbgDchar /* Send it */
1399 lwz r5,savelr(r13) /* Do register */
1400 bl dbg4byte /* Print */
1401 lwz r5,savecr(r13) /* Do register */
1402 bl dbg4byte /* Print */
1403 lwz r5,savectr(r13) /* Do register */
1404 bl dbg4byte /* Print */
1405 li r3,0x0A /* Linefeed */
1406 bl dbgDchar /* Send it */
1407 li r3,0x0D /* Carriage return */
1408 bl dbgDchar /* Send it */
1409 mtlr r11 /* Get back the return */
1410 dcbi 0,r10 /* ? */
1411 #if !SIMPLESCC && !NOTQUITEASSIMPLE
1412 li r7,0 /* Get a zero */
1413 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */
1414 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */
1415 #endif
1416 lis r3,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
1417 li r7,0 /* Get a zero */
1418 ori r3,r3,LOW_ADDR(fwdisplock) /* Last part */
1419 stw r7,0(r3) /* Clear display lock */
1420 mtmsr r8 /* Restore the MSR */
1421 isync /* Wait for it */
1422 blr /* Leave... */
1423
1424
1425 /*
1426 * Used for debugging to leave stuff in 0x380-0x3FF (128 bytes).
1427 * Mapping is V=R. Stores and loads are real.
1428 */
1429
1430 ENTRY(dbgCkpt, TAG_NO_FRAME_USED)
1431
1432 mr r12,r0 /* Keep R0 pristene */
1433 lis r0,HIGH_ADDR(dbgCkptCall) /* Top half of dbgCkptCall firmware call number */
1434 ori r0,r0,LOW_ADDR(dbgCkptCall) /* Bottom half */
1435
1436 sc /* Go stash the stuff */
1437
1438 mr r0,r12 /* Restore R0 */
1439 blr /* Return... */
1440
1441 /* Here's the low-level part of dbgCkpt */
1442
1443 ENTRY(dbgCkptLL, TAG_NO_FRAME_USED)
1444
1445 li r12,0x380 /* Point to output area */
1446 li r1,32 /* Get line size */
1447 dcbz 0,r12 /* Make sure we don't fetch a cache line */
1448
1449 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1450
1451 dcbt r1,r3 /* Start in the next line */
1452
1453 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1454 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1455 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1456 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1457 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1458 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1459 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1460
1461 add r3,r3,r1 /* Bump input */
1462
1463 stw r4,0x00(r12) /* Store it */
1464 stw r5,0x04(r12) /* Store it */
1465 stw r6,0x08(r12) /* Store it */
1466 stw r7,0x0C(r12) /* Store it */
1467 stw r8,0x10(r12) /* Store it */
1468 stw r9,0x14(r12) /* Store it */
1469 stw r10,0x18(r12) /* Store it */
1470 stw r11,0x1C(r12) /* Store it */
1471
1472 dcbz r1,r12 /* Clear the next line */
1473 add r12,r12,r1 /* Point to next output line */
1474
1475 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1476 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1477 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1478 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1479 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1480 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1481 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1482 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1483
1484 dcbt r1,r3 /* Touch the next line */
1485 add r3,r3,r1 /* Point to next input line */
1486
1487 stw r4,0x00(r12) /* Store it */
1488 stw r5,0x04(r12) /* Store it */
1489 stw r6,0x08(r12) /* Store it */
1490 stw r7,0x0C(r12) /* Store it */
1491 stw r8,0x10(r12) /* Store it */
1492 stw r9,0x14(r12) /* Store it */
1493 stw r10,0x18(r12) /* Store it */
1494 stw r11,0x1C(r12) /* Store it */
1495
1496 dcbz r1,r12 /* Clear the next line */
1497 add r12,r12,r1 /* Point to next output line */
1498
1499 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1500 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1501 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1502 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1503 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1504 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1505 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1506 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1507
1508 dcbt r1,r3 /* Touch the next line */
1509 add r3,r3,r1 /* Point to next input line */
1510
1511 stw r4,0x00(r12) /* Store it */
1512 stw r5,0x04(r12) /* Store it */
1513 stw r6,0x08(r12) /* Store it */
1514 stw r7,0x0C(r12) /* Store it */
1515 stw r8,0x10(r12) /* Store it */
1516 stw r9,0x14(r12) /* Store it */
1517 stw r10,0x18(r12) /* Store it */
1518 stw r11,0x1C(r12) /* Store it */
1519
1520 dcbz r1,r12 /* Clear the next line */
1521 add r12,r12,r1 /* Point to next output line */
1522
1523 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1524 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1525 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1526 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1527 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1528 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1529 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1530 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1531
1532 stw r4,0x00(r12) /* Store it */
1533 stw r5,0x04(r12) /* Store it */
1534 stw r6,0x08(r12) /* Store it */
1535 stw r7,0x0C(r12) /* Store it */
1536 stw r8,0x10(r12) /* Store it */
1537 stw r9,0x14(r12) /* Store it */
1538 stw r10,0x18(r12) /* Store it */
1539 stw r11,0x1C(r12) /* Store it */
1540
1541 blr
1542
1543
1544 /*
1545 * Do Preemption. Forces a T_PREEMPT trap to allow a preemption to occur.
1546 */
1547
1548 ENTRY(DoPreemptLL, TAG_NO_FRAME_USED)
1549
1550 mfsprg r11,0 /* Get the per_proc address */
1551 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1552 li r3,T_PREEMPT /* Set preemption interrupt value */
1553 mtlr r11 /* Restore the LR */
1554 stw r3,saveexception(r13) /* Modify the exception type to preemption */
1555 blr /* Return to interrupt handler */
1556
1557
1558 /*
1559 * Force 'rupt handler to dispatch with new context
1560 * R3 at the call contains the new savearea.
1561 * R4 at the call contains a return code to pass back in R3.
1562 * Forces a T_CSWITCH
1563 */
1564
1565 ENTRY(SwitchContextLL, TAG_NO_FRAME_USED)
1566
1567 mfsprg r11,0 /* Get the per_proc address */
1568 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1569 li r3,T_CSWITCH /* Set context switch value */
1570 mtlr r11 /* Restore the LR */
1571 stw r3,saveexception(r13) /* Modify the exception type to switch context */
1572 blr /* Return to interrupt handler */
1573
1574
1575 /*
1576 * Create a fake I/O 'rupt.
1577 * Forces a T_INTERRUPT trap to pretend that an actual I/O interrupt occurred.
1578 */
1579
1580 ENTRY(CreateFakeIOLL, TAG_NO_FRAME_USED)
1581
1582 mfsprg r11,0 /* Get the per_proc address */
1583 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1584 li r3,T_INTERRUPT /* Set external interrupt value */
1585 mtlr r11 /* Restore the LR */
1586 stw r3,saveexception(r13) /* Modify the exception type to external */
1587 blr /* Return to interrupt handler */
1588
1589 /*
1590 * Create a shutdown context
1591 * Forces a T_SHUTDOWN trap.
1592 */
1593
1594 ENTRY(CreateShutdownCTXLL, TAG_NO_FRAME_USED)
1595
1596 mfsprg r11,0 /* Get the per_proc address */
1597 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1598 li r3,T_SHUTDOWN /* Set external interrupt value */
1599 mtlr r11 /* Restore the LR */
1600 stw r3,saveexception(r13) /* Modify the exception type to external */
1601 blr /* Return to interrupt handler */
1602
1603 /*
1604 * Create a fake decrementer 'rupt.
1605 * Forces a T_DECREMENTER trap to pretend that an actual decrementer interrupt occurred.
1606 */
1607
1608 ENTRY(CreateFakeDECLL, TAG_NO_FRAME_USED)
1609
1610 mfsprg r11,0 /* Get the per_proc address */
1611 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1612 li r3,T_DECREMENTER /* Set decrementer interrupt value */
1613 mtlr r11 /* Restore the LR */
1614 stw r3,saveexception(r13) /* Modify the exception type to external */
1615 blr /* Return to interrupt handler */
1616
1617 /*
1618 * Choke the system.
1619 */
1620
1621 ENTRY(DoChokeLL, TAG_NO_FRAME_USED)
1622
1623 mfsprg r11,0 ; Get the per_proc address
1624 lwz r11,PP_TEMPWORK1(r11) ; Restore the return address
1625 li r3,T_CHOKE ; Set external interrupt value
1626 mtlr r11 ; Restore the LR
1627 stw r3,saveexception(r13) ; Modify the exception type to external
1628 blr ; Return to interrupt handler
1629
1630 /*
1631 * Set the low level trace flags
1632 */
1633
1634 ENTRY(LLTraceSet, TAG_NO_FRAME_USED)
1635
1636 mfsprg r6,2 ; Get feature flags
1637 mfmsr r12 /* Get the MSR */
1638 mr r4,r3 /* Save the new value */
1639 andi. r3,r12,0x01C0 /* Clear interrupts and translation */
1640 mtcrf 0x04,r6 ; Set the features
1641 bt pfNoMSRirb,ltsNoMSR ; Use MSR...
1642
1643 mtmsr r3 ; Translation and all off
1644 isync ; Toss prefetch
1645 b ltsNoMSRx
1646
1647 ltsNoMSR: li r0,loadMSR ; Get the MSR setter SC
1648 sc ; Set it
1649
1650 ltsNoMSRx:
1651
1652 lis r5,hi16(EXT(trcWork)) ; Get trace area
1653 ori r5,r5,lo16(EXT(trcWork)) ; again
1654
1655 lwz r3,traceMask(r5) /* Get the old trace flags to pass back */
1656 stw r4,traceMask(r5) /* Replace with the new ones */
1657
1658 mtmsr r12 /* Restore the MSR */
1659 isync
1660
1661 blr /* Leave... */
1662
1663 #if 1
1664
1665 /*
1666 ; ***************************************************************************
1667 ;
1668 ; ----------------- Grateful Deb ----------------
1669 ;
1670 ; Debugging: direct draw into main screen menu bar
1671 ;
1672 ; Takes R4 value, converts it to hex characters and displays it.
1673 ;
1674 ; Gotta make sure the DCBST is done to force the pixels from the cache.
1675 ;
1676 ; Position is taken as column, row (0 based) from R3.
1677 ; Characters are from hexfont, and are 16x16 pixels.
1678 ;
1679 ; Only works with two processors so far
1680 ;
1681 ;
1682 ; ***************************************************************************
1683 */
1684
1685 #define GDfromright 20
1686 #define GDfontsize 16
1687
1688 ENTRY(GratefulDeb,TAG_NO_FRAME_USED)
1689 mfspr r6,pir /* Get the PIR */
1690 lis r5,HIGH_ADDR(EXT(GratefulDebWork)) /* Point to our work area */
1691 rlwinm r6,r6,8,23,23 /* Get part of the offset to our processors area */
1692 ori r5,r5,LOW_ADDR(EXT(GratefulDebWork)) /* Start building the address */
1693 rlwimi r6,r6,2,21,21 /* Get the rest of the offset to our processors area */
1694 add r6,r6,r5 /* Point at our CPU's work area */
1695 mfmsr r5 /* Get that MSR */
1696 stmw r0,GDsave(r6) /* Save all registers */
1697 lwz r10,GDready(r6) /* See if we're all ready to go */
1698 ori r0,r5,0x2000 /* Turn on the floating point */
1699 mr r31,r6 /* Get a more sane base register */
1700 mr. r10,r10 /* Are we all set? */
1701 mtmsr r0 /* Enable floating point */
1702 isync
1703
1704 stfd f0,GDfp0(r31) /* Save FP */
1705 stfd f1,GDfp1(r31) /* Save FP */
1706 stfd f2,GDfp2(r31) /* Save FP */
1707 stfd f3,GDfp3(r31) /* Save FP */
1708
1709 beq- GDbailout /* Go and bail... */
1710
1711 rlwinm r25,r3,0,16,31 /* Isolate just the row number */
1712 lwz r28,GDtopleft(r31) /* Get the physical address of our line 0 */
1713 rlwinm r3,r3,16,16,31 /* Isolate the column number */
1714 lwz r27,GDrowbytes(r31) /* Get the number of bytes per row */
1715 lwz r9,GDrowchar(r31) /* Get the number of bytes per row of full leaded charactrers */
1716 lwz r26,GDdepth(r31) /* Get the bit depth */
1717 mullw r25,r25,r9 /* get offset to the row to write in bytes */
1718 lwz r24,GDcollgn(r31) /* Get the size of columns in bytes */
1719 add r25,r28,r25 /* Physical address of row */
1720 mullw r3,r3,r24 /* Get byte offset to first output column */
1721
1722 li r9,32 /* Get the initial shift calc */
1723
1724 lis r20,HIGH_ADDR(hexfont) /* Point to the font */
1725
1726 li r18,GDfontsize /* Get the number of rows in the font */
1727 ori r20,r20,LOW_ADDR(hexfont) /* Point to the low part */
1728 add r21,r25,r3 /* Physical address of top left output pixel */
1729 sub r9,r9,r26 /* Get right shift justifier for pixel size */
1730 li r7,32 /* Number of bits per word */
1731
1732 startNybble:
1733 la r6,GDrowbuf1(r31) /* Point to the row buffer */
1734 li r19,8 /* Get the number of characters in a row */
1735
1736 getNybble: rlwinm r10,r4,9,23,26 /* Get the top nybble * 32 */
1737 rlwinm r4,r4,4,0,31 /* Rotate a nybble */
1738 add r10,r20,r10 /* Point to the character in the font */
1739
1740 rlwinm r16,r26,4,0,27 /* Width of row in actual bits */
1741 lhz r15,0(r10) /* Get the next row of the font */
1742
1743 rendrow: rlwinm r17,r15,16,0,0 /* Get the next font pixel in the row */
1744 rlwinm r15,r15,1,16,31 /* Move in the next font pixel */
1745 srawi r17,r17,31 /* Fill with 1s if black and 0s if white (reversed) */
1746
1747 slw r14,r14,r26 /* Make room for our pixel in a register */
1748 srw r17,r17,r9 /* Isolate one pixels worth of black or white */
1749 sub. r7,r7,r26 /* See how may bits are left */
1750 sub r16,r16,r26 /* Count how many bits are left to store for this row */
1751 or r14,r14,r17 /* Put in the pixel */
1752 bne+ notfull /* Finish rendering this word */
1753
1754 not r14,r14 /* Invert to black on white */
1755 stw r14,0(r6) /* Write out the word */
1756 li r7,32 /* Bit per word count */
1757 addi r6,r6,4 /* Point to the next word */
1758
1759 notfull: mr. r16,r16 /* Have we finished the whole character row? */
1760 bne+ rendrow /* Finish rendering the row */
1761
1762 addic. r19,r19,-1 /* Are we finished with a whole display row yet? */
1763 bne+ getNybble /* Not yet... */
1764
1765 la r6,GDrowbuf1(r31) /* Point to the row buffer */
1766 rlwinm r19,r26,31,0,29 /* Number of cache lines (depth/2) */
1767 mr r14,r21 /* Get the frame buffer address */
1768
1769 // BREAKPOINT_TRAP
1770
1771 blitrow: lfd f0,0(r6) /* Load a line */
1772 lfd f1,8(r6)
1773 lfd f2,16(r6)
1774 lfd f3,24(r6)
1775
1776 stfd f0,0(r14) /* Blit a line */
1777 stfd f1,8(r14)
1778 stfd f2,16(r14)
1779 stfd f3,24(r14)
1780
1781 addi r6,r6,32 /* Next buffered line */
1782
1783 dcbst 0,r14 /* Force the line to the screen */
1784 sync /* Make sure the line is on it's way */
1785 eieio /* Make sure we beat the invalidate */
1786 dcbi 0,r14 /* Make sure we leave no paradox */
1787
1788 addic. r19,r19,-1 /* Done all lines yet? */
1789 addi r14,r14,32 /* Point to the next output */
1790 bne+ blitrow /* Nope, do it some more... */
1791
1792 addic. r18,r18,-1 /* Have we done all the rows in character yet? */
1793 addi r20,r20,2 /* Offset the font to the next row */
1794 add r21,r21,r27 /* Point to start of next row */
1795 bne+ startNybble /* Nope, go through the word one more time... */
1796
1797 GDbailout: mr r1,r31 /* Move the workarea base */
1798
1799 lfd f0,GDfp0(r31) /* Restore FP */
1800 lfd f1,GDfp1(r31) /* Restore FP */
1801 lfd f2,GDfp2(r31) /* Restore FP */
1802 lfd f3,GDfp3(r31) /* Restore FP */
1803
1804 mtmsr r5 /* Disable floating point */
1805 isync
1806
1807 lmw r3,GDsave+12(r1) /* Restore most registers */
1808 lwz r0,GDsave(r1) /* Restore R0 */
1809 lwz r1,GDsave+4(r1) /* Finally, R1 */
1810 blr /* Leave... */
1811
1812
1813 /*
1814 * void GratefulDebDisp(unsigned int coord, unsigned int data);
1815 */
1816
1817
1818 ENTRY(GratefulDebDisp,TAG_NO_FRAME_USED)
1819
1820 mfmsr r9 /* Save the current MSR */
1821 mflr r7 /* Save the return */
1822 andi. r8,r9,0x7FCF /* Clear interrupt and translation */
1823 mtmsr r8 /* Turn 'em really off */
1824 isync /* Make sure about the translation part */
1825 bl EXT(GratefulDeb) /* Display it */
1826 mtmsr r9 /* Restore interrupt and translation */
1827 mtlr r7 /* Restore return */
1828 isync /* Make sure */
1829 blr
1830
1831
1832 #endif
1833
1834 /*
1835 * void checkNMI(void);
1836 */
1837
1838
1839 ENTRY(checkNMI,TAG_NO_FRAME_USED)
1840
1841 mfmsr r9 /* Save it */
1842 andi. r8,r9,0x7FCF /* Clear it */
1843 mtmsr r8 /* Disable it */
1844 isync /* Fence it */
1845 lis r7,0xF300 /* Find it */
1846 ori r7,r7,0x0020 /* Find it */
1847 dcbi 0,r7 /* Toss it */
1848 sync /* Sync it */
1849 eieio /* Get it */
1850 lwz r6,0x000C(r7) /* Check it */
1851 eieio /* Fence it */
1852 dcbi 0,r7 /* Toss it */
1853 rlwinm. r4,r6,0,19,19 /* Check it */
1854 rlwinm r6,r6,0,20,18 /* Clear it */
1855 sync /* Sync it */
1856 eieio /* Fence it */
1857 beq+ xnonmi /* Branch on it */
1858
1859 stw r6,0x0008(r7) /* Reset it */
1860 sync /* Sync it */
1861 dcbi 0,r6 /* Toss it */
1862 eieio /* Fence it */
1863
1864 mtmsr r9 /* Restore it */
1865 isync /* Hold it */
1866
1867 BREAKPOINT_TRAP /* Kill it */
1868 blr /* Return from it */
1869
1870 xnonmi: /* Label it */
1871 mtmsr r9 /* Restore it */
1872 isync /* Hold it */
1873 blr /* Return from it */
1874
1875
1876 /*
1877 * Early debug code
1878 */
1879
1880 dumpr7: lis r9,HIGH_ADDR(hexTab) /* (TEST/DEBUG) */
1881 li r5,8 /* (TEST/DEBUG) */
1882 ori r9,r9,LOW_ADDR(hexTab) /* (TEST/DEBUG) */
1883
1884 dumpr7n: rlwinm r7,r7,4,0,31 /* (TEST/DEBUG) */
1885 mr r6,r7 /* (TEST/DEBUG) */
1886 andi. r6,r6,15 /* (TEST/DEBUG) */
1887 lbzx r6,r9,r6 /* (TEST/DEBUG) */
1888 lis r10,0xF301 /* (TEST/DEBUG) */
1889 ori r10,r10,0x2000 /* (TEST/DEBUG) */
1890
1891 #if 0
1892 xqrw2: eieio /* (TEST/DEBUG) */
1893 lbz r7,0(r10) /* (TEST/DEBUG) */
1894 dcbi 0,r10 /* (TEST/DEBUG) */
1895 sync /* (TEST/DEBUG) */
1896 andi. r7,r7,0x04 /* (TEST/DEBUG) */
1897 beq xqrw2 /* (TEST/DEBUG) */
1898 #endif
1899
1900 dcbf 0,r10 /* (TEST/DEBUG) */
1901 sync /* (TEST/DEBUG) */
1902 dcbi 0,r10 /* (TEST/DEBUG) */
1903 eieio /* (TEST/DEBUG) */
1904 stb r6,4(r10) /* (TEST/DEBUG) */
1905
1906 lis r6,10 /* (TEST/DEBUG) */
1907 dumpr7d: addi r6,r6,-1 /* (TEST/DEBUG) */
1908 mr. r6,r6 /* (TEST/DEBUG) */
1909 bne- dumpr7d /* (TEST/DEBUG) */
1910 dcbf 0,r10 /* (TEST/DEBUG) */
1911 sync /* (TEST/DEBUG) */
1912 dcbi 0,r10 /* (TEST/DEBUG) */
1913 eieio /* (TEST/DEBUG) */
1914
1915 addic. r5,r5,-1 /* (TEST/DEBUG) */
1916 bne+ dumpr7n /* (TEST/DEBUG) */
1917
1918 blr /* (TEST/DEBUG) */
1919
1920 ;
1921 ; Log a special entry in physical memory.
1922 ; This assumes that memory size has been significantly lowered using
1923 ; the maxmem boot option. The buffer starts just after the end of mem_size.
1924 ;
1925 ; This is absolutely for special tracing cases. Do not ever leave in...
1926 ;
1927
1928 ENTRY(dbgLog,TAG_NO_FRAME_USED)
1929
1930 li r11,0 ; Clear callers callers callers return
1931 li r10,0 ; Clear callers callers callers callers return
1932 li r9,0 ; Clear callers callers callers callers callers return
1933 lwz r2,0(r1) ; Get callers callers stack frame
1934 lis r0,0x4000 ; First invalid address
1935 lwz r12,8(r2) ; Get our callers return
1936 lwz r2,0(r2) ; Back chain
1937
1938 mr. r2,r2 ; End of chain?
1939 cmplw cr1,r2,r0 ; Valid kernel address?
1940 beq- nosavehere ; Yes, end of chain...
1941 bge- cr1,nosavehere ; No...
1942 lwz r11,8(r2) ; Get our callers return
1943 lwz r2,0(r2) ; Back chain
1944
1945 mr. r2,r2 ; End of chain?
1946 cmplw cr1,r2,r0 ; Valid kernel address?
1947 beq- nosavehere ; Yes, end of chain...
1948 bge- cr1,nosavehere ; No...
1949 lwz r10,8(r2) ; Get our callers return
1950 lwz r2,0(r2) ; Back chain
1951
1952 mr. r2,r2 ; End of chain?
1953 cmplw cr1,r2,r0 ; Valid kernel address?
1954 beq- nosavehere ; Yes, end of chain...
1955 bge- cr1,nosavehere ; No...
1956 lwz r9,8(r2) ; Get our callers return
1957
1958 nosavehere: mfmsr r8 ; Get the MSR
1959 lis r2,hi16(EXT(DebugWork)) ; High part of area
1960 lis r7,hi16(EXT(mem_actual)) ; High part of actual
1961 andi. r0,r8,0x7FCF ; Interrupts and translation off
1962 ori r2,r2,lo16(EXT(DebugWork)) ; Get the entry
1963 mtmsr r0 ; Turn stuff off
1964 ori r7,r7,lo16(EXT(mem_actual)) ; Get the actual
1965 isync
1966
1967 lwz r0,4(r2) ; Get the flag
1968 mr. r0,r0 ; Should we log?
1969 lwz r0,0(r7) ; Get the end of memory
1970 lwz r7,0(r2) ; Get the position
1971 bne- waytoofar ; No logging...
1972 mr. r7,r7 ; Is this the first?
1973 bne+ gotspot ; Nope...
1974
1975 lis r7,hi16(EXT(mem_size)) ; High part of defined memory
1976 ori r7,r7,lo16(EXT(mem_size)) ; Low part of defined memory
1977 lwz r7,0(r7) ; Make it end of defined
1978
1979 gotspot: cmplw r7,r0 ; Do we fit in memory
1980 addi r0,r7,0x0020 ; Next slot
1981 bge- waytoofar ; No fit...
1982
1983 stw r0,0(r2) ; Set next time slot
1984 dcbz 0,r7 ; Zap it
1985
1986 stw r3,0(r7) ; First data
1987 li r3,32 ; Disp to next line
1988 stw r4,4(r7) ; Second data
1989 dcbz r3,r7 ; Zap it
1990 stw r5,8(r7) ; Third data
1991 stw r6,12(r7) ; Fourth data
1992
1993 stw r12,16(r7) ; Callers callers
1994 stw r11,20(r7) ; Callers callers caller
1995 stw r10,24(r7) ; Callers callers callers caller
1996 stw r9,28(r7) ; Callers callers callers callers caller
1997
1998 waytoofar: mtmsr r8 ; Back to normal
1999 isync
2000 blr
2001
2002 ;
2003 ; Same as the other, but no traceback and 16 byte entry
2004 ; Trashes R0, R2, R10, R12
2005 ;
2006
2007 .align 5
2008 .globl EXT(dbgLog2)
2009
2010 LEXT(dbgLog2)
2011
2012
2013 mfmsr r10 ; Get the MSR
2014 lis r2,hi16(EXT(DebugWork)) ; High part of area
2015 lis r12,hi16(EXT(mem_actual)) ; High part of actual
2016 andi. r0,r10,0x7FCF ; Interrupts and translation off
2017 ori r2,r2,lo16(EXT(DebugWork)) ; Get the entry
2018 mtmsr r0 ; Turn stuff off
2019 ori r12,r12,lo16(EXT(mem_actual)) ; Get the actual
2020 isync
2021
2022 lwz r0,4(r2) ; Get the flag
2023 mr. r0,r0 ; Should we log?
2024 lwz r0,0(r12) ; Get the end of memory
2025 lwz r12,0(r2) ; Get the position
2026 bne- waytoofar2 ; No logging...
2027 mr. r12,r12 ; Is this the first?
2028 bne+ gotspot2 ; Nope...
2029
2030 lis r12,hi16(EXT(mem_size)) ; High part of defined memory
2031 ori r12,r12,lo16(EXT(mem_size)) ; Low part of defined memory
2032 lwz r12,0(r12) ; Make it end of defined
2033
2034 gotspot2: cmplw cr1,r12,r0 ; Do we fit in memory
2035 rlwinm. r0,r12,0,27,27 ; Are we on a new line?
2036 bge- cr1,waytoofar2 ; No fit...
2037 addi r0,r12,0x0010 ; Next slot
2038
2039 bne+ nonewline ; Not on a new line...
2040 dcbz br0,r12 ; Clear it so we do not fetch it
2041
2042 nonewline: cmplwi r3,68 ; Special place for time stamp?
2043
2044 stw r0,0(r2) ; Set next time slot
2045 bne+ nospcts ; Nope...
2046
2047 lwz r0,0x17C(br0) ; Get special saved time stamp
2048 b nospctt ; Skip...
2049
2050 nospcts: mftb r0 ; Get the current time
2051
2052 nospctt: stw r3,4(r12) ; First data
2053 stw r4,8(r12) ; Second data
2054 stw r5,12(r12) ; Third data
2055 stw r0,0(r12) ; Time stamp
2056
2057 waytoofar2: mtmsr r10 ; Back to normal
2058 isync
2059 blr
2060
2061
2062 ;
2063 ; Saves floating point registers
2064 ;
2065
2066 .align 5
2067 .globl EXT(stFloat)
2068
2069 LEXT(stFloat)
2070
2071 mfmsr r0 ; Save the MSR
2072 rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
2073 ori r4,r4,lo16(MASK(MSR_FP)) ; Enable floating point
2074 mtmsr r4
2075 isync
2076
2077 stfd f0,0x00(r3)
2078 stfd f1,0x08(r3)
2079 stfd f2,0x10(r3)
2080 stfd f3,0x18(r3)
2081 stfd f4,0x20(r3)
2082 stfd f5,0x28(r3)
2083 stfd f6,0x30(r3)
2084 stfd f7,0x38(r3)
2085 stfd f8,0x40(r3)
2086 stfd f9,0x48(r3)
2087 stfd f10,0x50(r3)
2088 stfd f11,0x58(r3)
2089 stfd f12,0x60(r3)
2090 stfd f13,0x68(r3)
2091 stfd f14,0x70(r3)
2092 stfd f15,0x78(r3)
2093 stfd f16,0x80(r3)
2094 stfd f17,0x88(r3)
2095 stfd f18,0x90(r3)
2096 stfd f19,0x98(r3)
2097 stfd f20,0xA0(r3)
2098 stfd f21,0xA8(r3)
2099 stfd f22,0xB0(r3)
2100 stfd f23,0xB8(r3)
2101 stfd f24,0xC0(r3)
2102 stfd f25,0xC8(r3)
2103 stfd f26,0xD0(r3)
2104 stfd f27,0xD8(r3)
2105 stfd f28,0xE0(r3)
2106 stfd f29,0xE8(r3)
2107 stfd f30,0xF0(r3)
2108 stfd f31,0xF8(r3)
2109 mffs f0
2110 stfd f0,0x100(r3)
2111 lfd f0,0x00(r3)
2112 mtmsr r0
2113 isync
2114 blr
2115
2116
2117 ;
2118 ; Saves vector registers. Returns 0 if non-Altivec machine.
2119 ;
2120
2121 .align 5
2122 .globl EXT(stVectors)
2123
2124 LEXT(stVectors)
2125 #if 0
2126
2127 mfpvr r6 ; Get machine type
2128 mr r5,r3 ; Save area address
2129 rlwinm r6,r6,16,17,31 ; Rotate on it
2130 li r3,0 ; Assume failure
2131 cmplwi r6,PROCESSOR_VERSION_7400 ; Do we have Altivec?
2132 bltlr+ ; No...
2133
2134 mfmsr r0 ; Save the MSR
2135 rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
2136 oris r4,r4,hi16(MASK(MSR_VEC)) ; Enable vectors
2137 mtmsr r4
2138 isync
2139
2140 stvxl v0,0,r5
2141 addi r5,r5,16
2142 stvxl v1,0,r5
2143 addi r5,r5,16
2144 stvxl v2,0,r5
2145 addi r5,r5,16
2146 stvxl v3,0,r5
2147 addi r5,r5,16
2148 stvxl v4,0,r5
2149 addi r5,r5,16
2150 stvxl v5,0,r5
2151 addi r5,r5,16
2152 stvxl v6,0,r5
2153 addi r5,r5,16
2154 stvxl v7,0,r5
2155 addi r5,r5,16
2156 stvxl v8,0,r5
2157 addi r5,r5,16
2158 stvxl v9,0,r5
2159 addi r5,r5,16
2160 stvxl v10,0,r5
2161 addi r5,r5,16
2162 stvxl v11,0,r5
2163 addi r5,r5,16
2164 stvxl v12,0,r5
2165 addi r5,r5,16
2166 stvxl v13,0,r5
2167 addi r5,r5,16
2168 stvxl v14,0,r5
2169 addi r5,r5,16
2170 stvxl v15,0,r5
2171 addi r5,r5,16
2172 stvxl v16,0,r5
2173 addi r5,r5,16
2174 stvxl v17,0,r5
2175 addi r5,r5,16
2176 stvxl v18,0,r5
2177 addi r5,r5,16
2178 stvxl v19,0,r5
2179 addi r5,r5,16
2180 stvxl v20,0,r5
2181 addi r5,r5,16
2182 stvxl v21,0,r5
2183 addi r5,r5,16
2184 stvxl v22,0,r5
2185 addi r5,r5,16
2186 stvxl v23,0,r5
2187 addi r5,r5,16
2188 stvxl v24,0,r5
2189 addi r5,r5,16
2190 stvxl v25,0,r5
2191 addi r5,r5,16
2192 stvxl v26,0,r5
2193 addi r5,r5,16
2194 stvxl v27,0,r5
2195 addi r5,r5,16
2196 stvxl v28,0,r5
2197 addi r5,r5,16
2198 stvxl v29,0,r5
2199 addi r5,r5,16
2200 stvxl v30,0,r5
2201 addi r5,r5,16
2202 stvxl v31,0,r5
2203 mfvscr v31
2204 addi r6,r5,16
2205 stvxl v31,0,r6
2206 li r3,1
2207 lvxl v31,0,r5
2208 mtmsr r0
2209 isync
2210
2211 #endif
2212 blr
2213
2214
2215 ;
2216 ; Saves yet more registers
2217 ;
2218
2219 .align 5
2220 .globl EXT(stSpecrs)
2221
2222 LEXT(stSpecrs)
2223 #if 0
2224
2225 mfmsr r0 ; Save the MSR
2226 rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
2227 mtmsr r4
2228 isync
2229
2230 mfpvr r12
2231 stw r12,4(r3)
2232 rlwinm r12,r12,16,16,31
2233
2234 mfdbatu r4,0
2235 mfdbatl r5,0
2236 mfdbatu r6,1
2237 mfdbatl r7,1
2238 mfdbatu r8,2
2239 mfdbatl r9,2
2240 mfdbatu r10,3
2241 mfdbatl r11,3
2242 stw r4,8(r3)
2243 stw r5,12(r3)
2244 stw r6,16(r3)
2245 stw r7,20(r3)
2246 stw r8,24(r3)
2247 stw r9,28(r3)
2248 stw r10,32(r3)
2249 stw r11,36(r3)
2250
2251 mfibatu r4,0
2252 mfibatl r5,0
2253 mfibatu r6,1
2254 mfibatl r7,1
2255 mfibatu r8,2
2256 mfibatl r9,2
2257 mfibatu r10,3
2258 mfibatl r11,3
2259 stw r4,40(r3)
2260 stw r5,44(r3)
2261 stw r6,48(r3)
2262 stw r7,52(r3)
2263 stw r8,56(r3)
2264 stw r9,60(r3)
2265 stw r10,64(r3)
2266 stw r11,68(r3)
2267
2268 mfsprg r4,0
2269 mfsprg r5,1
2270 mfsprg r6,2
2271 mfsprg r7,3
2272 stw r4,72(r3)
2273 stw r5,76(r3)
2274 stw r6,80(r3)
2275 stw r7,84(r3)
2276
2277 mfsdr1 r4
2278 stw r4,88(r3)
2279
2280 la r4,92(r3)
2281 li r5,0
2282
2283 stSnsr: mfsrin r6,r5
2284 addis r5,r5,0x1000
2285 stw r6,0(r4)
2286 mr. r5,r5
2287 addi r4,r4,4
2288 bne+ stSnsr
2289
2290 cmplwi cr1,r12,PROCESSOR_VERSION_604e
2291 cmplwi cr5,r12,PROCESSOR_VERSION_604ev
2292 cror cr1_eq,cr1_eq,cr5_eq ; Set if 604 type
2293 cmplwi r12,PROCESSOR_VERSION_750
2294 mfspr r4,hid0
2295 stw r4,(39*4)(r3)
2296
2297 li r4,0
2298 li r5,0
2299 li r6,0
2300 li r7,0
2301 beq- cr1,before750
2302 blt- before750
2303
2304 mfspr r4,hid1
2305 mfspr r5,l2cr
2306 mfspr r6,msscr0
2307 mfspr r7,msscr1
2308
2309 before750: stw r4,(40*4)(r3)
2310 stw r6,(42*4)(r3)
2311 stw r5,(41*4)(r3)
2312 stw r7,(43*4)(r3)
2313
2314 li r4,0
2315 beq isis750
2316
2317 mfspr r4,pir
2318 isis750: stw r4,0(r3)
2319
2320 li r4,0
2321 li r5,0
2322 li r6,0
2323 li r7,0
2324 beq- cr1,b4750
2325 blt- b4750
2326
2327 mfspr r4,thrm1
2328 mfspr r5,thrm2
2329 mfspr r6,thrm3
2330 mfspr r7,ictc
2331
2332 b4750: stw r4,(44*4)(r3)
2333 stw r5,(45*4)(r3)
2334 stw r6,(46*4)(r3)
2335 stw r7,(47*4)(r3)
2336
2337 li r4,0
2338 cmplwi r12,PROCESSOR_VERSION_7400
2339 bne nnmax
2340
2341 mfpvr r5
2342 rlwinm r5,r5,0,16,31
2343 cmplwi r5,0x1101
2344 beq gnmax
2345 cmplwi r5,0x1102
2346 bne nnmax
2347
2348 gnmax: mfspr r4,1016
2349
2350 nnmax: stw r4,(48*4)(r3)
2351
2352 mtmsr r0
2353 isync
2354
2355 #endif
2356 blr
mirror of XNU