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1 /*
2 * Copyright (c) 2000-2018 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 /*
32 * Mach Operating System
33 * Copyright (c) 1991,1990,1989,1988 Carnegie Mellon University
34 * All Rights Reserved.
35 *
36 * Permission to use, copy, modify and distribute this software and its
37 * documentation is hereby granted, provided that both the copyright
38 * notice and this permission notice appear in all copies of the
39 * software, derivative works or modified versions, and any portions
40 * thereof, and that both notices appear in supporting documentation.
41 *
42 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
43 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
44 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
45 *
46 * Carnegie Mellon requests users of this software to return to
47 *
48 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
49 * School of Computer Science
50 * Carnegie Mellon University
51 * Pittsburgh PA 15213-3890
52 *
53 * any improvements or extensions that they make and grant Carnegie Mellon
54 * the rights to redistribute these changes.
55 */
56 /*
57 */
58
59 /*
60 * Hardware trap/fault handler.
61 */
62
63 #include <mach_kdp.h>
64 #include <mach_ldebug.h>
65
66 #include <types.h>
67 #include <i386/eflags.h>
68 #include <i386/trap.h>
69 #include <i386/pmap.h>
70 #include <i386/fpu.h>
71 #include <i386/misc_protos.h> /* panic_io_port_read() */
72 #include <i386/lapic.h>
73
74 #include <mach/exception.h>
75 #include <mach/kern_return.h>
76 #include <mach/vm_param.h>
77 #include <mach/i386/thread_status.h>
78
79 #include <vm/vm_kern.h>
80 #include <vm/vm_fault.h>
81
82 #include <kern/kern_types.h>
83 #include <kern/processor.h>
84 #include <kern/thread.h>
85 #include <kern/task.h>
86 #include <kern/sched.h>
87 #include <kern/sched_prim.h>
88 #include <kern/exception.h>
89 #include <kern/spl.h>
90 #include <kern/misc_protos.h>
91 #include <kern/debug.h>
92 #if CONFIG_TELEMETRY
93 #include <kern/telemetry.h>
94 #endif
95 #include <sys/kdebug.h>
96 #include <kperf/kperf.h>
97 #include <prng/random.h>
98
99 #include <string.h>
100
101 #include <i386/postcode.h>
102 #include <i386/mp_desc.h>
103 #include <i386/proc_reg.h>
104 #if CONFIG_MCA
105 #include <i386/machine_check.h>
106 #endif
107 #include <mach/i386/syscall_sw.h>
108
109 #include <libkern/OSDebug.h>
110 #include <i386/cpu_threads.h>
111 #include <machine/pal_routines.h>
112
113 extern void throttle_lowpri_io(int);
114 extern void kprint_state(x86_saved_state64_t *saved_state);
115
116 /*
117 * Forward declarations
118 */
119 static void user_page_fault_continue(kern_return_t kret);
120 static void panic_trap(x86_saved_state64_t *saved_state, uint32_t pl, kern_return_t fault_result);
121 static void set_recovery_ip(x86_saved_state64_t *saved_state, vm_offset_t ip);
122
123 #if CONFIG_DTRACE
124 /* See <rdar://problem/4613924> */
125 perfCallback tempDTraceTrapHook = NULL; /* Pointer to DTrace fbt trap hook routine */
126
127 extern boolean_t dtrace_tally_fault(user_addr_t);
128 #endif
129
130 extern boolean_t pmap_smep_enabled;
131 extern boolean_t pmap_smap_enabled;
132
133 __attribute__((noreturn))
134 void
135 thread_syscall_return(
136 kern_return_t ret)
137 {
138 thread_t thr_act = current_thread();
139 boolean_t is_mach;
140 int code;
141
142 pal_register_cache_state(thr_act, DIRTY);
143
144 if (thread_is_64bit_addr(thr_act)) {
145 x86_saved_state64_t *regs;
146
147 regs = USER_REGS64(thr_act);
148
149 code = (int) (regs->rax & SYSCALL_NUMBER_MASK);
150 is_mach = (regs->rax & SYSCALL_CLASS_MASK)
151 == (SYSCALL_CLASS_MACH << SYSCALL_CLASS_SHIFT);
152 if (kdebug_enable && is_mach) {
153 /* Mach trap */
154 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
155 MACHDBG_CODE(DBG_MACH_EXCP_SC, code) | DBG_FUNC_END,
156 ret, 0, 0, 0, 0);
157 }
158 regs->rax = ret;
159 #if DEBUG
160 if (is_mach) {
161 DEBUG_KPRINT_SYSCALL_MACH(
162 "thread_syscall_return: 64-bit mach ret=%u\n",
163 ret);
164 } else {
165 DEBUG_KPRINT_SYSCALL_UNIX(
166 "thread_syscall_return: 64-bit unix ret=%u\n",
167 ret);
168 }
169 #endif
170 } else {
171 x86_saved_state32_t *regs;
172
173 regs = USER_REGS32(thr_act);
174
175 code = ((int) regs->eax);
176 is_mach = (code < 0);
177 if (kdebug_enable && is_mach) {
178 /* Mach trap */
179 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
180 MACHDBG_CODE(DBG_MACH_EXCP_SC, -code) | DBG_FUNC_END,
181 ret, 0, 0, 0, 0);
182 }
183 regs->eax = ret;
184 #if DEBUG
185 if (is_mach) {
186 DEBUG_KPRINT_SYSCALL_MACH(
187 "thread_syscall_return: 32-bit mach ret=%u\n",
188 ret);
189 } else {
190 DEBUG_KPRINT_SYSCALL_UNIX(
191 "thread_syscall_return: 32-bit unix ret=%u\n",
192 ret);
193 }
194 #endif
195 }
196
197 #if DEBUG || DEVELOPMENT
198 kern_allocation_name_t
199 prior __assert_only = thread_get_kernel_state(thr_act)->allocation_name;
200 assertf(prior == NULL, "thread_set_allocation_name(\"%s\") not cleared", kern_allocation_get_name(prior));
201 #endif /* DEBUG || DEVELOPMENT */
202
203 throttle_lowpri_io(1);
204
205 thread_exception_return();
206 /*NOTREACHED*/
207 }
208
209
210 static inline void
211 user_page_fault_continue(
212 kern_return_t kr)
213 {
214 thread_t thread = current_thread();
215 user_addr_t vaddr;
216
217 if (thread_is_64bit_addr(thread)) {
218 x86_saved_state64_t *uregs;
219
220 uregs = USER_REGS64(thread);
221
222 vaddr = (user_addr_t)uregs->cr2;
223 } else {
224 x86_saved_state32_t *uregs;
225
226 uregs = USER_REGS32(thread);
227
228 vaddr = uregs->cr2;
229 }
230
231
232 /* PAL debug hook */
233 pal_dbg_page_fault( thread, vaddr, kr );
234
235 i386_exception(EXC_BAD_ACCESS, kr, vaddr);
236 /*NOTREACHED*/
237 }
238
239 /*
240 * Fault recovery in copyin/copyout routines.
241 */
242 struct recovery {
243 uintptr_t fault_addr;
244 uintptr_t recover_addr;
245 };
246
247 extern struct recovery recover_table[];
248 extern struct recovery recover_table_end[];
249
250 const char * trap_type[] = {TRAP_NAMES};
251 unsigned TRAP_TYPES = sizeof(trap_type) / sizeof(trap_type[0]);
252
253 extern void PE_incoming_interrupt(int interrupt);
254
255 #if defined(__x86_64__) && DEBUG
256 void
257 kprint_state(x86_saved_state64_t *saved_state)
258 {
259 kprintf("current_cpu_datap() 0x%lx\n", (uintptr_t)current_cpu_datap());
260 kprintf("Current GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_GS_BASE));
261 kprintf("Kernel GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_KERNEL_GS_BASE));
262 kprintf("state at 0x%lx:\n", (uintptr_t) saved_state);
263
264 kprintf(" rdi 0x%llx\n", saved_state->rdi);
265 kprintf(" rsi 0x%llx\n", saved_state->rsi);
266 kprintf(" rdx 0x%llx\n", saved_state->rdx);
267 kprintf(" r10 0x%llx\n", saved_state->r10);
268 kprintf(" r8 0x%llx\n", saved_state->r8);
269 kprintf(" r9 0x%llx\n", saved_state->r9);
270
271 kprintf(" cr2 0x%llx\n", saved_state->cr2);
272 kprintf("real cr2 0x%lx\n", get_cr2());
273 kprintf(" r15 0x%llx\n", saved_state->r15);
274 kprintf(" r14 0x%llx\n", saved_state->r14);
275 kprintf(" r13 0x%llx\n", saved_state->r13);
276 kprintf(" r12 0x%llx\n", saved_state->r12);
277 kprintf(" r11 0x%llx\n", saved_state->r11);
278 kprintf(" rbp 0x%llx\n", saved_state->rbp);
279 kprintf(" rbx 0x%llx\n", saved_state->rbx);
280 kprintf(" rcx 0x%llx\n", saved_state->rcx);
281 kprintf(" rax 0x%llx\n", saved_state->rax);
282
283 kprintf(" gs 0x%x\n", saved_state->gs);
284 kprintf(" fs 0x%x\n", saved_state->fs);
285
286 kprintf(" isf.trapno 0x%x\n", saved_state->isf.trapno);
287 kprintf(" isf._pad 0x%x\n", saved_state->isf._pad);
288 kprintf(" isf.trapfn 0x%llx\n", saved_state->isf.trapfn);
289 kprintf(" isf.err 0x%llx\n", saved_state->isf.err);
290 kprintf(" isf.rip 0x%llx\n", saved_state->isf.rip);
291 kprintf(" isf.cs 0x%llx\n", saved_state->isf.cs);
292 kprintf(" isf.rflags 0x%llx\n", saved_state->isf.rflags);
293 kprintf(" isf.rsp 0x%llx\n", saved_state->isf.rsp);
294 kprintf(" isf.ss 0x%llx\n", saved_state->isf.ss);
295 }
296 #endif
297
298
299 /*
300 * Non-zero indicates latency assert is enabled and capped at valued
301 * absolute time units.
302 */
303
304 uint64_t interrupt_latency_cap = 0;
305 boolean_t ilat_assert = FALSE;
306
307 void
308 interrupt_latency_tracker_setup(void)
309 {
310 uint32_t ilat_cap_us;
311 if (PE_parse_boot_argn("interrupt_latency_cap_us", &ilat_cap_us, sizeof(ilat_cap_us))) {
312 interrupt_latency_cap = ilat_cap_us * NSEC_PER_USEC;
313 nanoseconds_to_absolutetime(interrupt_latency_cap, &interrupt_latency_cap);
314 } else {
315 interrupt_latency_cap = LockTimeOut;
316 }
317 PE_parse_boot_argn("-interrupt_latency_assert_enable", &ilat_assert, sizeof(ilat_assert));
318 }
319
320 void
321 interrupt_reset_latency_stats(void)
322 {
323 uint32_t i;
324 for (i = 0; i < real_ncpus; i++) {
325 cpu_data_ptr[i]->cpu_max_observed_int_latency =
326 cpu_data_ptr[i]->cpu_max_observed_int_latency_vector = 0;
327 }
328 }
329
330 void
331 interrupt_populate_latency_stats(char *buf, unsigned bufsize)
332 {
333 uint32_t i, tcpu = ~0;
334 uint64_t cur_max = 0;
335
336 for (i = 0; i < real_ncpus; i++) {
337 if (cur_max < cpu_data_ptr[i]->cpu_max_observed_int_latency) {
338 cur_max = cpu_data_ptr[i]->cpu_max_observed_int_latency;
339 tcpu = i;
340 }
341 }
342
343 if (tcpu < real_ncpus) {
344 snprintf(buf, bufsize, "0x%x 0x%x 0x%llx", tcpu, cpu_data_ptr[tcpu]->cpu_max_observed_int_latency_vector, cpu_data_ptr[tcpu]->cpu_max_observed_int_latency);
345 }
346 }
347
348 uint32_t interrupt_timer_coalescing_enabled = 1;
349 uint64_t interrupt_coalesced_timers;
350
351 /*
352 * Handle interrupts:
353 * - local APIC interrupts (IPIs, timers, etc) are handled by the kernel,
354 * - device interrupts go to the platform expert.
355 */
356 void
357 interrupt(x86_saved_state_t *state)
358 {
359 uint64_t rip;
360 uint64_t rsp;
361 int interrupt_num;
362 boolean_t user_mode = FALSE;
363 int ipl;
364 int cnum = cpu_number();
365 cpu_data_t *cdp = cpu_data_ptr[cnum];
366 int itype = DBG_INTR_TYPE_UNKNOWN;
367 int handled;
368
369 x86_saved_state64_t *state64 = saved_state64(state);
370 rip = state64->isf.rip;
371 rsp = state64->isf.rsp;
372 interrupt_num = state64->isf.trapno;
373 if (state64->isf.cs & 0x03) {
374 user_mode = TRUE;
375 }
376
377 if (cpu_data_ptr[cnum]->lcpu.package->num_idle == topoParms.nLThreadsPerPackage) {
378 cpu_data_ptr[cnum]->cpu_hwIntpexits[interrupt_num]++;
379 }
380
381 if (interrupt_num == (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_INTERPROCESSOR_INTERRUPT)) {
382 itype = DBG_INTR_TYPE_IPI;
383 } else if (interrupt_num == (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_TIMER_INTERRUPT)) {
384 itype = DBG_INTR_TYPE_TIMER;
385 } else {
386 itype = DBG_INTR_TYPE_OTHER;
387 }
388
389 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
390 MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_START,
391 interrupt_num,
392 (user_mode ? rip : VM_KERNEL_UNSLIDE(rip)),
393 user_mode, itype, 0);
394
395 SCHED_STATS_INTERRUPT(current_processor());
396
397 #if CONFIG_TELEMETRY
398 if (telemetry_needs_record) {
399 telemetry_mark_curthread(user_mode, FALSE);
400 }
401 #endif
402
403 ipl = get_preemption_level();
404
405 /*
406 * Handle local APIC interrupts
407 * else call platform expert for devices.
408 */
409 handled = lapic_interrupt(interrupt_num, state);
410
411 if (!handled) {
412 if (interrupt_num == (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_CMCI_INTERRUPT)) {
413 /*
414 * CMCI can be signalled on any logical processor, and the kexts
415 * that implement handling CMCI use IOKit to register handlers for
416 * the CMCI vector, so if we see a CMCI, do not encode a CPU
417 * number in bits 8:31 (since the vector is the same regardless of
418 * the handling CPU).
419 */
420 PE_incoming_interrupt(interrupt_num);
421 } else if (cnum <= lapic_max_interrupt_cpunum) {
422 PE_incoming_interrupt((cnum << 8) | interrupt_num);
423 }
424 }
425
426 if (__improbable(get_preemption_level() != ipl)) {
427 panic("Preemption level altered by interrupt vector 0x%x: initial 0x%x, final: 0x%x\n", interrupt_num, ipl, get_preemption_level());
428 }
429
430
431 if (__improbable(cdp->cpu_nested_istack)) {
432 cdp->cpu_nested_istack_events++;
433 } else {
434 uint64_t ctime = mach_absolute_time();
435 uint64_t int_latency = ctime - cdp->cpu_int_event_time;
436 uint64_t esdeadline, ehdeadline;
437 /* Attempt to process deferred timers in the context of
438 * this interrupt, unless interrupt time has already exceeded
439 * TCOAL_ILAT_THRESHOLD.
440 */
441 #define TCOAL_ILAT_THRESHOLD (30000ULL)
442
443 if ((int_latency < TCOAL_ILAT_THRESHOLD) &&
444 interrupt_timer_coalescing_enabled) {
445 esdeadline = cdp->rtclock_timer.queue.earliest_soft_deadline;
446 ehdeadline = cdp->rtclock_timer.deadline;
447 if ((ctime >= esdeadline) && (ctime < ehdeadline)) {
448 interrupt_coalesced_timers++;
449 TCOAL_DEBUG(0x88880000 | DBG_FUNC_START, ctime, esdeadline, ehdeadline, interrupt_coalesced_timers, 0);
450 rtclock_intr(state);
451 TCOAL_DEBUG(0x88880000 | DBG_FUNC_END, ctime, esdeadline, interrupt_coalesced_timers, 0, 0);
452 } else {
453 TCOAL_DEBUG(0x77770000, ctime, cdp->rtclock_timer.queue.earliest_soft_deadline, cdp->rtclock_timer.deadline, interrupt_coalesced_timers, 0);
454 }
455 }
456
457 if (__improbable(ilat_assert && (int_latency > interrupt_latency_cap) && !machine_timeout_suspended())) {
458 panic("Interrupt vector 0x%x exceeded interrupt latency threshold, 0x%llx absolute time delta, prior signals: 0x%x, current signals: 0x%x", interrupt_num, int_latency, cdp->cpu_prior_signals, cdp->cpu_signals);
459 }
460
461 if (__improbable(int_latency > cdp->cpu_max_observed_int_latency)) {
462 cdp->cpu_max_observed_int_latency = int_latency;
463 cdp->cpu_max_observed_int_latency_vector = interrupt_num;
464 }
465 }
466
467 /*
468 * Having serviced the interrupt first, look at the interrupted stack depth.
469 */
470 if (!user_mode) {
471 uint64_t depth = cdp->cpu_kernel_stack
472 + sizeof(struct thread_kernel_state)
473 + sizeof(struct i386_exception_link *)
474 - rsp;
475 if (__improbable(depth > kernel_stack_depth_max)) {
476 kernel_stack_depth_max = (vm_offset_t)depth;
477 KERNEL_DEBUG_CONSTANT(
478 MACHDBG_CODE(DBG_MACH_SCHED, MACH_STACK_DEPTH),
479 (long) depth, (long) VM_KERNEL_UNSLIDE(rip), 0, 0, 0);
480 }
481 }
482
483 if (cnum == master_cpu) {
484 ml_entropy_collect();
485 }
486
487 #if KPERF
488 kperf_interrupt();
489 #endif /* KPERF */
490
491 KDBG_RELEASE(MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_END,
492 interrupt_num);
493
494 assert(ml_get_interrupts_enabled() == FALSE);
495 }
496
497 static inline void
498 reset_dr7(void)
499 {
500 long dr7 = 0x400; /* magic dr7 reset value; 32 bit on i386, 64 bit on x86_64 */
501 __asm__ volatile ("mov %0,%%dr7" : : "r" (dr7));
502 }
503 #if MACH_KDP
504 unsigned kdp_has_active_watchpoints = 0;
505 #define NO_WATCHPOINTS (!kdp_has_active_watchpoints)
506 #else
507 #define NO_WATCHPOINTS 1
508 #endif
509 /*
510 * Trap from kernel mode. Only page-fault errors are recoverable,
511 * and then only in special circumstances. All other errors are
512 * fatal. Return value indicates if trap was handled.
513 */
514
515 void
516 kernel_trap(
517 x86_saved_state_t *state,
518 uintptr_t *lo_spp)
519 {
520 x86_saved_state64_t *saved_state;
521 int code;
522 user_addr_t vaddr;
523 int type;
524 vm_map_t map = 0; /* protected by T_PAGE_FAULT */
525 kern_return_t result = KERN_FAILURE;
526 kern_return_t fault_result = KERN_SUCCESS;
527 thread_t thread;
528 boolean_t intr;
529 vm_prot_t prot;
530 struct recovery *rp;
531 vm_offset_t kern_ip;
532 #if NCOPY_WINDOWS > 0
533 int fault_in_copy_window = -1;
534 #endif
535 int is_user;
536 int trap_pl = get_preemption_level();
537
538 thread = current_thread();
539
540 if (__improbable(is_saved_state32(state))) {
541 panic("kernel_trap(%p) with 32-bit state", state);
542 }
543 saved_state = saved_state64(state);
544
545 /* Record cpu where state was captured */
546 saved_state->isf.cpu = cpu_number();
547
548 vaddr = (user_addr_t)saved_state->cr2;
549 type = saved_state->isf.trapno;
550 code = (int)(saved_state->isf.err & 0xffff);
551 intr = (saved_state->isf.rflags & EFL_IF) != 0; /* state of ints at trap */
552 kern_ip = (vm_offset_t)saved_state->isf.rip;
553
554 is_user = (vaddr < VM_MAX_USER_PAGE_ADDRESS);
555
556 #if CONFIG_DTRACE
557 /*
558 * Is there a DTrace hook?
559 */
560 if (__improbable(tempDTraceTrapHook != NULL)) {
561 if (tempDTraceTrapHook(type, state, lo_spp, 0) == KERN_SUCCESS) {
562 /*
563 * If it succeeds, we are done...
564 */
565 return;
566 }
567 }
568 #endif /* CONFIG_DTRACE */
569
570 /*
571 * we come here with interrupts off as we don't want to recurse
572 * on preemption below. but we do want to re-enable interrupts
573 * as soon we possibly can to hold latency down
574 */
575 if (__improbable(T_PREEMPT == type)) {
576 ast_taken_kernel();
577
578 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
579 (MACHDBG_CODE(DBG_MACH_EXCP_KTRAP_x86, type)) | DBG_FUNC_NONE,
580 0, 0, 0, VM_KERNEL_UNSLIDE(kern_ip), 0);
581 return;
582 }
583
584 user_addr_t kd_vaddr = is_user ? vaddr : VM_KERNEL_UNSLIDE(vaddr);
585 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
586 (MACHDBG_CODE(DBG_MACH_EXCP_KTRAP_x86, type)) | DBG_FUNC_NONE,
587 (unsigned)(kd_vaddr >> 32), (unsigned)kd_vaddr, is_user,
588 VM_KERNEL_UNSLIDE(kern_ip), 0);
589
590
591 if (T_PAGE_FAULT == type) {
592 /*
593 * assume we're faulting in the kernel map
594 */
595 map = kernel_map;
596
597 if (__probable(thread != THREAD_NULL && thread->map != kernel_map)) {
598 #if NCOPY_WINDOWS > 0
599 vm_offset_t copy_window_base;
600 vm_offset_t kvaddr;
601 int window_index;
602
603 kvaddr = (vm_offset_t)vaddr;
604 /*
605 * must determine if fault occurred in
606 * the copy window while pre-emption is
607 * disabled for this processor so that
608 * we only need to look at the window
609 * associated with this processor
610 */
611 copy_window_base = current_cpu_datap()->cpu_copywindow_base;
612
613 if (kvaddr >= copy_window_base && kvaddr < (copy_window_base + (NBPDE * NCOPY_WINDOWS))) {
614 window_index = (int)((kvaddr - copy_window_base) / NBPDE);
615
616 if (thread->machine.copy_window[window_index].user_base != (user_addr_t)-1) {
617 kvaddr -= (copy_window_base + (NBPDE * window_index));
618 vaddr = thread->machine.copy_window[window_index].user_base + kvaddr;
619
620 map = thread->map;
621 fault_in_copy_window = window_index;
622 }
623 }
624 #else
625 if (__probable(vaddr < VM_MAX_USER_PAGE_ADDRESS)) {
626 /* fault occurred in userspace */
627 map = thread->map;
628
629 /* Intercept a potential Supervisor Mode Execute
630 * Protection fault. These criteria identify
631 * both NX faults and SMEP faults, but both
632 * are fatal. We avoid checking PTEs (racy).
633 * (The VM could just redrive a SMEP fault, hence
634 * the intercept).
635 */
636 if (__improbable((code == (T_PF_PROT | T_PF_EXECUTE)) &&
637 (pmap_smep_enabled) && (saved_state->isf.rip == vaddr))) {
638 goto debugger_entry;
639 }
640
641 /*
642 * Additionally check for SMAP faults...
643 * which are characterized by page-present and
644 * the AC bit unset (i.e. not from copyin/out path).
645 */
646 if (__improbable(code & T_PF_PROT &&
647 pmap_smap_enabled &&
648 (saved_state->isf.rflags & EFL_AC) == 0)) {
649 goto debugger_entry;
650 }
651
652 /*
653 * If we're not sharing cr3 with the user
654 * and we faulted in copyio,
655 * then switch cr3 here and dismiss the fault.
656 */
657 if (no_shared_cr3 &&
658 (thread->machine.specFlags & CopyIOActive) &&
659 map->pmap->pm_cr3 != get_cr3_base()) {
660 pmap_assert(current_cpu_datap()->cpu_pmap_pcid_enabled == FALSE);
661 set_cr3_raw(map->pmap->pm_cr3);
662 return;
663 }
664 if (__improbable(vaddr < PAGE_SIZE) &&
665 ((thread->machine.specFlags & CopyIOActive) == 0)) {
666 goto debugger_entry;
667 }
668 }
669 #endif
670 }
671 }
672
673 (void) ml_set_interrupts_enabled(intr);
674
675 switch (type) {
676 case T_NO_FPU:
677 fpnoextflt();
678 return;
679
680 case T_FPU_FAULT:
681 fpextovrflt();
682 return;
683
684 case T_FLOATING_POINT_ERROR:
685 fpexterrflt();
686 return;
687
688 case T_SSE_FLOAT_ERROR:
689 fpSSEexterrflt();
690 return;
691
692 case T_INVALID_OPCODE:
693 fpUDflt(kern_ip);
694 goto debugger_entry;
695
696 case T_DEBUG:
697 if ((saved_state->isf.rflags & EFL_TF) == 0 && NO_WATCHPOINTS) {
698 /* We've somehow encountered a debug
699 * register match that does not belong
700 * to the kernel debugger.
701 * This isn't supposed to happen.
702 */
703 reset_dr7();
704 return;
705 }
706 goto debugger_entry;
707 case T_INT3:
708 goto debugger_entry;
709 case T_PAGE_FAULT:
710
711 #if CONFIG_DTRACE
712 if (thread != THREAD_NULL && thread->options & TH_OPT_DTRACE) { /* Executing under dtrace_probe? */
713 if (dtrace_tally_fault(vaddr)) { /* Should a fault under dtrace be ignored? */
714 /*
715 * DTrace has "anticipated" the possibility of this fault, and has
716 * established the suitable recovery state. Drop down now into the
717 * recovery handling code in "case T_GENERAL_PROTECTION:".
718 */
719 goto FALL_THROUGH;
720 }
721 }
722 #endif /* CONFIG_DTRACE */
723
724 prot = VM_PROT_READ;
725
726 if (code & T_PF_WRITE) {
727 prot |= VM_PROT_WRITE;
728 }
729 if (code & T_PF_EXECUTE) {
730 prot |= VM_PROT_EXECUTE;
731 }
732
733 fault_result = result = vm_fault(map,
734 vaddr,
735 prot,
736 FALSE, VM_KERN_MEMORY_NONE,
737 THREAD_UNINT, NULL, 0);
738
739 if (result == KERN_SUCCESS) {
740 #if NCOPY_WINDOWS > 0
741 if (fault_in_copy_window != -1) {
742 ml_set_interrupts_enabled(FALSE);
743 copy_window_fault(thread, map,
744 fault_in_copy_window);
745 (void) ml_set_interrupts_enabled(intr);
746 }
747 #endif /* NCOPY_WINDOWS > 0 */
748 return;
749 }
750 /*
751 * fall through
752 */
753 #if CONFIG_DTRACE
754 FALL_THROUGH:
755 #endif /* CONFIG_DTRACE */
756
757 case T_GENERAL_PROTECTION:
758 /*
759 * If there is a failure recovery address
760 * for this fault, go there.
761 */
762 for (rp = recover_table; rp < recover_table_end; rp++) {
763 if (kern_ip == rp->fault_addr) {
764 set_recovery_ip(saved_state, rp->recover_addr);
765 return;
766 }
767 }
768
769 /*
770 * Check thread recovery address also.
771 */
772 if (thread != THREAD_NULL && thread->recover) {
773 set_recovery_ip(saved_state, thread->recover);
774 thread->recover = 0;
775 return;
776 }
777 /*
778 * Unanticipated page-fault errors in kernel
779 * should not happen.
780 *
781 * fall through...
782 */
783 default:
784 /*
785 * Exception 15 is reserved but some chips may generate it
786 * spuriously. Seen at startup on AMD Athlon-64.
787 */
788 if (type == 15) {
789 kprintf("kernel_trap() ignoring spurious trap 15\n");
790 return;
791 }
792 debugger_entry:
793 /* Ensure that the i386_kernel_state at the base of the
794 * current thread's stack (if any) is synchronized with the
795 * context at the moment of the trap, to facilitate
796 * access through the debugger.
797 */
798 sync_iss_to_iks(state);
799 #if MACH_KDP
800 if (kdp_i386_trap(type, saved_state, result, (vm_offset_t)vaddr)) {
801 return;
802 }
803 #endif
804 }
805 pal_cli();
806 panic_trap(saved_state, trap_pl, fault_result);
807 /*
808 * NO RETURN
809 */
810 }
811
812 static void
813 set_recovery_ip(x86_saved_state64_t *saved_state, vm_offset_t ip)
814 {
815 saved_state->isf.rip = ip;
816 }
817
818 static void
819 panic_trap(x86_saved_state64_t *regs, uint32_t pl, kern_return_t fault_result)
820 {
821 const char *trapname = "Unknown";
822 pal_cr_t cr0, cr2, cr3, cr4;
823 boolean_t potential_smep_fault = FALSE, potential_kernel_NX_fault = FALSE;
824 boolean_t potential_smap_fault = FALSE;
825
826 pal_get_control_registers( &cr0, &cr2, &cr3, &cr4 );
827 assert(ml_get_interrupts_enabled() == FALSE);
828 current_cpu_datap()->cpu_fatal_trap_state = regs;
829 /*
830 * Issue an I/O port read if one has been requested - this is an
831 * event logic analyzers can use as a trigger point.
832 */
833 panic_io_port_read();
834
835 kprintf("CPU %d panic trap number 0x%x, rip 0x%016llx\n",
836 cpu_number(), regs->isf.trapno, regs->isf.rip);
837 kprintf("cr0 0x%016llx cr2 0x%016llx cr3 0x%016llx cr4 0x%016llx\n",
838 cr0, cr2, cr3, cr4);
839
840 if (regs->isf.trapno < TRAP_TYPES) {
841 trapname = trap_type[regs->isf.trapno];
842 }
843
844 if ((regs->isf.trapno == T_PAGE_FAULT) && (regs->isf.err == (T_PF_PROT | T_PF_EXECUTE)) && (regs->isf.rip == regs->cr2)) {
845 if (pmap_smep_enabled && (regs->isf.rip < VM_MAX_USER_PAGE_ADDRESS)) {
846 potential_smep_fault = TRUE;
847 } else if (regs->isf.rip >= VM_MIN_KERNEL_AND_KEXT_ADDRESS) {
848 potential_kernel_NX_fault = TRUE;
849 }
850 } else if (pmap_smap_enabled &&
851 regs->isf.trapno == T_PAGE_FAULT &&
852 regs->isf.err & T_PF_PROT &&
853 regs->cr2 < VM_MAX_USER_PAGE_ADDRESS &&
854 regs->isf.rip >= VM_MIN_KERNEL_AND_KEXT_ADDRESS) {
855 potential_smap_fault = TRUE;
856 }
857
858 #undef panic
859 panic("Kernel trap at 0x%016llx, type %d=%s, registers:\n"
860 "CR0: 0x%016llx, CR2: 0x%016llx, CR3: 0x%016llx, CR4: 0x%016llx\n"
861 "RAX: 0x%016llx, RBX: 0x%016llx, RCX: 0x%016llx, RDX: 0x%016llx\n"
862 "RSP: 0x%016llx, RBP: 0x%016llx, RSI: 0x%016llx, RDI: 0x%016llx\n"
863 "R8: 0x%016llx, R9: 0x%016llx, R10: 0x%016llx, R11: 0x%016llx\n"
864 "R12: 0x%016llx, R13: 0x%016llx, R14: 0x%016llx, R15: 0x%016llx\n"
865 "RFL: 0x%016llx, RIP: 0x%016llx, CS: 0x%016llx, SS: 0x%016llx\n"
866 "Fault CR2: 0x%016llx, Error code: 0x%016llx, Fault CPU: 0x%x%s%s%s%s, PL: %d, VF: %d\n",
867 regs->isf.rip, regs->isf.trapno, trapname,
868 cr0, cr2, cr3, cr4,
869 regs->rax, regs->rbx, regs->rcx, regs->rdx,
870 regs->isf.rsp, regs->rbp, regs->rsi, regs->rdi,
871 regs->r8, regs->r9, regs->r10, regs->r11,
872 regs->r12, regs->r13, regs->r14, regs->r15,
873 regs->isf.rflags, regs->isf.rip, regs->isf.cs & 0xFFFF,
874 regs->isf.ss & 0xFFFF, regs->cr2, regs->isf.err, regs->isf.cpu,
875 virtualized ? " VMM" : "",
876 potential_kernel_NX_fault ? " Kernel NX fault" : "",
877 potential_smep_fault ? " SMEP/User NX fault" : "",
878 potential_smap_fault ? " SMAP fault" : "",
879 pl,
880 fault_result);
881 /*
882 * This next statement is not executed,
883 * but it's needed to stop the compiler using tail call optimization
884 * for the panic call - which confuses the subsequent backtrace.
885 */
886 cr0 = 0;
887 }
888
889 #if CONFIG_DTRACE
890 extern kern_return_t dtrace_user_probe(x86_saved_state_t *);
891 #endif
892
893 #if DEBUG
894 uint32_t fsigs[2];
895 uint32_t fsigns, fsigcs;
896 #endif
897
898 /*
899 * Trap from user mode.
900 */
901 void
902 user_trap(
903 x86_saved_state_t *saved_state)
904 {
905 int exc;
906 int err;
907 mach_exception_code_t code;
908 mach_exception_subcode_t subcode;
909 int type;
910 user_addr_t vaddr;
911 vm_prot_t prot;
912 thread_t thread = current_thread();
913 kern_return_t kret;
914 user_addr_t rip;
915 unsigned long dr6 = 0; /* 32 bit for i386, 64 bit for x86_64 */
916
917 assert((is_saved_state32(saved_state) && !thread_is_64bit_addr(thread)) ||
918 (is_saved_state64(saved_state) && thread_is_64bit_addr(thread)));
919
920 if (is_saved_state64(saved_state)) {
921 x86_saved_state64_t *regs;
922
923 regs = saved_state64(saved_state);
924
925 /* Record cpu where state was captured */
926 regs->isf.cpu = cpu_number();
927
928 type = regs->isf.trapno;
929 err = (int)regs->isf.err & 0xffff;
930 vaddr = (user_addr_t)regs->cr2;
931 rip = (user_addr_t)regs->isf.rip;
932 } else {
933 x86_saved_state32_t *regs;
934
935 regs = saved_state32(saved_state);
936
937 /* Record cpu where state was captured */
938 regs->cpu = cpu_number();
939
940 type = regs->trapno;
941 err = regs->err & 0xffff;
942 vaddr = (user_addr_t)regs->cr2;
943 rip = (user_addr_t)regs->eip;
944 }
945
946 if ((type == T_DEBUG) && thread->machine.ids) {
947 unsigned long clear = 0;
948 /* Stash and clear this processor's DR6 value, in the event
949 * this was a debug register match
950 */
951 __asm__ volatile ("mov %%db6, %0" : "=r" (dr6));
952 __asm__ volatile ("mov %0, %%db6" : : "r" (clear));
953 }
954
955 pal_sti();
956
957 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
958 (MACHDBG_CODE(DBG_MACH_EXCP_UTRAP_x86, type)) | DBG_FUNC_NONE,
959 (unsigned)(vaddr >> 32), (unsigned)vaddr,
960 (unsigned)(rip >> 32), (unsigned)rip, 0);
961
962 code = 0;
963 subcode = 0;
964 exc = 0;
965
966 #if CONFIG_DTRACE
967 /*
968 * DTrace does not consume all user traps, only INT_3's for now.
969 * Avoid needlessly calling tempDTraceTrapHook here, and let the
970 * INT_3 case handle them.
971 */
972 #endif
973
974 DEBUG_KPRINT_SYSCALL_MASK(1,
975 "user_trap: type=0x%x(%s) err=0x%x cr2=%p rip=%p\n",
976 type, trap_type[type], err, (void *)(long) vaddr, (void *)(long) rip);
977
978 switch (type) {
979 case T_DIVIDE_ERROR:
980 exc = EXC_ARITHMETIC;
981 code = EXC_I386_DIV;
982 break;
983
984 case T_DEBUG:
985 {
986 pcb_t pcb;
987 /*
988 * Update the PCB with this processor's DR6 value
989 * in the event this was a debug register match.
990 */
991 pcb = THREAD_TO_PCB(thread);
992 if (pcb->ids) {
993 /*
994 * We can get and set the status register
995 * in 32-bit mode even on a 64-bit thread
996 * because the high order bits are not
997 * used on x86_64
998 */
999 if (thread_is_64bit_addr(thread)) {
1000 x86_debug_state64_t *ids = pcb->ids;
1001 ids->dr6 = dr6;
1002 } else { /* 32 bit thread */
1003 x86_debug_state32_t *ids = pcb->ids;
1004 ids->dr6 = (uint32_t) dr6;
1005 }
1006 }
1007 exc = EXC_BREAKPOINT;
1008 code = EXC_I386_SGL;
1009 break;
1010 }
1011 case T_INT3:
1012 #if CONFIG_DTRACE
1013 if (dtrace_user_probe(saved_state) == KERN_SUCCESS) {
1014 return; /* If it succeeds, we are done... */
1015 }
1016 #endif
1017 exc = EXC_BREAKPOINT;
1018 code = EXC_I386_BPT;
1019 break;
1020
1021 case T_OVERFLOW:
1022 exc = EXC_ARITHMETIC;
1023 code = EXC_I386_INTO;
1024 break;
1025
1026 case T_OUT_OF_BOUNDS:
1027 exc = EXC_SOFTWARE;
1028 code = EXC_I386_BOUND;
1029 break;
1030
1031 case T_INVALID_OPCODE:
1032 #if !defined(RC_HIDE_XNU_J137)
1033 fpUDflt(rip); /* May return from exception directly */
1034 #endif
1035 exc = EXC_BAD_INSTRUCTION;
1036 code = EXC_I386_INVOP;
1037 break;
1038
1039 case T_NO_FPU:
1040 fpnoextflt();
1041 return;
1042
1043 case T_FPU_FAULT:
1044 fpextovrflt(); /* Propagates exception directly, doesn't return */
1045 return;
1046
1047 case T_INVALID_TSS: /* invalid TSS == iret with NT flag set */
1048 exc = EXC_BAD_INSTRUCTION;
1049 code = EXC_I386_INVTSSFLT;
1050 subcode = err;
1051 break;
1052
1053 case T_SEGMENT_NOT_PRESENT:
1054 exc = EXC_BAD_INSTRUCTION;
1055 code = EXC_I386_SEGNPFLT;
1056 subcode = err;
1057 break;
1058
1059 case T_STACK_FAULT:
1060 exc = EXC_BAD_INSTRUCTION;
1061 code = EXC_I386_STKFLT;
1062 subcode = err;
1063 break;
1064
1065 case T_GENERAL_PROTECTION:
1066 /*
1067 * There's a wide range of circumstances which generate this
1068 * class of exception. From user-space, many involve bad
1069 * addresses (such as a non-canonical 64-bit address).
1070 * So we map this to EXC_BAD_ACCESS (and thereby SIGSEGV).
1071 * The trouble is cr2 doesn't contain the faulting address;
1072 * we'd need to decode the faulting instruction to really
1073 * determine this. We'll leave that to debuggers.
1074 * However, attempted execution of privileged instructions
1075 * (e.g. cli) also generate GP faults and so we map these to
1076 * to EXC_BAD_ACCESS (and thence SIGSEGV) also - rather than
1077 * EXC_BAD_INSTRUCTION which is more accurate. We just can't
1078 * win!
1079 */
1080 exc = EXC_BAD_ACCESS;
1081 code = EXC_I386_GPFLT;
1082 subcode = err;
1083 break;
1084
1085 case T_PAGE_FAULT:
1086 {
1087 prot = VM_PROT_READ;
1088
1089 if (err & T_PF_WRITE) {
1090 prot |= VM_PROT_WRITE;
1091 }
1092 if (__improbable(err & T_PF_EXECUTE)) {
1093 prot |= VM_PROT_EXECUTE;
1094 }
1095 #if DEVELOPMENT || DEBUG
1096 uint32_t fsig = 0;
1097 fsig = thread_fpsimd_hash(thread);
1098 #if DEBUG
1099 fsigs[0] = fsig;
1100 #endif
1101 #endif
1102 kret = vm_fault(thread->map,
1103 vaddr,
1104 prot, FALSE, VM_KERN_MEMORY_NONE,
1105 THREAD_ABORTSAFE, NULL, 0);
1106 #if DEVELOPMENT || DEBUG
1107 if (fsig) {
1108 uint32_t fsig2 = thread_fpsimd_hash(thread);
1109 #if DEBUG
1110 fsigcs++;
1111 fsigs[1] = fsig2;
1112 #endif
1113 if (fsig != fsig2) {
1114 panic("FP/SIMD state hash mismatch across fault thread: %p 0x%x->0x%x", thread, fsig, fsig2);
1115 }
1116 } else {
1117 #if DEBUG
1118 fsigns++;
1119 #endif
1120 }
1121 #endif
1122 if (__probable((kret == KERN_SUCCESS) || (kret == KERN_ABORTED))) {
1123 thread_exception_return();
1124 /*NOTREACHED*/
1125 }
1126
1127 user_page_fault_continue(kret);
1128 } /* NOTREACHED */
1129 break;
1130
1131 case T_SSE_FLOAT_ERROR:
1132 fpSSEexterrflt(); /* Propagates exception directly, doesn't return */
1133 return;
1134
1135
1136 case T_FLOATING_POINT_ERROR:
1137 fpexterrflt(); /* Propagates exception directly, doesn't return */
1138 return;
1139
1140 case T_DTRACE_RET:
1141 #if CONFIG_DTRACE
1142 if (dtrace_user_probe(saved_state) == KERN_SUCCESS) {
1143 return; /* If it succeeds, we are done... */
1144 }
1145 #endif
1146 /*
1147 * If we get an INT 0x7f when we do not expect to,
1148 * treat it as an illegal instruction
1149 */
1150 exc = EXC_BAD_INSTRUCTION;
1151 code = EXC_I386_INVOP;
1152 break;
1153
1154 default:
1155 panic("Unexpected user trap, type %d", type);
1156 return;
1157 }
1158 /* Note: Codepaths that directly return from user_trap() have pending
1159 * ASTs processed in locore
1160 */
1161 i386_exception(exc, code, subcode);
1162 /* NOTREACHED */
1163 }
1164
1165 /*
1166 * Handle exceptions for i386.
1167 *
1168 * If we are an AT bus machine, we must turn off the AST for a
1169 * delayed floating-point exception.
1170 *
1171 * If we are providing floating-point emulation, we may have
1172 * to retrieve the real register values from the floating point
1173 * emulator.
1174 */
1175 void
1176 i386_exception(
1177 int exc,
1178 mach_exception_code_t code,
1179 mach_exception_subcode_t subcode)
1180 {
1181 mach_exception_data_type_t codes[EXCEPTION_CODE_MAX];
1182
1183 DEBUG_KPRINT_SYSCALL_MACH("i386_exception: exc=%d code=0x%llx subcode=0x%llx\n",
1184 exc, code, subcode);
1185 codes[0] = code; /* new exception interface */
1186 codes[1] = subcode;
1187 exception_triage(exc, codes, 2);
1188 /*NOTREACHED*/
1189 }
1190
1191
1192 /* Synchronize a thread's x86_kernel_state (if any) with the given
1193 * x86_saved_state_t obtained from the trap/IPI handler; called in
1194 * kernel_trap() prior to entering the debugger, and when receiving
1195 * an "MP_KDP" IPI. Called with null saved_state if an incoming IPI
1196 * was detected from the kernel while spinning with interrupts masked.
1197 */
1198
1199 void
1200 sync_iss_to_iks(x86_saved_state_t *saved_state)
1201 {
1202 struct x86_kernel_state *iks = NULL;
1203 vm_offset_t kstack;
1204 boolean_t record_active_regs = FALSE;
1205
1206 /* The PAL may have a special way to sync registers */
1207 if (saved_state && saved_state->flavor == THREAD_STATE_NONE) {
1208 pal_get_kern_regs( saved_state );
1209 }
1210
1211 if (current_thread() != NULL &&
1212 (kstack = current_thread()->kernel_stack) != 0) {
1213 x86_saved_state64_t *regs = saved_state64(saved_state);
1214
1215 iks = STACK_IKS(kstack);
1216
1217 /* Did we take the trap/interrupt in kernel mode? */
1218 if (saved_state == NULL || /* NULL => polling in kernel */
1219 regs == USER_REGS64(current_thread())) {
1220 record_active_regs = TRUE;
1221 } else {
1222 iks->k_rbx = regs->rbx;
1223 iks->k_rsp = regs->isf.rsp;
1224 iks->k_rbp = regs->rbp;
1225 iks->k_r12 = regs->r12;
1226 iks->k_r13 = regs->r13;
1227 iks->k_r14 = regs->r14;
1228 iks->k_r15 = regs->r15;
1229 iks->k_rip = regs->isf.rip;
1230 }
1231 }
1232
1233 if (record_active_regs == TRUE) {
1234 /* Show the trap handler path */
1235 __asm__ volatile ("movq %%rbx, %0" : "=m" (iks->k_rbx));
1236 __asm__ volatile ("movq %%rsp, %0" : "=m" (iks->k_rsp));
1237 __asm__ volatile ("movq %%rbp, %0" : "=m" (iks->k_rbp));
1238 __asm__ volatile ("movq %%r12, %0" : "=m" (iks->k_r12));
1239 __asm__ volatile ("movq %%r13, %0" : "=m" (iks->k_r13));
1240 __asm__ volatile ("movq %%r14, %0" : "=m" (iks->k_r14));
1241 __asm__ volatile ("movq %%r15, %0" : "=m" (iks->k_r15));
1242 /* "Current" instruction pointer */
1243 __asm__ volatile ("leaq 1f(%%rip), %%rax; mov %%rax, %0\n1:"
1244 : "=m" (iks->k_rip)
1245 :
1246 : "rax");
1247 }
1248 }
1249
1250 /*
1251 * This is used by the NMI interrupt handler (from mp.c) to
1252 * uncondtionally sync the trap handler context to the IKS
1253 * irrespective of whether the NMI was fielded in kernel
1254 * or user space.
1255 */
1256 void
1257 sync_iss_to_iks_unconditionally(__unused x86_saved_state_t *saved_state)
1258 {
1259 struct x86_kernel_state *iks;
1260 vm_offset_t kstack;
1261
1262 if ((kstack = current_thread()->kernel_stack) != 0) {
1263 iks = STACK_IKS(kstack);
1264 /* Display the trap handler path */
1265 __asm__ volatile ("movq %%rbx, %0" : "=m" (iks->k_rbx));
1266 __asm__ volatile ("movq %%rsp, %0" : "=m" (iks->k_rsp));
1267 __asm__ volatile ("movq %%rbp, %0" : "=m" (iks->k_rbp));
1268 __asm__ volatile ("movq %%r12, %0" : "=m" (iks->k_r12));
1269 __asm__ volatile ("movq %%r13, %0" : "=m" (iks->k_r13));
1270 __asm__ volatile ("movq %%r14, %0" : "=m" (iks->k_r14));
1271 __asm__ volatile ("movq %%r15, %0" : "=m" (iks->k_r15));
1272 /* "Current" instruction pointer */
1273 __asm__ volatile ("leaq 1f(%%rip), %%rax; mov %%rax, %0\n1:" : "=m" (iks->k_rip)::"rax");
1274 }
1275 }
1276
1277 #if DEBUG
1278 #define TERI 1
1279 #endif
1280
1281 #if TERI
1282 extern void thread_exception_return_internal(void) __dead2;
1283
1284 void
1285 thread_exception_return(void)
1286 {
1287 thread_t thread = current_thread();
1288 ml_set_interrupts_enabled(FALSE);
1289 if (thread_is_64bit_addr(thread) != task_has_64Bit_addr(thread->task)) {
1290 panic("Task/thread bitness mismatch %p %p, task: %d, thread: %d", thread, thread->task, thread_is_64bit_addr(thread), task_has_64Bit_addr(thread->task));
1291 }
1292
1293 if (thread_is_64bit_addr(thread)) {
1294 if ((gdt_desc_p(USER64_CS)->access & ACC_PL_U) == 0) {
1295 panic("64-GDT mismatch %p, descriptor: %p", thread, gdt_desc_p(USER64_CS));
1296 }
1297 } else {
1298 if ((gdt_desc_p(USER_CS)->access & ACC_PL_U) == 0) {
1299 panic("32-GDT mismatch %p, descriptor: %p", thread, gdt_desc_p(USER_CS));
1300 }
1301 }
1302 assert(get_preemption_level() == 0);
1303 thread_exception_return_internal();
1304 }
1305 #endif
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