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1 /*
2 * Copyright (c) 2000-2013 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 /*
32 * Mach Operating System
33 * Copyright (c) 1991,1990,1989 Carnegie Mellon University
34 * All Rights Reserved.
35 *
36 * Permission to use, copy, modify and distribute this software and its
37 * documentation is hereby granted, provided that both the copyright
38 * notice and this permission notice appear in all copies of the
39 * software, derivative works or modified versions, and any portions
40 * thereof, and that both notices appear in supporting documentation.
41 *
42 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
43 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
44 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
45 *
46 * Carnegie Mellon requests users of this software to return to
47 *
48 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
49 * School of Computer Science
50 * Carnegie Mellon University
51 * Pittsburgh PA 15213-3890
52 *
53 * any improvements or extensions that they make and grant Carnegie Mellon
54 * the rights to redistribute these changes.
55 */
56 /*
57 */
58 #include <mach_assert.h>
59
60 #include <string.h>
61 #include <mach/boolean.h>
62 #include <mach/i386/vm_types.h>
63 #include <mach/i386/vm_param.h>
64 #include <kern/kern_types.h>
65 #include <kern/misc_protos.h>
66 #include <sys/errno.h>
67 #include <i386/param.h>
68 #include <i386/misc_protos.h>
69 #include <i386/cpu_data.h>
70 #include <i386/machine_routines.h>
71 #include <i386/cpuid.h>
72 #include <i386/vmx.h>
73 #include <vm/pmap.h>
74 #include <vm/vm_map.h>
75 #include <vm/vm_kern.h>
76 #include <vm/vm_fault.h>
77
78 #include <libkern/OSAtomic.h>
79 #include <sys/kdebug.h>
80
81 #if !MACH_KDP
82 #include <kdp/kdp_callout.h>
83 #endif /* !MACH_KDP */
84
85 #include <libkern/OSDebug.h>
86 #if CONFIG_DTRACE
87 #include <mach/sdt.h>
88 #endif
89
90 #if 0
91
92 #undef KERNEL_DEBUG
93 #define KERNEL_DEBUG KERNEL_DEBUG_CONSTANT
94 #define KDEBUG 1
95
96 #endif
97
98 /* XXX - should be gone from here */
99 extern void invalidate_icache64(addr64_t addr, unsigned cnt, int phys);
100 extern void flush_dcache64(addr64_t addr, unsigned count, int phys);
101 extern boolean_t phys_page_exists(ppnum_t);
102 extern void bcopy_no_overwrite(const char *from, char *to,vm_size_t bytes);
103 extern void pmap_set_reference(ppnum_t pn);
104 extern void mapping_set_mod(ppnum_t pa);
105 extern void mapping_set_ref(ppnum_t pn);
106
107 extern void ovbcopy(const char *from,
108 char *to,
109 vm_size_t nbytes);
110 void machine_callstack(uintptr_t *buf, vm_size_t callstack_max);
111
112
113 #define value_64bit(value) ((value) & 0xFFFFFFFF00000000ULL)
114 #define low32(x) ((unsigned int)((x) & 0x00000000FFFFFFFFULL))
115
116 #define INT_SIZE (BYTE_SIZE * sizeof (int))
117
118 /*
119 * Set indicated bit in bit string.
120 */
121 void
122 setbit(int bitno, int *s)
123 {
124 s[bitno / INT_SIZE] |= 1 << (bitno % INT_SIZE);
125 }
126
127 /*
128 * Clear indicated bit in bit string.
129 */
130 void
131 clrbit(int bitno, int *s)
132 {
133 s[bitno / INT_SIZE] &= ~(1 << (bitno % INT_SIZE));
134 }
135
136 /*
137 * Test if indicated bit is set in bit string.
138 */
139 int
140 testbit(int bitno, int *s)
141 {
142 return s[bitno / INT_SIZE] & (1 << (bitno % INT_SIZE));
143 }
144
145 /*
146 * Find first bit set in bit string.
147 */
148 int
149 ffsbit(int *s)
150 {
151 int offset;
152
153 for (offset = 0; !*s; offset += (int)INT_SIZE, ++s);
154 return offset + __builtin_ctz(*s);
155 }
156
157 int
158 ffs(unsigned int mask)
159 {
160 if (mask == 0)
161 return 0;
162
163 /*
164 * NOTE: cannot use __builtin_ffs because it generates a call to
165 * 'ffs'
166 */
167 return 1 + __builtin_ctz(mask);
168 }
169
170 void
171 bzero_phys_nc(
172 addr64_t src64,
173 uint32_t bytes)
174 {
175 bzero_phys(src64,bytes);
176 }
177
178 void
179 bzero_phys(
180 addr64_t src64,
181 uint32_t bytes)
182 {
183 bzero(PHYSMAP_PTOV(src64), bytes);
184 }
185
186
187 /*
188 * bcopy_phys - like bcopy but copies from/to physical addresses.
189 */
190
191 void
192 bcopy_phys(
193 addr64_t src64,
194 addr64_t dst64,
195 vm_size_t bytes)
196 {
197 /* Not necessary for K64 - but ensure we stay within a page */
198 if (((((uint32_t)src64 & (NBPG-1)) + bytes) > NBPG) ||
199 ((((uint32_t)dst64 & (NBPG-1)) + bytes) > NBPG) ) {
200 panic("bcopy_phys alignment");
201 }
202 bcopy(PHYSMAP_PTOV(src64), PHYSMAP_PTOV(dst64), bytes);
203 }
204
205 /*
206 * allow a function to get a quick virtual mapping of a physical page
207 */
208
209 int
210 apply_func_phys(
211 addr64_t dst64,
212 vm_size_t bytes,
213 int (*func)(void * buffer, vm_size_t bytes, void * arg),
214 void * arg)
215 {
216 /* Not necessary for K64 - but ensure we stay within a page */
217 if (((((uint32_t)dst64 & (NBPG-1)) + bytes) > NBPG) ) {
218 panic("apply_func_phys alignment");
219 }
220
221 return func(PHYSMAP_PTOV(dst64), bytes, arg);
222 }
223
224 /*
225 * ovbcopy - like bcopy, but recognizes overlapping ranges and handles
226 * them correctly.
227 */
228
229 void
230 ovbcopy(
231 const char *from,
232 char *to,
233 vm_size_t bytes) /* num bytes to copy */
234 {
235 /* Assume that bcopy copies left-to-right (low addr first). */
236 if (from + bytes <= to || to + bytes <= from || to == from)
237 bcopy_no_overwrite(from, to, bytes); /* non-overlapping or no-op*/
238 else if (from > to)
239 bcopy_no_overwrite(from, to, bytes); /* overlapping but OK */
240 else {
241 /* to > from: overlapping, and must copy right-to-left. */
242 from += bytes - 1;
243 to += bytes - 1;
244 while (bytes-- > 0)
245 *to-- = *from--;
246 }
247 }
248
249
250 /*
251 * Read data from a physical address. Memory should not be cache inhibited.
252 */
253
254 uint64_t reportphyreaddelayabs;
255 uint32_t reportphyreadosbt;
256 #if DEVELOPMENT || DEBUG
257 uint32_t phyreadpanic = 1;
258 #else
259 uint32_t phyreadpanic = 0;
260 #endif
261
262 __private_extern__ uint64_t
263 ml_phys_read_data(pmap_paddr_t paddr, int size) {
264 uint64_t result = 0;
265 unsigned char s1;
266 unsigned short s2;
267 boolean_t istate, timeread = FALSE;
268 uint64_t sabs, eabs;
269
270 if (__improbable(!physmap_enclosed(paddr)))
271 panic("%s: 0x%llx out of bounds\n", __FUNCTION__, paddr);
272
273 if (__improbable(reportphyreaddelayabs != 0)) {
274 istate = ml_set_interrupts_enabled(FALSE);
275 sabs = mach_absolute_time();
276 timeread = TRUE;
277 }
278
279 switch (size) {
280 case 1:
281 s1 = *(volatile unsigned char *)PHYSMAP_PTOV(paddr);
282 result = s1;
283 break;
284 case 2:
285 s2 = *(volatile unsigned short *)PHYSMAP_PTOV(paddr);
286 result = s2;
287 break;
288 case 4:
289 result = *(volatile unsigned int *)PHYSMAP_PTOV(paddr);
290 break;
291 case 8:
292 result = *(volatile unsigned long long *)PHYSMAP_PTOV(paddr);
293 break;
294 default:
295 panic("Invalid size %d for ml_phys_read_data\n", size);
296 break;
297 }
298
299 if (__improbable(timeread == TRUE)) {
300 eabs = mach_absolute_time();
301 (void)ml_set_interrupts_enabled(istate);
302
303 if (__improbable((eabs - sabs) > reportphyreaddelayabs)) {
304 if (phyreadpanic) {
305 panic_io_port_read();
306 panic("Read from physical addr 0x%llx took %llu ns, result: 0x%llx (start: %llu, end: %llu), ceiling: %llu", paddr, (eabs - sabs), result, sabs, eabs, reportphyreaddelayabs);
307 }
308
309 if (reportphyreadosbt) {
310 OSReportWithBacktrace("ml_phys_read_data took %lluus\n", (eabs - sabs) / 1000);
311 }
312 #if CONFIG_DTRACE
313 DTRACE_PHYSLAT3(physread, uint64_t, (eabs - sabs),
314 pmap_paddr_t, paddr, uint32_t, size);
315 #endif
316 }
317 }
318
319 return result;
320 }
321
322 static unsigned long long
323 ml_phys_read_long_long(pmap_paddr_t paddr) {
324 return ml_phys_read_data(paddr, 8);
325 }
326
327 unsigned int ml_phys_read( vm_offset_t paddr)
328 {
329 return (unsigned int) ml_phys_read_data((pmap_paddr_t)paddr, 4);
330 }
331
332 unsigned int ml_phys_read_word(vm_offset_t paddr) {
333
334 return (unsigned int) ml_phys_read_data((pmap_paddr_t)paddr, 4);
335 }
336
337 unsigned int ml_phys_read_64(addr64_t paddr64)
338 {
339 return (unsigned int) ml_phys_read_data((pmap_paddr_t)paddr64, 4);
340 }
341
342 unsigned int ml_phys_read_word_64(addr64_t paddr64)
343 {
344 return (unsigned int) ml_phys_read_data((pmap_paddr_t)paddr64, 4);
345 }
346
347 unsigned int ml_phys_read_half(vm_offset_t paddr)
348 {
349 return (unsigned int) ml_phys_read_data((pmap_paddr_t)paddr, 2);
350 }
351
352 unsigned int ml_phys_read_half_64(addr64_t paddr64)
353 {
354 return (unsigned int) ml_phys_read_data((pmap_paddr_t)paddr64, 2);
355 }
356
357 unsigned int ml_phys_read_byte(vm_offset_t paddr)
358 {
359 return (unsigned int) ml_phys_read_data((pmap_paddr_t)paddr, 1);
360 }
361
362 unsigned int ml_phys_read_byte_64(addr64_t paddr64)
363 {
364 return (unsigned int) ml_phys_read_data((pmap_paddr_t)paddr64, 1);
365 }
366
367 unsigned long long ml_phys_read_double(vm_offset_t paddr)
368 {
369 return ml_phys_read_long_long((pmap_paddr_t)paddr);
370 }
371
372 unsigned long long ml_phys_read_double_64(addr64_t paddr64)
373 {
374 return ml_phys_read_long_long((pmap_paddr_t)paddr64);
375 }
376
377
378
379 /*
380 * Write data to a physical address. Memory should not be cache inhibited.
381 */
382
383 static inline void
384 ml_phys_write_data(pmap_paddr_t paddr, unsigned long data, int size)
385 {
386 if (!physmap_enclosed(paddr))
387 panic("%s: 0x%llx out of bounds\n", __FUNCTION__, paddr);
388
389 switch (size) {
390 case 1:
391 *(volatile unsigned char *)PHYSMAP_PTOV(paddr) = (unsigned char)data;
392 break;
393 case 2:
394 *(volatile unsigned short *)PHYSMAP_PTOV(paddr) = (unsigned short)data;
395 break;
396 case 4:
397 *(volatile unsigned int *)PHYSMAP_PTOV(paddr) = (unsigned int)data;
398 break;
399 default:
400 panic("Invalid size %d for ml_phys_write_data\n", size);
401 break;
402 }
403 }
404
405 static void
406 ml_phys_write_long_long(pmap_paddr_t paddr, unsigned long long data)
407 {
408 if (!physmap_enclosed(paddr))
409 panic("%s: 0x%llx out of bounds\n", __FUNCTION__, paddr);
410
411 *(volatile unsigned long long *)PHYSMAP_PTOV(paddr) = data;
412 }
413
414 void ml_phys_write_byte(vm_offset_t paddr, unsigned int data)
415 {
416 ml_phys_write_data((pmap_paddr_t)paddr, data, 1);
417 }
418
419 void ml_phys_write_byte_64(addr64_t paddr64, unsigned int data)
420 {
421 ml_phys_write_data((pmap_paddr_t)paddr64, data, 1);
422 }
423
424 void ml_phys_write_half(vm_offset_t paddr, unsigned int data)
425 {
426 ml_phys_write_data((pmap_paddr_t)paddr, data, 2);
427 }
428
429 void ml_phys_write_half_64(addr64_t paddr64, unsigned int data)
430 {
431 ml_phys_write_data((pmap_paddr_t)paddr64, data, 2);
432 }
433
434 void ml_phys_write(vm_offset_t paddr, unsigned int data)
435 {
436 ml_phys_write_data((pmap_paddr_t)paddr, data, 4);
437 }
438
439 void ml_phys_write_64(addr64_t paddr64, unsigned int data)
440 {
441 ml_phys_write_data((pmap_paddr_t)paddr64, data, 4);
442 }
443
444 void ml_phys_write_word(vm_offset_t paddr, unsigned int data)
445 {
446 ml_phys_write_data((pmap_paddr_t)paddr, data, 4);
447 }
448
449 void ml_phys_write_word_64(addr64_t paddr64, unsigned int data)
450 {
451 ml_phys_write_data((pmap_paddr_t)paddr64, data, 4);
452 }
453
454 void ml_phys_write_double(vm_offset_t paddr, unsigned long long data)
455 {
456 ml_phys_write_long_long((pmap_paddr_t)paddr, data);
457 }
458
459 void ml_phys_write_double_64(addr64_t paddr64, unsigned long long data)
460 {
461 ml_phys_write_long_long((pmap_paddr_t)paddr64, data);
462 }
463
464
465 /* PCI config cycle probing
466 *
467 *
468 * Read the memory location at physical address paddr.
469 * *Does not* recover from machine checks, unlike the PowerPC implementation.
470 * Should probably be deprecated.
471 */
472
473 boolean_t
474 ml_probe_read(vm_offset_t paddr, unsigned int *val)
475 {
476 if ((PAGE_SIZE - (paddr & PAGE_MASK)) < 4)
477 return FALSE;
478
479 *val = ml_phys_read((pmap_paddr_t)paddr);
480
481 return TRUE;
482 }
483
484 /*
485 * Read the memory location at physical address paddr.
486 * This is a part of a device probe, so there is a good chance we will
487 * have a machine check here. So we have to be able to handle that.
488 * We assume that machine checks are enabled both in MSR and HIDs
489 */
490 boolean_t
491 ml_probe_read_64(addr64_t paddr64, unsigned int *val)
492 {
493 if ((PAGE_SIZE - (paddr64 & PAGE_MASK)) < 4)
494 return FALSE;
495
496 *val = ml_phys_read_64((pmap_paddr_t)paddr64);
497 return TRUE;
498 }
499
500
501 int bcmp(
502 const void *pa,
503 const void *pb,
504 size_t len)
505 {
506 const char *a = (const char *)pa;
507 const char *b = (const char *)pb;
508
509 if (len == 0)
510 return 0;
511
512 do
513 if (*a++ != *b++)
514 break;
515 while (--len);
516
517 return (int)len;
518 }
519
520 int
521 memcmp(const void *s1, const void *s2, size_t n)
522 {
523 if (n != 0) {
524 const unsigned char *p1 = s1, *p2 = s2;
525
526 do {
527 if (*p1++ != *p2++)
528 return (*--p1 - *--p2);
529 } while (--n != 0);
530 }
531 return (0);
532 }
533
534 void *
535 memmove(void *dst, const void *src, size_t ulen)
536 {
537 bcopy(src, dst, ulen);
538 return dst;
539 }
540
541 /*
542 * Abstract:
543 * strlen returns the number of characters in "string" preceeding
544 * the terminating null character.
545 */
546
547 size_t
548 strlen(
549 const char *string)
550 {
551 const char *ret = string;
552
553 while (*string++ != '\0')
554 continue;
555 return string - 1 - ret;
556 }
557
558 #if MACH_ASSERT
559
560 /*
561 * Machine-dependent routine to fill in an array with up to callstack_max
562 * levels of return pc information.
563 */
564 void machine_callstack(
565 __unused uintptr_t *buf,
566 __unused vm_size_t callstack_max)
567 {
568 }
569
570 #endif /* MACH_ASSERT */
571
572 void fillPage(ppnum_t pa, unsigned int fill)
573 {
574 pmap_paddr_t src;
575 int i;
576 int cnt = PAGE_SIZE / sizeof(unsigned int);
577 unsigned int *addr;
578
579 src = i386_ptob(pa);
580 for (i = 0, addr = (unsigned int *)PHYSMAP_PTOV(src); i < cnt; i++)
581 *addr++ = fill;
582 }
583
584 static inline void __clflush(void *ptr)
585 {
586 __asm__ volatile("clflush (%0)" : : "r" (ptr));
587 }
588
589 void dcache_incoherent_io_store64(addr64_t pa, unsigned int count)
590 {
591 addr64_t linesize = cpuid_info()->cache_linesize;
592 addr64_t bound = (pa + count + linesize - 1) & ~(linesize - 1);
593
594 mfence();
595
596 while (pa < bound) {
597 __clflush(PHYSMAP_PTOV(pa));
598 pa += linesize;
599 }
600
601 mfence();
602 }
603
604 void dcache_incoherent_io_flush64(addr64_t pa, unsigned int count)
605 {
606 return(dcache_incoherent_io_store64(pa,count));
607 }
608
609 void
610 flush_dcache64(addr64_t addr, unsigned count, int phys)
611 {
612 if (phys) {
613 dcache_incoherent_io_flush64(addr, count);
614 }
615 else {
616 uint64_t linesize = cpuid_info()->cache_linesize;
617 addr64_t bound = (addr + count + linesize -1) & ~(linesize - 1);
618 mfence();
619 while (addr < bound) {
620 __clflush((void *) (uintptr_t) addr);
621 addr += linesize;
622 }
623 mfence();
624 }
625 }
626
627 void
628 invalidate_icache64(__unused addr64_t addr,
629 __unused unsigned count,
630 __unused int phys)
631 {
632 }
633
634
635 addr64_t vm_last_addr;
636
637 void
638 mapping_set_mod(ppnum_t pn)
639 {
640 pmap_set_modify(pn);
641 }
642
643 void
644 mapping_set_ref(ppnum_t pn)
645 {
646 pmap_set_reference(pn);
647 }
648
649 extern i386_cpu_info_t cpuid_cpu_info;
650 void
651 cache_flush_page_phys(ppnum_t pa)
652 {
653 boolean_t istate;
654 unsigned char *cacheline_addr;
655 i386_cpu_info_t *cpuid_infop = cpuid_info();
656 int cacheline_size;
657 int cachelines_to_flush;
658
659 cacheline_size = cpuid_infop->cache_linesize;
660 if (cacheline_size == 0)
661 panic("cacheline_size=0 cpuid_infop=%p\n", cpuid_infop);
662 cachelines_to_flush = PAGE_SIZE/cacheline_size;
663
664 mfence();
665
666 istate = ml_set_interrupts_enabled(FALSE);
667
668 for (cacheline_addr = (unsigned char *)PHYSMAP_PTOV(i386_ptob(pa));
669 cachelines_to_flush > 0;
670 cachelines_to_flush--, cacheline_addr += cacheline_size) {
671 __clflush((void *) cacheline_addr);
672 }
673
674 (void) ml_set_interrupts_enabled(istate);
675
676 mfence();
677 }
678
679
680 #if !MACH_KDP
681 void
682 kdp_register_callout(kdp_callout_fn_t fn, void *arg)
683 {
684 #pragma unused(fn,arg)
685 }
686 #endif
687
688 #if !CONFIG_VMX
689 int host_vmxon(boolean_t exclusive __unused)
690 {
691 return VMX_UNSUPPORTED;
692 }
693
694 void host_vmxoff(void)
695 {
696 return;
697 }
698 #endif