osfmk/x86_64/kpc_x86.c

   1 /*
   2  * Copyright (c) 2012 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28
  29 #include <mach/mach_types.h>
  30 #include <machine/machine_routines.h>
  31 #include <kern/processor.h>
  32 #include <kern/kalloc.h>
  33 #include <i386/cpuid.h>
  34 #include <i386/proc_reg.h>
  35 #include <i386/mp.h>
  36 #include <i386/lapic.h>
  37 #include <sys/errno.h>
  38 #include <kperf/buffer.h>
  39
  40 #include <kern/kpc.h>
  41
  42 #include <kperf/kperf.h>
  43 #include <kperf/sample.h>
  44 #include <kperf/context.h>
  45 #include <kperf/action.h>
  46
  47 #include <chud/chud_xnu.h>
  48
  49
  50
  51 /* Fixed counter mask -- three counters, each with OS and USER */
  52 #define IA32_FIXED_CTR_ENABLE_ALL_CTRS_ALL_RINGS (0x333)
  53 #define IA32_FIXED_CTR_ENABLE_ALL_PMI (0x888)
  54
  55 #define IA32_PERFEVTSEL_PMI (1ull << 20)
  56 #define IA32_PERFEVTSEL_EN (1ull << 22)
  57
  58 /* Non-serialising */
  59 #define USE_RDPMC
  60
  61 #define RDPMC_FIXED_COUNTER_SELECTOR (1ULL<<30)
  62
  63 /* track the last config we enabled */
  64 static uint64_t kpc_running_cfg_pmc_mask = 0;
  65 static uint32_t kpc_running_classes = 0;
  66
  67 /* PMC / MSR accesses */
  68
  69 static uint64_t
  70 IA32_FIXED_CTR_CTRL(void)
  71 {
  72         return rdmsr64( MSR_IA32_PERF_FIXED_CTR_CTRL );
  73 }
  74
  75 static uint64_t
  76 IA32_FIXED_CTRx(uint32_t ctr)
  77 {
  78 #ifdef USE_RDPMC
  79         return rdpmc64(RDPMC_FIXED_COUNTER_SELECTOR | ctr);
  80 #else /* !USE_RDPMC */
  81         return rdmsr64(MSR_IA32_PERF_FIXED_CTR0 + ctr);
  82 #endif /* !USE_RDPMC */
  83 }
  84
  85 #ifdef FIXED_COUNTER_RELOAD
  86 static void
  87 wrIA32_FIXED_CTRx(uint32_t ctr, uint64_t value)
  88 {
  89         return wrmsr64(MSR_IA32_PERF_FIXED_CTR0 + ctr, value);
  90 }
  91 #endif
  92
  93 static uint64_t
  94 IA32_PMCx(uint32_t ctr)
  95 {
  96 #ifdef USE_RDPMC
  97         return rdpmc64(ctr);
  98 #else /* !USE_RDPMC */
  99         return rdmsr64(MSR_IA32_PERFCTR0 + ctr);
 100 #endif /* !USE_RDPMC */
 101 }
 102
 103 static void
 104 wrIA32_PMCx(uint32_t ctr, uint64_t value)
 105 {
 106         return wrmsr64(MSR_IA32_PERFCTR0 + ctr, value);
 107 }
 108
 109 static uint64_t
 110 IA32_PERFEVTSELx(uint32_t ctr)
 111 {
 112         return rdmsr64(MSR_IA32_EVNTSEL0 + ctr);
 113 }
 114
 115 static void
 116 wrIA32_PERFEVTSELx(uint32_t ctr, uint64_t value)
 117 {
 118         wrmsr64(MSR_IA32_EVNTSEL0 + ctr, value);
 119 }
 120
 121
 122 /* internal functions */
 123
 124 boolean_t
 125 kpc_is_running_fixed(void)
 126 {
 127         return (kpc_running_classes & KPC_CLASS_FIXED_MASK) == KPC_CLASS_FIXED_MASK;
 128 }
 129
 130 boolean_t
 131 kpc_is_running_configurable(uint64_t pmc_mask)
 132 {
 133         assert(kpc_popcount(pmc_mask) <= kpc_configurable_count());
 134         return ((kpc_running_classes & KPC_CLASS_CONFIGURABLE_MASK) == KPC_CLASS_CONFIGURABLE_MASK) &&
 135                ((kpc_running_cfg_pmc_mask & pmc_mask) == pmc_mask);
 136 }
 137
 138 uint32_t
 139 kpc_fixed_count(void)
 140 {
 141         i386_cpu_info_t *info = NULL;
 142         info = cpuid_info();
 143         return info->cpuid_arch_perf_leaf.fixed_number;
 144 }
 145
 146 uint32_t
 147 kpc_configurable_count(void)
 148 {
 149         i386_cpu_info_t *info = NULL;
 150         info = cpuid_info();
 151         return info->cpuid_arch_perf_leaf.number;
 152 }
 153
 154 uint32_t
 155 kpc_fixed_config_count(void)
 156 {
 157         return KPC_X86_64_FIXED_CONFIGS;
 158 }
 159
 160 uint32_t
 161 kpc_configurable_config_count(uint64_t pmc_mask)
 162 {
 163         assert(kpc_popcount(pmc_mask) <= kpc_configurable_count());
 164         return kpc_popcount(pmc_mask);
 165 }
 166
 167 uint32_t
 168 kpc_rawpmu_config_count(void)
 169 {
 170         // RAW PMU access not implemented.
 171         return 0;
 172 }
 173
 174 int
 175 kpc_get_rawpmu_config(__unused kpc_config_t *configv)
 176 {
 177         return 0;
 178 }
 179
 180 static uint8_t
 181 kpc_fixed_width(void)
 182 {
 183         i386_cpu_info_t *info = NULL;
 184
 185         info = cpuid_info();
 186
 187         return info->cpuid_arch_perf_leaf.fixed_width;
 188 }
 189
 190 static uint8_t
 191 kpc_configurable_width(void)
 192 {
 193         i386_cpu_info_t *info = NULL;
 194
 195         info = cpuid_info();
 196
 197         return info->cpuid_arch_perf_leaf.width;
 198 }
 199
 200 uint64_t
 201 kpc_fixed_max(void)
 202 {
 203         return (1ULL << kpc_fixed_width()) - 1;
 204 }
 205
 206 uint64_t
 207 kpc_configurable_max(void)
 208 {
 209         return (1ULL << kpc_configurable_width()) - 1;
 210 }
 211
 212 #ifdef FIXED_COUNTER_SHADOW
 213 static uint64_t
 214 kpc_reload_fixed(int ctr)
 215 {
 216         uint64_t old = IA32_FIXED_CTRx(ctr);
 217         wrIA32_FIXED_CTRx(ctr, FIXED_RELOAD(ctr));
 218         return old;
 219 }
 220 #endif
 221
 222 static uint64_t
 223 kpc_reload_configurable(int ctr)
 224 {
 225         uint64_t cfg = IA32_PERFEVTSELx(ctr);
 226
 227         /* counters must be disabled before they can be written to */
 228         uint64_t old = IA32_PMCx(ctr);
 229         wrIA32_PERFEVTSELx(ctr, cfg & ~IA32_PERFEVTSEL_EN);
 230         wrIA32_PMCx(ctr, CONFIGURABLE_RELOAD(ctr));
 231         wrIA32_PERFEVTSELx(ctr, cfg);
 232         return old;
 233 }
 234
 235 void kpc_pmi_handler(x86_saved_state_t *state);
 236
 237 static void
 238 set_running_fixed(boolean_t on)
 239 {
 240         uint64_t global = 0, mask = 0, fixed_ctrl = 0;
 241         int i;
 242         boolean_t enabled;
 243
 244         if( on )
 245                 /* these are per-thread in SMT */
 246                 fixed_ctrl = IA32_FIXED_CTR_ENABLE_ALL_CTRS_ALL_RINGS | IA32_FIXED_CTR_ENABLE_ALL_PMI;
 247         else
 248                 /* don't allow disabling fixed counters */
 249                 return;
 250
 251         wrmsr64( MSR_IA32_PERF_FIXED_CTR_CTRL, fixed_ctrl );
 252
 253         enabled = ml_set_interrupts_enabled(FALSE);
 254
 255         /* rmw the global control */
 256         global = rdmsr64(MSR_IA32_PERF_GLOBAL_CTRL);
 257         for( i = 0; i < (int) kpc_fixed_count(); i++ )
 258                 mask |= (1ULL<<(32+i));
 259
 260         if( on )
 261                 global |= mask;
 262         else
 263                 global &= ~mask;
 264
 265         wrmsr64(MSR_IA32_PERF_GLOBAL_CTRL, global);
 266
 267         ml_set_interrupts_enabled(enabled);
 268 }
 269
 270 static void
 271 set_running_configurable(uint64_t target_mask, uint64_t state_mask)
 272 {
 273         uint32_t cfg_count = kpc_configurable_count();
 274         uint64_t global = 0ULL, cfg = 0ULL, save = 0ULL;
 275         boolean_t enabled;
 276
 277         enabled = ml_set_interrupts_enabled(FALSE);
 278
 279         /* rmw the global control */
 280         global = rdmsr64(MSR_IA32_PERF_GLOBAL_CTRL);
 281
 282         /* need to save and restore counter since it resets when reconfigured */
 283         for (uint32_t i = 0; i < cfg_count; ++i) {
 284                 cfg = IA32_PERFEVTSELx(i);
 285                 save = IA32_PMCx(i);
 286                 wrIA32_PERFEVTSELx(i, cfg | IA32_PERFEVTSEL_PMI | IA32_PERFEVTSEL_EN);
 287                 wrIA32_PMCx(i, save);
 288         }
 289
 290         /* update the global control value */
 291         global &= ~target_mask; /* clear the targeted PMCs bits */
 292         global |= state_mask;   /* update the targeted PMCs bits with their new states */
 293         wrmsr64(MSR_IA32_PERF_GLOBAL_CTRL, global);
 294
 295         ml_set_interrupts_enabled(enabled);
 296 }
 297
 298 static void
 299 kpc_set_running_mp_call( void *vstate )
 300 {
 301         struct kpc_running_remote *mp_config = (struct kpc_running_remote*) vstate;
 302         assert(mp_config);
 303
 304         if (kpc_controls_fixed_counters())
 305                 set_running_fixed(mp_config->classes & KPC_CLASS_FIXED_MASK);
 306
 307         set_running_configurable(mp_config->cfg_target_mask,
 308                                  mp_config->cfg_state_mask);
 309 }
 310
 311 int
 312 kpc_get_fixed_config(kpc_config_t *configv)
 313 {
 314         configv[0] = IA32_FIXED_CTR_CTRL();
 315         return 0;
 316 }
 317
 318 static int
 319 kpc_set_fixed_config(kpc_config_t *configv)
 320 {
 321         (void) configv;
 322
 323         /* NYI */
 324         return -1;
 325 }
 326
 327 int
 328 kpc_get_fixed_counters(uint64_t *counterv)
 329 {
 330         int i, n = kpc_fixed_count();
 331
 332 #ifdef FIXED_COUNTER_SHADOW
 333         uint64_t status;
 334
 335         /* snap the counters */
 336         for( i = 0; i < n; i++ ) {
 337                 counterv[i] = FIXED_SHADOW(ctr) +
 338                         (IA32_FIXED_CTRx(i) - FIXED_RELOAD(ctr));
 339         }
 340
 341         /* Grab the overflow bits */
 342         status = rdmsr64(MSR_IA32_PERF_GLOBAL_STATUS);
 343
 344         /* If the overflow bit is set for a counter, our previous read may or may not have been
 345          * before the counter overflowed. Re-read any counter with it's overflow bit set so
 346          * we know for sure that it has overflowed. The reason this matters is that the math
 347          * is different for a counter that has overflowed. */
 348         for( i = 0; i < n; i++ ) {
 349                 if ((1ull << (i + 32)) & status)
 350                         counterv[i] = FIXED_SHADOW(ctr) +
 351                                 (kpc_fixed_max() - FIXED_RELOAD(ctr) + 1 /* Wrap */) + IA32_FIXED_CTRx(i);
 352         }
 353 #else
 354         for( i = 0; i < n; i++ )
 355                 counterv[i] = IA32_FIXED_CTRx(i);
 356 #endif
 357
 358         return 0;
 359 }
 360
 361 int
 362 kpc_get_configurable_config(kpc_config_t *configv, uint64_t pmc_mask)
 363 {
 364         uint32_t cfg_count = kpc_configurable_count();
 365
 366         assert(configv);
 367
 368         for (uint32_t i = 0; i < cfg_count; ++i)
 369                 if ((1ULL << i) & pmc_mask)
 370                         *configv++  = IA32_PERFEVTSELx(i);
 371         return 0;
 372 }
 373
 374 static int
 375 kpc_set_configurable_config(kpc_config_t *configv, uint64_t pmc_mask)
 376 {
 377         uint32_t cfg_count = kpc_configurable_count();
 378         uint64_t save;
 379
 380         for (uint32_t i = 0; i < cfg_count; i++ ) {
 381                 if (((1ULL << i) & pmc_mask) == 0)
 382                         continue;
 383
 384                 /* need to save and restore counter since it resets when reconfigured */
 385                 save = IA32_PMCx(i);
 386
 387                 /*
 388                  * Some bits are not safe to set from user space.
 389                  * Allow these bits to be set:
 390                  *
 391                  *   0-7    Event select
 392                  *   8-15   UMASK
 393                  *   16     USR
 394                  *   17     OS
 395                  *   18     E
 396                  *   22     EN
 397                  *   23     INV
 398                  *   24-31  CMASK
 399                  *
 400                  * Excluding:
 401                  *
 402                  *   19     PC
 403                  *   20     INT
 404                  *   21     AnyThread
 405                  *   32     IN_TX
 406                  *   33     IN_TXCP
 407                  *   34-63  Reserved
 408                  */
 409                 wrIA32_PERFEVTSELx(i, *configv & 0xffc7ffffull);
 410                 wrIA32_PMCx(i, save);
 411
 412                 /* next configuration word */
 413                 configv++;
 414         }
 415
 416         return 0;
 417 }
 418
 419 int
 420 kpc_get_configurable_counters(uint64_t *counterv, uint64_t pmc_mask)
 421 {
 422         uint32_t cfg_count = kpc_configurable_count();
 423         uint64_t status, *it_counterv = counterv;
 424
 425         /* snap the counters */
 426         for (uint32_t i = 0; i < cfg_count; ++i) {
 427                 if ((1ULL << i) & pmc_mask) {
 428                         *it_counterv++ = CONFIGURABLE_SHADOW(i) +
 429                                          (IA32_PMCx(i) - CONFIGURABLE_RELOAD(i));
 430                 }
 431         }
 432
 433         /* Grab the overflow bits */
 434         status = rdmsr64(MSR_IA32_PERF_GLOBAL_STATUS);
 435
 436         /* reset the iterator */
 437         it_counterv = counterv;
 438
 439         /*
 440          * If the overflow bit is set for a counter, our previous read may or may not have been
 441          * before the counter overflowed. Re-read any counter with it's overflow bit set so
 442          * we know for sure that it has overflowed. The reason this matters is that the math
 443          * is different for a counter that has overflowed.
 444          */
 445         for (uint32_t i = 0; i < cfg_count; ++i) {
 446                 if (((1ULL << i) & pmc_mask) &&
 447                     ((1ULL << i) & status))
 448                 {
 449                         *it_counterv++ = CONFIGURABLE_SHADOW(i) +
 450                                          (kpc_configurable_max() - CONFIGURABLE_RELOAD(i)) + IA32_PMCx(i);
 451                 }
 452         }
 453
 454         return 0;
 455 }
 456
 457 static void
 458 kpc_get_curcpu_counters_mp_call(void *args)
 459 {
 460         struct kpc_get_counters_remote *handler = args;
 461         int offset=0, r=0;
 462
 463         assert(handler);
 464         assert(handler->buf);
 465
 466         offset = cpu_number() * handler->buf_stride;
 467         r = kpc_get_curcpu_counters(handler->classes, NULL, &handler->buf[offset]);
 468
 469         /* number of counters added by this CPU, needs to be atomic  */
 470         hw_atomic_add(&(handler->nb_counters), r);
 471 }
 472
 473 int
 474 kpc_get_all_cpus_counters(uint32_t classes, int *curcpu, uint64_t *buf)
 475 {
 476         int enabled = 0;
 477
 478         struct kpc_get_counters_remote hdl = {
 479                 .classes = classes, .nb_counters = 0,
 480                 .buf_stride = kpc_get_counter_count(classes), .buf = buf
 481         };
 482
 483         assert(buf);
 484
 485         enabled = ml_set_interrupts_enabled(FALSE);
 486
 487         if (curcpu)
 488                 *curcpu = current_processor()->cpu_id;
 489         mp_cpus_call(CPUMASK_ALL, ASYNC, kpc_get_curcpu_counters_mp_call, &hdl);
 490
 491         ml_set_interrupts_enabled(enabled);
 492
 493         return hdl.nb_counters;
 494 }
 495
 496 static void
 497 kpc_set_config_mp_call(void *vmp_config)
 498 {
 499
 500         struct kpc_config_remote *mp_config = vmp_config;
 501         kpc_config_t *new_config = NULL;
 502         uint32_t classes = 0, count = 0;
 503         boolean_t enabled;
 504
 505         assert(mp_config);
 506         assert(mp_config->configv);
 507         classes = mp_config->classes;
 508         new_config = mp_config->configv;
 509
 510         enabled = ml_set_interrupts_enabled(FALSE);
 511
 512         if (classes & KPC_CLASS_FIXED_MASK)
 513         {
 514                 kpc_set_fixed_config(&new_config[count]);
 515                 count += kpc_get_config_count(KPC_CLASS_FIXED_MASK);
 516         }
 517
 518         if (classes & KPC_CLASS_CONFIGURABLE_MASK) {
 519                 kpc_set_configurable_config(&new_config[count], mp_config->pmc_mask);
 520                 count += kpc_popcount(mp_config->pmc_mask);
 521         }
 522
 523         ml_set_interrupts_enabled(enabled);
 524 }
 525
 526 static void
 527 kpc_set_reload_mp_call(void *vmp_config)
 528 {
 529         struct kpc_config_remote *mp_config = vmp_config;
 530         uint64_t *new_period = NULL, max = kpc_configurable_max();
 531         uint32_t classes = 0, count = 0;
 532         boolean_t enabled;
 533
 534         assert(mp_config);
 535         assert(mp_config->configv);
 536         classes = mp_config->classes;
 537         new_period = mp_config->configv;
 538
 539         enabled = ml_set_interrupts_enabled(FALSE);
 540
 541         if (classes & KPC_CLASS_CONFIGURABLE_MASK) {
 542                 /*
 543                  * Update _all_ shadow counters, this cannot be done for only
 544                  * selected PMCs. Otherwise, we would corrupt the configurable
 545                  * shadow buffer since the PMCs are muxed according to the pmc
 546                  * mask.
 547                  */
 548                 uint64_t all_cfg_mask = (1ULL << kpc_configurable_count()) - 1;
 549                 kpc_get_configurable_counters(&CONFIGURABLE_SHADOW(0), all_cfg_mask);
 550
 551                 /* set the new period */
 552                 count = kpc_configurable_count();
 553                 for (uint32_t i = 0; i < count; ++i) {
 554                         /* ignore the counter */
 555                         if (((1ULL << i) & mp_config->pmc_mask) == 0)
 556                                 continue;
 557
 558                         if (*new_period == 0)
 559                                 *new_period = kpc_configurable_max();
 560
 561                         CONFIGURABLE_RELOAD(i) = max - *new_period;
 562
 563                         /* reload the counter */
 564                         kpc_reload_configurable(i);
 565
 566                         /* clear overflow bit just in case */
 567                         wrmsr64(MSR_IA32_PERF_GLOBAL_OVF_CTRL, 1ull << i);
 568
 569                         /* next period value */
 570                         new_period++;
 571                 }
 572         }
 573
 574         ml_set_interrupts_enabled(enabled);
 575 }
 576
 577 int
 578 kpc_set_period_arch( struct kpc_config_remote *mp_config )
 579 {
 580         mp_cpus_call( CPUMASK_ALL, ASYNC, kpc_set_reload_mp_call, mp_config );
 581
 582         return 0;
 583 }
 584
 585
 586 /* interface functions */
 587
 588 void
 589 kpc_arch_init(void)
 590 {
 591         /* No-op */
 592 }
 593
 594 uint32_t
 595 kpc_get_classes(void)
 596 {
 597         return KPC_CLASS_FIXED_MASK | KPC_CLASS_CONFIGURABLE_MASK;
 598 }
 599
 600 int
 601 kpc_set_running_arch(struct kpc_running_remote *mp_config)
 602 {
 603         assert(mp_config);
 604
 605         lapic_set_pmi_func((i386_intr_func_t)kpc_pmi_handler);
 606
 607         /* dispatch to all CPUs */
 608         mp_cpus_call(CPUMASK_ALL, ASYNC, kpc_set_running_mp_call, mp_config);
 609
 610         kpc_running_cfg_pmc_mask = mp_config->cfg_state_mask;
 611         kpc_running_classes = mp_config->classes;
 612
 613         return 0;
 614 }
 615
 616 int
 617 kpc_set_config_arch(struct kpc_config_remote *mp_config)
 618 {
 619         mp_cpus_call( CPUMASK_ALL, ASYNC, kpc_set_config_mp_call, mp_config );
 620
 621         return 0;
 622 }
 623
 624 /* PMI stuff */
 625 void kpc_pmi_handler(__unused x86_saved_state_t *state)
 626 {
 627         uint64_t status, extra;
 628         uint32_t ctr;
 629         int enabled;
 630
 631         enabled = ml_set_interrupts_enabled(FALSE);
 632
 633         status = rdmsr64(MSR_IA32_PERF_GLOBAL_STATUS);
 634
 635 #ifdef FIXED_COUNTER_SHADOW
 636         for (ctr = 0; ctr < kpc_fixed_count(); ctr++) {
 637                 if ((1ULL << (ctr + 32)) & status) {
 638                         extra = kpc_reload_fixed(ctr);
 639
 640                         FIXED_SHADOW(ctr)
 641                                 += (kpc_fixed_max() - FIXED_RELOAD(ctr) + 1 /* Wrap */) + extra;
 642
 643                         BUF_INFO(PERF_KPC_FCOUNTER, ctr, FIXED_SHADOW(ctr), extra, FIXED_ACTIONID(ctr));
 644
 645                         if (FIXED_ACTIONID(ctr))
 646                                 kpc_sample_kperf(FIXED_ACTIONID(ctr));
 647                 }
 648         }
 649 #endif
 650
 651         for (ctr = 0; ctr < kpc_configurable_count(); ctr++) {
 652                 if ((1ULL << ctr) & status) {
 653                         extra = kpc_reload_configurable(ctr);
 654
 655                         CONFIGURABLE_SHADOW(ctr)
 656                                 += kpc_configurable_max() - CONFIGURABLE_RELOAD(ctr) + extra;
 657
 658                         /* kperf can grab the PMCs when it samples so we need to make sure the overflow
 659                          * bits are in the correct state before the call to kperf_sample */
 660                         wrmsr64(MSR_IA32_PERF_GLOBAL_OVF_CTRL, 1ull << ctr);
 661
 662                         BUF_INFO(PERF_KPC_COUNTER, ctr, CONFIGURABLE_SHADOW(ctr), extra, CONFIGURABLE_ACTIONID(ctr));
 663
 664                         if (CONFIGURABLE_ACTIONID(ctr))
 665                                 kpc_sample_kperf(CONFIGURABLE_ACTIONID(ctr));
 666                 }
 667         }
 668
 669         ml_set_interrupts_enabled(enabled);
 670 }
 671
 672 int
 673 kpc_set_sw_inc( uint32_t mask __unused )
 674 {
 675         return ENOTSUP;
 676 }
 677
 678 int
 679 kpc_get_pmu_version(void)
 680 {
 681         i386_cpu_info_t *info = cpuid_info();
 682
 683         uint8_t version_id = info->cpuid_arch_perf_leaf.version;
 684
 685         if (version_id == 3) {
 686                 return KPC_PMU_INTEL_V3;
 687         } else if (version_id == 2) {
 688                 return KPC_PMU_INTEL_V2;
 689         }
 690
 691         return KPC_PMU_ERROR;
 692 }
 693