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1/*
2 * Copyright (c) 2000-2004 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22/*
23 * @OSF_COPYRIGHT@
24 */
25
26#define __APPLE_API_PRIVATE
27
28#include <mach_kdb.h>
29#include <mach_kdp.h>
30#include <mach_kgdb.h>
31#include <ppc/asm.h>
32#include <ppc/proc_reg.h>
33#include <ppc/spec_reg.h>
34#include <machine/cpu_capabilities.h>
35#include <mach/ppc/vm_param.h>
36#include <assym.s>
37
38
39; Definitions of the processor type table format, which drives this code.
40; The table ("processor_types") is assembled in at the end of this file.
41
42#define ptFilter 0
43#define ptVersion 4
44#define ptRevision 6
45#define ptFeatures 8
46#define ptCPUCap 12
47#define ptPwrModes 16
48#define ptPatch 20
49#define ptInitRout 24
50#define ptRptdProc 28
51#define ptLineSize 32
52#define ptl1iSize 36
53#define ptl1dSize 40
54#define ptPTEG 44
55#define ptMaxVAddr 48
56#define ptMaxPAddr 52
57#define ptSize 56
58
59
60; We use cr2 for flags:
61
62#define bootCPU 10
63#define firstInit 9
64#define firstBoot 8
65
66/*
67 * Interrupt and bootup stack for initial processor
68 */
69
70 .file "start.s"
71
72/*
73 * All CPUs start here.
74 *
75 * This code is called from SecondaryLoader
76 *
77 * Various arguments are passed via a table:
78 * R3 = pointer to other startup parameters
79 */
80 .text
81
82ENTRY(resetPOR,TAG_NO_FRAME_USED)
83
84 li r12,0 ; Get a 0
85 stw r12,0xF0(0) ; Make sure the special flag is clear
86 mtmsrd r12 ; Make sure we are in 32-bit mode
87 isync ; Really make sure
88 lwz r3,0xF4(0) ; Get the boot_args pointer
89 b startJoin ; Join up...
90
91
92ENTRY(_start_cpu,TAG_NO_FRAME_USED)
93 crclr bootCPU ; Set non-boot processor
94 crclr firstInit ; Set not first time init
95 lwz r30,ppe_paddr(r3) ; Set current per_proc
96 lwz r28,ppe_paddr+4(r3) ; Set current per_proc
97 rlwinm r30,r30,0,1,0 ; Copy low 32 bits to top 32
98 rlwimi r30,r28,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
99 subi r29,r3,(ACT_PER_PROC-ppe_vaddr) ; Substract mact.PerProc offset
100 mr r3,r30 ; Set current per_proc
101
102;
103; Note that we are just trying to get close. The real TB sync will take
104; place later. The value we are loading is set in two places. For the
105; main processor, it will be the TB at the last interrupt before we went
106; to sleep. For the others, it will be the time just before the main
107; processor woke us up.
108;
109
110 lwz r15,ruptStamp(r3) ; Get the timebase from the other processor
111 li r17,0 ; Clear this out
112 lwz r16,ruptStamp+4(r3) ; Get the timebase from the other processor
113 mtspr tbl,r17 ; Clear bottom so we do not tick
114 mtspr tbu,r15 ; Set top
115 mtspr tbl,r16 ; Then bottom again
116 b allstart
117
118ENTRY(_start,TAG_NO_FRAME_USED)
119
120startJoin:
121 mflr r2 ; Save the return address
122 lis r28,hi16(EXT(PerProcTable)) ; Set PerProcTable
123 lis r30,hi16(EXT(BootProcInfo)) ; Set current per_proc
124 ori r28,r28,lo16(EXT(PerProcTable)) ; Set PerProcTable
125 ori r30,r30,lo16(EXT(BootProcInfo)) ; Set current per_proc
126 stw r30,ppe_paddr+4(r28) ; Set per_proc_entry
127 stw r30,ppe_vaddr(r28) ; Set per_proc_entry
128 subi r29,r28,(ACT_PER_PROC-ppe_vaddr) ; Substract mact.PerProc offset
129 crset bootCPU ; Set boot processor
130
131 lwz r17,pfAvailable(r30) ; Get the available bits
132 rlwinm. r0,r17,0,pfValidb,pfValidb ; Have we initialized the feature flags yet?
133 crmove firstInit,cr0_eq ; Set if we are doing first time init
134 bne allstart ; Yeah, we must be waking up from sleep...
135
136;
137; Here is where we do any one time general low-level initialization
138
139 lis r20,HIGH_ADDR(fwdisplock) ; Get address of the firmware display lock
140 li r19,0 ; Zorch a register
141 ori r20,r20,LOW_ADDR(fwdisplock) ; Get address of the firmware display lock
142 stw r19,0(r20) ; Make sure the lock is free
143
144allstart:
145 mr r31,r3 ; Save away arguments
146
147 crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
148
149 mtsprg 0,r30 ; Set per_proc paddr
150 mtsprg 1,r29 ; Set spr1
151
152 li r9,0 ; Clear out a register
153 mtsprg 2,r9
154 mtsprg 3,r9
155
156 li r7,MSR_VM_OFF ; Get real mode MSR
157 mtmsr r7 ; Set the real mode SRR
158 isync
159
160 lis r26,hi16(processor_types) ; Point to processor table
161 ori r26,r26,lo16(processor_types) ; Other half
162 mfpvr r10 ; Get the PVR
163
164nextPVR: lwz r28,ptFilter(r26) ; Get the filter
165 lwz r27,ptVersion(r26) ; Get the version and revision codes
166 and r28,r10,r28 ; Throw away dont care bits
167 cmplw r27,r28 ; Is this the right set?
168 beq donePVR ; We have the right one...
169 addi r26,r26,ptSize ; Point to the next type
170 b nextPVR ; Check it out...
171
172donePVR: lwz r20,ptInitRout(r26) ; Grab the special init routine
173 mtlr r20 ; Setup to call the init
174
175 bf firstBoot,notFirst ; Not first boot, go...
176
177;
178; The following code just does a general initialization of the features just
179; after the initial first-time boot. This is not done after waking up or on
180; any "secondary" processor. Just after the boot-processor init, we copy the
181; features to any possible per_proc.
182;
183; We are just setting defaults. The specific initialization code will modify these
184; if necessary.
185;
186 lis r18,hi16(EXT(_cpu_capabilities)) ; Get the address of _cpu_capabilities
187 ori r18,r18,lo16(EXT(_cpu_capabilities))
188 lwz r17,ptCPUCap(r26) ; Get the default cpu capabilities
189 stw r17, 0(r18) ; Save the default value in _cpu_capabilities
190
191 lwz r17,ptFeatures(r26) ; Pick up the features
192
193 lwz r18,ptRptdProc(r26) ; Get the reported processor
194 sth r18,pfrptdProc(r30) ; Set the reported processor
195
196 lwz r13,ptPwrModes(r26) ; Get the supported power modes
197 stw r13,pfPowerModes(r30) ; Set the supported power modes
198
199 lwz r13,ptLineSize(r26) ; Get the cache line size
200 sth r13,pflineSize(r30) ; Save it
201 lwz r13,ptl1iSize(r26) ; Get icache size
202 stw r13,pfl1iSize(r30) ; Save it
203 lwz r13,ptl1dSize(r26) ; Get dcache size
204 stw r13,pfl1dSize(r30) ; Save it
205 lwz r13,ptPTEG(r26) ; Get PTEG size address
206 stw r13,pfPTEG(r30) ; Save it
207 lwz r13,ptMaxVAddr(r26) ; Get max virtual address
208 stw r13,pfMaxVAddr(r30) ; Save it
209 lwz r13,ptMaxPAddr(r26) ; Get max physical address
210 stw r13,pfMaxPAddr(r30) ; Save it
211
212
213; Go through the patch table, changing performance sensitive kernel routines based on the
214; processor type or other things.
215
216 lis r11,hi16(EXT(patch_table))
217 ori r11,r11,lo16(EXT(patch_table))
218 lwz r19,ptPatch(r26) ; Get ptPatch field
219patch_loop:
220 lwz r16,patchType(r11) ; Load the patch type
221 lwz r15,patchValue(r11) ; Load the patch value
222 cmplwi cr1,r16,PATCH_FEATURE ; Is it a patch feature entry
223 cmplwi cr7,r16,PATCH_END_OF_TABLE ; end of table?
224 and. r14,r15,r19 ; Is it set in the patch feature
225 crandc cr0_eq,cr1_eq,cr0_eq ; Do we have a match
226 beq cr7,doOurInit ; end of table, Go do processor specific initialization
227 beq patch_apply ; proc feature matches, so patch memory
228 cmplwi cr1,r16,PATCH_PROCESSOR ; Is it a patch processor entry
229 cmplw cr0,r15,r18 ; Check matching processor
230 crand cr0_eq,cr1_eq,cr0_eq ; Do we have a match
231 bne patch_skip ; No, skip patch memory
232patch_apply:
233 lwz r13,patchAddr(r11) ; Load the address to patch
234 lwz r14,patchData(r11) ; Load the patch data
235 stw r14,0(r13) ; Patch the location
236 dcbf 0,r13 ; Flush the old one
237 sync ; Make sure we see it all
238 icbi 0,r13 ; Flush the i-cache
239 isync ; Hang out
240 sync ; Hang out some more...
241patch_skip:
242 addi r11,r11,peSize ; Point to the next patch entry
243 b patch_loop ; handle next
244
245
246; Additional processors join here after skipping above code.
247
248notFirst: lwz r17,pfAvailable(r30) ; Get our features
249
250doOurInit: mr. r20,r20 ; See if initialization routine
251 crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
252 bnelrl ; Do the initialization
253
254 ori r17,r17,lo16(pfValid) ; Set the valid bit
255 stw r17,pfAvailable(r30) ; Set the available features
256
257 rlwinm. r0,r17,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
258 mtsprg 2,r17 ; Remember the feature flags
259
260 bne++ start64 ; Skip following if 64-bit...
261
262 mfspr r6,hid0 ; Get the HID0
263 rlwinm r6,r6,0,sleep+1,doze-1 ; Remove any vestiges of sleep
264 mtspr hid0,r6 ; Set the insominac HID0
265 isync
266
267; Clear the BAT registers
268
269 li r9,0 ; Clear out a register
270 sync
271 isync
272 mtdbatu 0,r9 ; Invalidate maps
273 mtdbatl 0,r9 ; Invalidate maps
274 mtdbatu 1,r9 ; Invalidate maps
275 mtdbatl 1,r9 ; Invalidate maps
276 mtdbatu 2,r9 ; Invalidate maps
277 mtdbatl 2,r9 ; Invalidate maps
278 mtdbatu 3,r9 ; Invalidate maps
279 mtdbatl 3,r9 ; Invalidate maps
280 sync
281 isync
282 mtibatu 0,r9 ; Invalidate maps
283 mtibatl 0,r9 ; Invalidate maps
284 mtibatu 1,r9 ; Invalidate maps
285 mtibatl 1,r9 ; Invalidate maps
286 mtibatu 2,r9 ; Invalidate maps
287 mtibatl 2,r9 ; Invalidate maps
288 mtibatu 3,r9 ; Invalidate maps
289 mtibatl 3,r9 ; Invalidate maps
290 sync
291 isync
292 b startcommon ; Go join up the common start routine
293
294start64: lis r5,hi16(startcommon) ; Get top of address of continue point
295 mfspr r6,hid0 ; Get the HID0
296 ori r5,r5,lo16(startcommon) ; Get low of address of continue point
297 lis r9,hi16(MASK(MSR_HV)|MASK(MSR_SF)) ; ?
298 lis r20,hi16(dozem|napm|sleepm) ; Get mask of power saving features
299 li r7,MSR_VM_OFF ; Get real mode MSR
300 sldi r9,r9,32 ; Slide into position
301 sldi r20,r20,32 ; Slide power stuff into position
302 or r9,r9,r7 ; Form initial MSR
303 andc r6,r6,r20 ; Remove any vestiges of sleep
304 isync
305 mtspr hid0,r6 ; Set the insominac HID0
306 mfspr r6,hid0 ; Get it
307 mfspr r6,hid0 ; Get it
308 mfspr r6,hid0 ; Get it
309 mfspr r6,hid0 ; Get it
310 mfspr r6,hid0 ; Get it
311 mfspr r6,hid0 ; Get it
312 isync
313 mtsrr0 r5 ; Set the continue point
314 mtsrr1 r9 ; Set our normal disabled MSR
315 rfid ; Tally ho...
316
317 .align 5
318
319startcommon:
320 rlwinm. r0,r17,0,pfFloatb,pfFloatb ; See if there is floating point
321 beq- noFloat ; Nope, this is a really stupid machine...
322
323 li r0,MSR_VM_OFF|MASK(MSR_FP) ; Enable for floating point
324 mtmsr r0 /* Set the standard MSR values */
325 isync
326
327 lis r5,HIGH_ADDR(EXT(FloatInit)) /* Get top of floating point init value */
328 ori r5,r5,LOW_ADDR(EXT(FloatInit)) /* Slam bottom */
329 lfd f0,0(r5) /* Initialize FP0 */
330 fmr f1,f0 /* Ours in not */
331 fmr f2,f0 /* to wonder why, */
332 fmr f3,f0 /* ours is but to */
333 fmr f4,f0 /* do or die! */
334 fmr f5,f0
335 fmr f6,f0
336 fmr f7,f0
337 fmr f8,f0
338 fmr f9,f0
339 fmr f10,f0
340 fmr f11,f0
341 fmr f12,f0
342 fmr f13,f0
343 fmr f14,f0
344 fmr f15,f0
345 fmr f16,f0
346 fmr f17,f0
347 fmr f18,f0
348 fmr f19,f0
349 fmr f20,f0
350 fmr f21,f0
351 fmr f22,f0
352 fmr f23,f0
353 fmr f24,f0
354 fmr f25,f0
355 fmr f26,f0
356 fmr f27,f0
357 fmr f28,f0
358 fmr f29,f0
359 fmr f30,f0
360 fmr f31,f0
361
362 li r0, MSR_VM_OFF ; Turn off floating point
363 mtmsr r0
364 isync
365
366noFloat: rlwinm. r0,r17,0,pfAltivecb,pfAltivecb ; See if there is Altivec
367 beq- noVector ; Nope...
368
369 li r0,0 ; Clear out a register
370
371 lis r7,hi16(MSR_VEC_ON) ; Get real mode MSR + Altivec
372 ori r7,r7,lo16(MSR_VM_OFF) ; Get real mode MSR + Altivec
373 mtmsr r7 ; Set the real mode SRR */
374 isync ; Make sure it has happened
375
376 lis r5,hi16(EXT(QNaNbarbarian)) ; Altivec initializer
377 ori r5,r5,lo16(EXT(QNaNbarbarian)) ; Altivec initializer
378
379 mtspr vrsave,r0 ; Set that no VRs are used yet */
380
381 vspltish v1,1 ; Turn on the non-Java bit and saturate
382 vspltisw v0,1 ; Turn on the saturate bit
383 vxor v1,v1,v0 ; Turn off saturate and leave non-Java set
384 lvx v0,br0,r5 ; Initialize VR0
385 mtvscr v1 ; Clear the vector status register
386 vor v2,v0,v0 ; Copy into the next register
387 vor v1,v0,v0 ; Copy into the next register
388 vor v3,v0,v0 ; Copy into the next register
389 vor v4,v0,v0 ; Copy into the next register
390 vor v5,v0,v0 ; Copy into the next register
391 vor v6,v0,v0 ; Copy into the next register
392 vor v7,v0,v0 ; Copy into the next register
393 vor v8,v0,v0 ; Copy into the next register
394 vor v9,v0,v0 ; Copy into the next register
395 vor v10,v0,v0 ; Copy into the next register
396 vor v11,v0,v0 ; Copy into the next register
397 vor v12,v0,v0 ; Copy into the next register
398 vor v13,v0,v0 ; Copy into the next register
399 vor v14,v0,v0 ; Copy into the next register
400 vor v15,v0,v0 ; Copy into the next register
401 vor v16,v0,v0 ; Copy into the next register
402 vor v17,v0,v0 ; Copy into the next register
403 vor v18,v0,v0 ; Copy into the next register
404 vor v19,v0,v0 ; Copy into the next register
405 vor v20,v0,v0 ; Copy into the next register
406 vor v21,v0,v0 ; Copy into the next register
407 vor v22,v0,v0 ; Copy into the next register
408 vor v23,v0,v0 ; Copy into the next register
409 vor v24,v0,v0 ; Copy into the next register
410 vor v25,v0,v0 ; Copy into the next register
411 vor v26,v0,v0 ; Copy into the next register
412 vor v27,v0,v0 ; Copy into the next register
413 vor v28,v0,v0 ; Copy into the next register
414 vor v29,v0,v0 ; Copy into the next register
415 vor v30,v0,v0 ; Copy into the next register
416 vor v31,v0,v0 ; Copy into the next register
417
418 li r0, MSR_VM_OFF ; Turn off vectors
419 mtmsr r0
420 isync
421
422noVector:
423 bl EXT(cacheInit) ; Initializes all caches (including the TLB)
424
425 bt bootCPU,run32
426
427 mfsprg r30,0 ; Phys per proc
428 lwz r29,PP_HIBERNATE(r30)
429 andi. r29, r29, 1
430 beq noHashTableInit ; Skip following if not waking from from hibernate
431 bl EXT(hw_clear_maps) ; Mark all maps as absent from hash table
432 bl EXT(hw_hash_init) ; Clear hash table
433 bl EXT(save_snapshot_restore) ; Reset save area chains
434noHashTableInit:
435 bl EXT(hw_setup_trans) ; Set up hardware needed for translation
436 bl EXT(hw_start_trans) ; Start translating
437
438run32:
439 rlwinm. r0,r17,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
440 beq++ isnot64 ; Skip following if not 64-bit...
441
442 mfmsr r29 ; Get the MSR
443 rldicl r29,r29,0,MSR_SF_BIT+1 ; turn 64-bit mode off
444 mtmsrd r29 ; Set it
445 isync ; Make sure
446
447isnot64: bf bootCPU,callcpu
448
449 lis r29,HIGH_ADDR(EXT(intstack)) ; move onto interrupt stack
450 ori r29,r29,LOW_ADDR(EXT(intstack))
451 addi r29,r29,INTSTACK_SIZE-FM_SIZE
452
453 li r28,0
454 stw r28,FM_BACKPTR(r29) ; store a null frame backpointer
455
456 mr r1,r29
457 mr r3,r31 ; Restore any arguments we may have trashed
458
459; Note that we exit from here with translation still off
460
461 bl EXT(ppc_init) ; Jump into boot init code
462 BREAKPOINT_TRAP
463
464callcpu:
465 mfsprg r31,1 ; Fake activation pointer
466 lwz r31,ACT_PER_PROC(r31) ; Load per_proc
467 lwz r29,PP_INTSTACK_TOP_SS(r31) ; move onto interrupt stack
468
469 li r28,0
470 stw r28,FM_BACKPTR(r29) ; store a null frame backpointer
471
472 mr r1,r29 ; move onto new stack
473 mr r3,r31 ; Restore any arguments we may have trashed
474
475; Note that we exit from here with translation on
476
477 bl EXT(ppc_init_cpu) ; Jump into cpu init code
478 BREAKPOINT_TRAP ; Should never return
479
480;
481; Specific processor initialization routines
482;
483
484; 750
485
486init750:
487 bf firstBoot, init750nb ; No init for wakeup....
488
489 mfspr r13,l2cr ; Get the L2CR
490 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
491 bne+ i750hl2 ; Yes...
492 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
493
494i750hl2:
495 lis r14,hi16(256*1024) ; Base L2 size
496 addis r15,r13,0x3000 ; Hah... Figure this one out...
497 rlwinm r15,r15,4,30,31 ; Isolate
498 rlwinm. r8,r13,0,l2siz,l2sizf ; Was size valid?
499 slw r14,r14,r15 ; Set 256KB, 512KB, or 1MB
500 beq- init750l2none ; Not a valid setting...
501
502 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
503 stw r13,pfl2cr(r30) ; Shadow the L2CR
504 stw r14,pfl2Size(r30) ; Set the L2 size
505 b init750l2done ; Done with L2
506
507init750l2none:
508 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No level 2 cache
509
510init750l2done:
511 mfspr r11,hid0 ; Get the current HID0
512 stw r11,pfHID0(r30) ; Save the HID0 value
513 blr ; Return...
514
515init750nb:
516 lwz r11,pfHID0(r30) ; Get HID0
517 sync
518 mtspr hid0,r11 ; Set the HID
519 isync
520 sync
521 blr
522
523; 750CX
524
525init750CX:
526 bf firstBoot, init750 ; No init for wakeup....
527 mfspr r13,hid1 ; Get HID1
528 li r14,lo16(0xFD5F) ; Get valid
529 rlwinm r13,r13,4,28,31 ; Isolate
530 slw r14,r14,r13 ; Position
531 rlwimi r17,r14,15-pfCanNapb,pfCanNapb,pfCanNapb ; Set it
532 b init750 ; Join common...
533
534
535; 750FX
536
537init750FX:
538 bf firstBoot, init750FXnb
539 mfspr r11, hid1
540 stw r11, pfHID1(r30) ; Save the HID1 value
541 b init750
542
543init750FXnb:
544 lwz r13, pfHID0(r30) ; Get HID0
545 lwz r11, pfHID1(r30) ; Get HID1
546
547 rlwinm. r0, r11, 0, hid1ps, hid1ps ; Isolate the hid1ps bit
548 beq init750FXnb2 ; Clear BTIC if hid1ps set
549 rlwinm r13, r13, 0, btic+1, btic-1 ; Clear the BTIC bit
550
551init750FXnb2:
552 sync
553 mtspr hid0, r13 ; Set the HID
554 isync
555 sync
556
557 rlwinm r12, r11, 0, hid1ps+1, hid1ps-1 ; Select PLL0
558 mtspr hid1, r12 ; Restore PLL config
559 mftb r13 ; Wait 5000 ticks (> 200 us)
560
561init750FXnbloop:
562 mftb r14
563 sub r14, r14, r13
564 cmpli cr0, r14, 5000
565 ble init750FXnbloop
566 mtspr hid1, r11 ; Select the desired PLL
567 blr
568
569; 750FX vers 2.0 or later
570init750FXV2:
571 bf firstBoot, init750FXV2nb ; Wake from sleep
572
573 mfspr r11, hid2
574 stw r11, pfHID2(r30) ; Save the HID2 value
575 b init750FX ; Continue with 750FX init
576
577init750FXV2nb:
578 lwz r13, pfHID2(r30) ; Get HID2
579 rlwinm r13, r13, 0, hid2vmin+1, hid2vmin-1 ; Clear the vmin bit
580 mtspr hid2, r13 ; Restore HID2 value
581 sync ; Wait for it to be done
582 b init750FX
583
584; 7400
585
586init7400: bf firstBoot,i7400nb ; Do different if not initial boot...
587 mfspr r13,l2cr ; Get the L2CR
588 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
589 bne+ i7400hl2 ; Yes...
590 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
591
592i7400hl2: lis r14,hi16(256*1024) ; Base L2 size
593 addis r15,r13,0x3000 ; Hah... Figure this one out...
594 rlwinm r15,r15,4,30,31
595 slw r14,r14,r15 ; Set 256KB, 512KB, 1MB, or 2MB
596
597 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
598 stw r13,pfl2cr(r30) ; Shadow the L2CR
599 stw r14,pfl2Size(r30) ; Set the L2 size
600
601 mfspr r11,hid0 ; Get the current HID0
602 oris r11,r11,hi16(emcpm|eiecm) ; ?
603 mtspr hid0,r11 ; ?
604 isync
605 stw r11,pfHID0(r30) ; Save the HID0 value
606
607 mfspr r11,msscr0 ; Get the msscr0 register
608 stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
609 mfspr r11,msscr1 ; Get the msscr1 register
610 stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
611 blr ; Return...
612
613i7400nb:
614 li r11,0
615 mtspr l2cr,r11 ; Make sure L2CR is zero
616 lwz r11,pfHID0(r30) ; Get HID0
617 sync
618 mtspr hid0,r11 ; Set the HID
619 isync
620 sync
621 lwz r11,pfMSSCR0(r30) ; Get MSSCR0
622 isync
623 sync
624 mtspr msscr0,r11 ; Set the MSSCR0
625 lwz r11,pfMSSCR1(r30) ; Get msscr1
626 isync
627 sync
628 mtspr msscr1,r11 ; Set the msscr1
629 isync
630 sync
631 blr
632
633; 7400 (ver 2.0 - ver 2.7)
634
635init7400v2_7:
636 bf firstBoot, init7400
637 mfspr r13, hid0 ; Get the HID0
638 ori r13, r13, nopdstm ; ?
639 mtspr hid0, r13 ; Set the HID0
640 isync
641 sync
642 b init7400
643
644; 7410
645; Note that this is the same as 7400 except we initialize the l2cr2 register
646
647init7410: li r13,0 ; Clear
648 mtspr 1016,r13 ; Turn off direct cache
649 b init7400 ; Join up with common....
650
651
652; 745X - Any 7450 family processor
653
654init745X:
655 bf firstBoot,init745Xnb ; Do different if not initial boot...
656
657 mfspr r13,l2cr ; Get the L2CR
658 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
659 bne+ init745Xhl2 ; Yes...
660 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
661
662init745Xhl2:
663 mfpvr r14 ; Get processor version
664 rlwinm r14,r14,16,16,31 ; Isolate processor version
665 cmpli cr0, r14, PROCESSOR_VERSION_7457 ; Test for 7457 or
666 cmpli cr1, r14, PROCESSOR_VERSION_7447A ; 7447A
667 cror cr0_eq, cr1_eq, cr0_eq
668 lis r14,hi16(512*1024) ; 512KB L2
669 beq init745Xhl2_2
670
671 lis r14,hi16(256*1024) ; Base L2 size
672 rlwinm r15,r13,22,12,13 ; Convert to 256k, 512k, or 768k
673 add r14,r14,r15 ; Add in minimum
674
675init745Xhl2_2:
676 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
677 stw r13,pfl2cr(r30) ; Shadow the L2CR
678 stw r14,pfl2Size(r30) ; Set the L2 size
679
680; Take care of level 3 cache
681
682 mfspr r13,l3cr ; Get the L3CR
683 rlwinm. r0,r13,0,l3e,l3e ; Any L3?
684 bne+ init745Xhl3 ; Yes...
685 rlwinm r17,r17,0,pfL3b+1,pfL3b-1 ; No L3, turn off feature
686
687init745Xhl3: cmplwi cr0,r13,0 ; No L3 if L3CR is zero
688 beq- init745Xnone ; Go turn off the features...
689 lis r14,hi16(1024*1024) ; Base L3 size
690 rlwinm r15,r13,4,31,31 ; Get size multiplier
691 slw r14,r14,r15 ; Set 1 or 2MB
692
693 stw r13,pfl3crOriginal(r30) ; Shadow the L3CR
694 stw r13,pfl3cr(r30) ; Shadow the L3CR
695 stw r14,pfl3Size(r30) ; Set the L3 size
696 b init745Xfin ; Return....
697
698init745Xnone:
699 rlwinm r17,r17,0,pfL3fab+1,pfL3b-1 ; No 3rd level cache or assist
700 rlwinm r11,r17,pfWillNapb-pfCanNapb,pfCanNapb,pfCanNapb ; Set pfCanNap if pfWillNap is set
701 or r17,r17,r11
702
703init745Xfin:
704 rlwinm r17,r17,0,pfWillNapb+1,pfWillNapb-1 ; Make sure pfWillNap is not set
705
706 mfspr r11,hid0 ; Get the current HID0
707 stw r11,pfHID0(r30) ; Save the HID0 value
708 mfspr r11,hid1 ; Get the current HID1
709 stw r11,pfHID1(r30) ; Save the HID1 value
710 mfspr r11,msscr0 ; Get the msscr0 register
711 stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
712 mfspr r11,msscr1 ; Get the msscr1 register
713 stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
714 mfspr r11,ictrl ; Get the ictrl register
715 stw r11,pfICTRL(r30) ; Save the ICTRL value
716 mfspr r11,ldstcr ; Get the ldstcr register
717 stw r11,pfLDSTCR(r30) ; Save the LDSTCR value
718 mfspr r11,ldstdb ; Get the ldstdb register
719 stw r11,pfLDSTDB(r30) ; Save the LDSTDB value
720 mfspr r11,pir ; Get the pir register
721 stw r11,pfBootConfig(r30) ; Save the BootConfig value
722 blr ; Return....
723
724
725init745Xnb: lwz r11,pfHID0(r30) ; Get HID0
726 sync
727 mtspr hid0,r11 ; Set the HID
728 isync
729 lwz r11,pfHID1(r30) ; Get HID1
730 sync
731 mtspr hid1,r11 ; Set the HID
732 isync
733 lwz r11,pfMSSCR0(r30) ; Get MSSCR0
734 sync
735 mtspr msscr0,r11 ; Set the MSSCR0
736 isync
737 sync
738 lwz r11,pfICTRL(r30) ; Get ICTRL
739 sync
740 mtspr ictrl,r11 ; Set the ICTRL
741 isync
742 sync
743 lwz r11,pfLDSTCR(r30) ; Get LDSTCR
744 sync
745 mtspr ldstcr,r11 ; Set the LDSTCR
746 isync
747 sync
748 lwz r11,pfLDSTDB(r30) ; Get LDSTDB
749 sync
750 mtspr ldstdb,r11 ; Set the LDSTDB
751 isync
752 sync
753 blr
754
755; 7450 - Specific
756
757init7450:
758 bf firstBoot, init745X ; Not boot, use standard init
759
760 mfspr r13, pir ; Get BootConfig from PIR
761 rlwinm. r14, r13, 0, 20, 23 ; Is the pdet value zero
762 bne init7450done ; No, done for now
763
764 ori r13, r13, 0x0400 ; Force pdet value to 4
765 mtspr pir, r13 ; Write back the BootConfig
766
767init7450done:
768 b init745X ; Continue with standard init
769
770
771init970:
772 lis r20,8 ; Set up for 512K L2
773init970x:
774 li r0,0 ; Clear this
775 mtspr hior,r0 ; Make sure that 0 is interrupt prefix
776 bf firstBoot,init970nb ; No init for wakeup or second processor....
777
778
779;
780; We can not query or change the L2 size. We will just
781; phoney up a L2CR to make sysctl "happy" and set the
782; L2 size to 512K.
783;
784
785 lis r0,0x8000 ; Synthesize a "valid" but non-existant L2CR
786 stw r0,pfl2crOriginal(r30) ; Set a dummy L2CR
787 stw r0,pfl2cr(r30) ; Set a dummy L2CR
788 stw r20,pfl2Size(r30) ; Set the L2 size
789
790 mfspr r11,hid0 ; Get original hid0
791 std r11,pfHID0(r30) ; Save original
792 mfspr r11,hid1 ; Get original hid1
793 std r11,pfHID1(r30) ; Save original
794 mfspr r11,hid4 ; Get original hid4
795 std r11,pfHID4(r30) ; Save original
796 mfspr r11,hid5 ; Get original hid5
797 std r11,pfHID5(r30) ; Save original
798
799 lis r0, hi16(dnapm) ; Create a mask for the dnap bit
800 sldi r0, r0, 32 ; Shift to the top half
801 ld r11,pfHID0(r30) ; Load the hid0 value
802 andc r11, r11, r0 ; Clear the dnap bit
803 isync
804 mtspr hid0,r11 ; Stuff it
805 mfspr r11,hid0 ; Get it
806 mfspr r11,hid0 ; Get it
807 mfspr r11,hid0 ; Get it
808 mfspr r11,hid0 ; Get it
809 mfspr r11,hid0 ; Get it
810 mfspr r11,hid0 ; Get it
811 isync
812
813 lis r0,(pcfValid|pcfLarge|pcfDedSeg)<<8 ; Set the valid bit, dedicated segment, and large page flags
814 ori r0,r0,(24<<8)|24 ; Add in the 16M page size
815 stw r0,lgpPcfg+(pcfSize*pcfLargePcfg)(0) ; Set the 16M primary large page configuration entry
816
817 blr
818
819;
820; Start up code for second processor or wake up from sleep
821;
822
823init970nb:
824 lis r0, hi16(dnapm) ; Create a mask for the dnap bit
825 sldi r0, r0, 32 ; Shift to the top half
826 ld r11,pfHID0(r30) ; Load the hid0 value
827 andc r11, r11, r0 ; Clear the dnap bit
828 isync
829 mtspr hid0,r11 ; Stuff it
830 mfspr r11,hid0 ; Get it
831 mfspr r11,hid0 ; Get it
832 mfspr r11,hid0 ; Get it
833 mfspr r11,hid0 ; Get it
834 mfspr r11,hid0 ; Get it
835 mfspr r11,hid0 ; Get it
836 isync
837
838 ld r20,pfHID1(r30) ; Get it
839 isync
840 mtspr hid1,r20 ; Stick it
841 mtspr hid1,r20 ; Stick it again
842 isync
843
844 ld r11,pfHID4(r30) ; Get it
845 sync
846 mtspr hid4,r11 ; Stick it
847 isync
848
849 lis r11,0xE000 ; Get the unlikeliest ESID possible
850 srdi r11,r11,1 ; Make 0x7FFFFFFFF0000000
851 slbie r11 ; Make sure the ERAT is cleared
852
853 ld r11,pfHID5(r30) ; Get it
854 mtspr hid5,r11 ; Set it
855 isync
856;
857; May have changed dcbz mode so kill icache
858;
859
860 eqv r13,r13,r13 ; Get a constant -1
861 mr r14,r20 ; Save HID1
862 rldimi r14,r13,54,9 ; Set force icbi match mode
863
864 li r11,0 ; Set start if ICBI range
865 isync
866 mtspr hid1,r14 ; Stick it
867 mtspr hid1,r14 ; Stick it again
868 isync
869
870inin970ki: icbi 0,r11 ; Kill I$
871 addi r11,r11,128 ; Next line
872 andis. r0,r11,1 ; Have we done them all?
873 beq++ inin970ki ; Not yet...
874
875 isync
876 mtspr hid1,r20 ; Stick it
877 mtspr hid1,r20 ; Stick it again
878 isync
879
880 blr ; Leave...
881
882
883
884; Unsupported Processors
885initUnsupported:
886 mtlr r2 ; Restore the return address
887 blr ; Return to the booter
888
889
890;
891; Processor to feature table
892
893; .align 2 - Always on word boundary
894; .long ptFilter - Mask of significant bits in the Version/Revision code
895; - NOTE: Always order from most restrictive to least restrictive matching
896; .short ptVersion - Version code from PVR. Always start with 0 which is default
897; .short ptRevision - Revision code from PVR. A zero value denotes the generic attributes if not specific
898; .long ptFeatures - Available features
899; .long ptCPUCap - Default value for _cpu_capabilities
900; .long ptPwrModes - Available power management features
901; .long ptPatch - Patch features
902; .long ptInitRout - Initilization routine. Can modify any of the other attributes.
903; .long ptRptdProc - Processor type reported
904; .long ptLineSize - Level 1 cache line size
905; .long ptl1iSize - Level 1 instruction cache size
906; .long ptl1dSize - Level 1 data cache size
907; .long ptPTEG - Size of PTEG
908; .long ptMaxVAddr - Maximum effective address
909; .long ptMaxPAddr - Maximum physical address
910;
911
912 .align 2
913processor_types:
914
915; 750CX (ver 2.x)
916
917 .align 2
918 .long 0xFFFF0F00 ; 2.x vers
919 .short PROCESSOR_VERSION_750
920 .short 0x0200
921 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2
922 .long kCache32 | kHasGraphicsOps | kHasStfiwx
923 .long 0
924 .long PatchExt32
925 .long init750CX
926 .long CPU_SUBTYPE_POWERPC_750
927 .long 32
928 .long 32*1024
929 .long 32*1024
930 .long 64
931 .long 52
932 .long 32
933
934; 750 (generic)
935
936 .align 2
937 .long 0xFFFF0000 ; All revisions
938 .short PROCESSOR_VERSION_750
939 .short 0
940 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2
941 .long kCache32 | kHasGraphicsOps | kHasStfiwx
942 .long 0
943 .long PatchExt32
944 .long init750
945 .long CPU_SUBTYPE_POWERPC_750
946 .long 32
947 .long 32*1024
948 .long 32*1024
949 .long 64
950 .long 52
951 .long 32
952
953; 750FX (ver 1.x)
954
955 .align 2
956 .long 0xFFFF0F00 ; 1.x vers
957 .short PROCESSOR_VERSION_750FX
958 .short 0x0100
959 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pf32Byte | pfL2
960 .long kCache32 | kHasGraphicsOps | kHasStfiwx
961 .long pmDualPLL
962 .long PatchExt32
963 .long init750FX
964 .long CPU_SUBTYPE_POWERPC_750
965 .long 32
966 .long 32*1024
967 .long 32*1024
968 .long 64
969 .long 52
970 .long 32
971
972; 750FX (generic)
973
974 .align 2
975 .long 0xFFFF0000 ; All revisions
976 .short PROCESSOR_VERSION_750FX
977 .short 0
978 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pf32Byte | pfL2
979 .long kCache32 | kHasGraphicsOps | kHasStfiwx
980 .long pmDualPLL | pmDPLLVmin
981 .long PatchExt32
982 .long init750FXV2
983 .long CPU_SUBTYPE_POWERPC_750
984 .long 32
985 .long 32*1024
986 .long 32*1024
987 .long 64
988 .long 52
989 .long 32
990
991; 7400 (ver 2.0 - ver 2.7)
992
993 .align 2
994 .long 0xFFFFFFF8 ; ver 2.0 - 2.7
995 .short PROCESSOR_VERSION_7400
996 .short 0x0200
997 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
998 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
999 .long 0
1000 .long PatchExt32
1001 .long init7400v2_7
1002 .long CPU_SUBTYPE_POWERPC_7400
1003 .long 32
1004 .long 32*1024
1005 .long 32*1024
1006 .long 64
1007 .long 52
1008 .long 32
1009
1010; 7400 (generic)
1011
1012 .align 2
1013 .long 0xFFFF0000 ; All revisions
1014 .short PROCESSOR_VERSION_7400
1015 .short 0
1016 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1017 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1018 .long 0
1019 .long PatchExt32
1020 .long init7400
1021 .long CPU_SUBTYPE_POWERPC_7400
1022 .long 32
1023 .long 32*1024
1024 .long 32*1024
1025 .long 64
1026 .long 52
1027 .long 36
1028
1029; 7410 (ver 1.1)
1030
1031 .align 2
1032 .long 0xFFFFFFFF ; Exact match
1033 .short PROCESSOR_VERSION_7400
1034 .short 0x1101
1035 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1036 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1037 .long 0
1038 .long PatchExt32
1039 .long init7410
1040 .long CPU_SUBTYPE_POWERPC_7400
1041 .long 32
1042 .long 32*1024
1043 .long 32*1024
1044 .long 64
1045 .long 52
1046 .long 36
1047
1048; 7410 (generic)
1049
1050 .align 2
1051 .long 0xFFFF0000 ; All other revisions
1052 .short PROCESSOR_VERSION_7410
1053 .short 0
1054 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1055 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1056 .long 0
1057 .long PatchExt32
1058 .long init7410
1059 .long CPU_SUBTYPE_POWERPC_7400
1060 .long 32
1061 .long 32*1024
1062 .long 32*1024
1063 .long 64
1064 .long 52
1065 .long 36
1066
1067; 7450 (ver 1.xx)
1068
1069 .align 2
1070 .long 0xFFFFFF00 ; Just revisions 1.xx
1071 .short PROCESSOR_VERSION_7450
1072 .short 0x0100
1073 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1074 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1075 .long 0
1076 .long PatchExt32
1077 .long init7450
1078 .long CPU_SUBTYPE_POWERPC_7450
1079 .long 32
1080 .long 32*1024
1081 .long 32*1024
1082 .long 64
1083 .long 52
1084 .long 36
1085
1086; 7450 (2.0)
1087
1088 .align 2
1089 .long 0xFFFFFFFF ; Just revision 2.0
1090 .short PROCESSOR_VERSION_7450
1091 .short 0x0200
1092 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1093 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1094 .long 0
1095 .long PatchExt32
1096 .long init7450
1097 .long CPU_SUBTYPE_POWERPC_7450
1098 .long 32
1099 .long 32*1024
1100 .long 32*1024
1101 .long 64
1102 .long 52
1103 .long 36
1104
1105; 7450 (2.1)
1106
1107 .align 2
1108 .long 0xFFFF0000 ; All other revisions
1109 .short PROCESSOR_VERSION_7450
1110 .short 0
1111 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1112 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1113 .long 0
1114 .long PatchExt32
1115 .long init7450
1116 .long CPU_SUBTYPE_POWERPC_7450
1117 .long 32
1118 .long 32*1024
1119 .long 32*1024
1120 .long 64
1121 .long 52
1122 .long 36
1123
1124; 7455 (1.xx) Just like 7450 2.0
1125
1126 .align 2
1127 .long 0xFFFFFF00 ; Just revisions 1.xx
1128 .short PROCESSOR_VERSION_7455
1129 .short 0x0100
1130 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1131 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1132 .long 0
1133 .long PatchExt32
1134 .long init745X
1135 .long CPU_SUBTYPE_POWERPC_7450
1136 .long 32
1137 .long 32*1024
1138 .long 32*1024
1139 .long 64
1140 .long 52
1141 .long 36
1142
1143; 7455 (2.0)
1144
1145 .align 2
1146 .long 0xFFFFFFFF ; Just revision 2.0
1147 .short PROCESSOR_VERSION_7455
1148 .short 0x0200
1149 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1150 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1151 .long 0
1152 .long PatchExt32
1153 .long init745X
1154 .long CPU_SUBTYPE_POWERPC_7450
1155 .long 32
1156 .long 32*1024
1157 .long 32*1024
1158 .long 64
1159 .long 52
1160 .long 36
1161
1162; 7455 (2.1)
1163
1164 .align 2
1165 .long 0xFFFF0000 ; All other revisions
1166 .short PROCESSOR_VERSION_7455
1167 .short 0
1168 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1169 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1170 .long 0
1171 .long PatchExt32
1172 .long init745X
1173 .long CPU_SUBTYPE_POWERPC_7450
1174 .long 32
1175 .long 32*1024
1176 .long 32*1024
1177 .long 64
1178 .long 52
1179 .long 36
1180
1181; 7457
1182
1183 .align 2
1184 .long 0xFFFF0000 ; All revisions
1185 .short PROCESSOR_VERSION_7457
1186 .short 0
1187 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1188 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1189 .long 0
1190 .long PatchExt32
1191 .long init745X
1192 .long CPU_SUBTYPE_POWERPC_7450
1193 .long 32
1194 .long 32*1024
1195 .long 32*1024
1196 .long 64
1197 .long 52
1198 .long 36
1199
1200; 7447A
1201
1202 .align 2
1203 .long 0xFFFF0000 ; All revisions
1204 .short PROCESSOR_VERSION_7447A
1205 .short 0
1206 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1207 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1208 .long pmDFS
1209 .long PatchExt32
1210 .long init745X
1211 .long CPU_SUBTYPE_POWERPC_7450
1212 .long 32
1213 .long 32*1024
1214 .long 32*1024
1215 .long 64
1216 .long 52
1217 .long 36
1218
1219; 970
1220
1221 .align 2
1222 .long 0xFFFF0000 ; All versions so far
1223 .short PROCESSOR_VERSION_970
1224 .short 0
1225 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pf128Byte | pf64Bit | pfL2 | pfSCOMFixUp
1226 .long kHasAltivec | k64Bit | kCache128 | kDataStreamsAvailable | kDcbtStreamsRecommended | kDcbtStreamsAvailable | kHasGraphicsOps | kHasStfiwx | kHasFsqrt
1227 .long 0
1228 .long PatchLwsync
1229 .long init970
1230 .long CPU_SUBTYPE_POWERPC_970
1231 .long 128
1232 .long 64*1024
1233 .long 32*1024
1234 .long 128
1235 .long 65
1236 .long 42
1237
1238; 970FX
1239
1240 .align 2
1241 .long 0xFFFF0000 ; All versions so far
1242 .short PROCESSOR_VERSION_970FX
1243 .short 0
1244 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pf128Byte | pf64Bit | pfL2
1245 .long kHasAltivec | k64Bit | kCache128 | kDataStreamsAvailable | kDcbtStreamsRecommended | kDcbtStreamsAvailable | kHasGraphicsOps | kHasStfiwx | kHasFsqrt
1246 .long pmPowerTune
1247 .long PatchLwsync
1248 .long init970
1249 .long CPU_SUBTYPE_POWERPC_970
1250 .long 128
1251 .long 64*1024
1252 .long 32*1024
1253 .long 128
1254 .long 65
1255 .long 42
1256
1257
1258; All other processors are not supported
1259
1260 .align 2
1261 .long 0x00000000 ; Matches everything
1262 .short 0
1263 .short 0
1264 .long pfFloat | pf32Byte
1265 .long kCache32 | kHasGraphicsOps | kHasStfiwx
1266 .long 0
1267 .long PatchExt32
1268 .long initUnsupported
1269 .long CPU_SUBTYPE_POWERPC_ALL
1270 .long 32
1271 .long 32*1024
1272 .long 32*1024
1273 .long 64
1274 .long 52
1275 .long 32
1276
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