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1c79356b 1/*
39236c6e 2 * Copyright (c) 2000-2012 Apple Inc. All rights reserved.
1c79356b 3 *
2d21ac55 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
1c79356b 5 *
2d21ac55
A
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
8f6c56a5 14 *
2d21ac55
A
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5
A
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55
A
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
8f6c56a5 25 *
2d21ac55 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
1c79356b
A
27 */
28/*
29 * @OSF_COPYRIGHT@
30 *
31 */
32
33#ifndef I386_CPU_DATA
34#define I386_CPU_DATA
35
1c79356b
A
36#include <mach_assert.h>
37
1c79356b
A
38#include <kern/assert.h>
39#include <kern/kern_types.h>
b0d623f7 40#include <kern/queue.h>
91447636 41#include <kern/processor.h>
0c530ab8 42#include <kern/pms.h>
55e303ae 43#include <pexpert/pexpert.h>
0c530ab8 44#include <mach/i386/thread_status.h>
b0d623f7 45#include <mach/i386/vm_param.h>
fe8ab488 46#include <i386/locks.h>
6d2010ae 47#include <i386/rtclock_protos.h>
0c530ab8 48#include <i386/pmCPU.h>
2d21ac55 49#include <i386/cpu_topology.h>
5ba3f43e 50#include <i386/seg.h>
2d21ac55 51
b0d623f7 52#if CONFIG_VMX
2d21ac55 53#include <i386/vmx/vmx_cpu.h>
b0d623f7 54#endif
91447636 55
5ba3f43e
A
56#if MONOTONIC
57#include <machine/monotonic.h>
58#endif /* MONOTONIC */
59
6d2010ae
A
60#include <machine/pal_routines.h>
61
91447636
A
62/*
63 * Data structures referenced (anonymously) from per-cpu data:
64 */
91447636 65struct cpu_cons_buffer;
0c530ab8 66struct cpu_desc_table;
2d21ac55 67struct mca_state;
fe8ab488 68struct prngContext;
91447636 69
91447636
A
70/*
71 * Data structures embedded in per-cpu data:
72 */
73typedef struct rtclock_timer {
6d2010ae 74 mpqueue_head_t queue;
c910b4d9 75 uint64_t deadline;
6d2010ae 76 uint64_t when_set;
c910b4d9 77 boolean_t has_expired;
91447636
A
78} rtclock_timer_t;
79
91447636 80typedef struct {
5c9f4661
A
81 /* The 'u' suffixed fields store the double-mapped descriptor addresses */
82 struct x86_64_tss *cdi_ktssu;
83 struct x86_64_tss *cdi_ktssb;
84 x86_64_desc_register_t cdi_gdtu;
85 x86_64_desc_register_t cdi_gdtb;
86 x86_64_desc_register_t cdi_idtu;
87 x86_64_desc_register_t cdi_idtb;
88 struct fake_descriptor *cdi_ldtu;
89 struct fake_descriptor *cdi_ldtb;
90 vm_offset_t cdi_sstku;
91 vm_offset_t cdi_sstkb;
b0d623f7
A
92} cpu_desc_index_t;
93
94typedef enum {
95 TASK_MAP_32BIT, /* 32-bit user, compatibility mode */
96 TASK_MAP_64BIT, /* 64-bit user thread, shared space */
97} task_map_t;
98
b0d623f7 99
0c530ab8
A
100/*
101 * This structure is used on entry into the (uber-)kernel on syscall from
102 * a 64-bit user. It contains the address of the machine state save area
103 * for the current thread and a temporary place to save the user's rsp
104 * before loading this address into rsp.
105 */
106typedef struct {
107 addr64_t cu_isf; /* thread->pcb->iss.isf */
108 uint64_t cu_tmp; /* temporary scratch */
6d2010ae 109 addr64_t cu_user_gs_base;
0c530ab8 110} cpu_uber_t;
91447636 111
6d2010ae
A
112typedef uint16_t pcid_t;
113typedef uint8_t pcid_ref_t;
bd504ef0
A
114
115#define CPU_RTIME_BINS (12)
116#define CPU_ITIME_BINS (CPU_RTIME_BINS)
117
5c9f4661 118#define MAXPLFRAMES (16)
39037602
A
119typedef struct {
120 boolean_t pltype;
121 int plevel;
122 uint64_t plbt[MAXPLFRAMES];
123} plrecord_t;
124
91447636
A
125/*
126 * Per-cpu data.
127 *
128 * Each processor has a per-cpu data area which is dereferenced through the
129 * current_cpu_datap() macro. For speed, the %gs segment is based here, and
130 * using this, inlines provides single-instruction access to frequently used
131 * members - such as get_cpu_number()/cpu_number(), and get_active_thread()/
132 * current_thread().
133 *
134 * Cpu data owned by another processor can be accessed using the
135 * cpu_datap(cpu_number) macro which uses the cpu_data_ptr[] array of per-cpu
136 * pointers.
137 */
5c9f4661
A
138typedef struct {
139 pcid_t cpu_pcid_free_hint;
140#define PMAP_PCID_MAX_PCID (0x800)
141 pcid_ref_t cpu_pcid_refcounts[PMAP_PCID_MAX_PCID];
142 pmap_t cpu_pcid_last_pmap_dispatched[PMAP_PCID_MAX_PCID];
143} pcid_cdata_t;
144
91447636
A
145typedef struct cpu_data
146{
6d2010ae
A
147 struct pal_cpu_data cpu_pal_data; /* PAL-specific data */
148#define cpu_pd cpu_pal_data /* convenience alias */
91447636
A
149 struct cpu_data *cpu_this; /* pointer to myself */
150 thread_t cpu_active_thread;
39236c6e
A
151 thread_t cpu_nthread;
152 volatile int cpu_preemption_level;
6d2010ae 153 int cpu_number; /* Logical CPU */
0c530ab8
A
154 void *cpu_int_state; /* interrupt state */
155 vm_offset_t cpu_active_stack; /* kernel stack base */
156 vm_offset_t cpu_kernel_stack; /* kernel stack top */
91447636 157 vm_offset_t cpu_int_stack_top;
91447636 158 int cpu_interrupt_level;
39236c6e
A
159 volatile int cpu_signals; /* IPI events */
160 volatile int cpu_prior_signals; /* Last set of events,
060df5ea
A
161 * debugging
162 */
91447636 163 ast_t cpu_pending_ast;
bd504ef0 164 volatile int cpu_running;
5ba3f43e 165#if !MONOTONIC
bd504ef0 166 boolean_t cpu_fixed_pmcs_enabled;
5ba3f43e 167#endif /* !MONOTONIC */
0c530ab8 168 rtclock_timer_t rtclock_timer;
5ba3f43e 169 uint64_t quantum_timer_deadline;
6d2010ae
A
170 volatile addr64_t cpu_active_cr3 __attribute((aligned(64)));
171 union {
172 volatile uint32_t cpu_tlb_invalid;
173 struct {
174 volatile uint16_t cpu_tlb_invalid_local;
175 volatile uint16_t cpu_tlb_invalid_global;
176 };
177 };
178 volatile task_map_t cpu_task_map;
b0d623f7 179 volatile addr64_t cpu_task_cr3;
2d21ac55 180 addr64_t cpu_kernel_cr3;
a39ff7e2 181 volatile addr64_t cpu_ucr3;
39037602 182 boolean_t cpu_pagezero_mapped;
0c530ab8 183 cpu_uber_t cpu_uber;
a39ff7e2 184/* Double-mapped per-CPU exception stack address */
5c9f4661 185 uintptr_t cd_estack;
d26ffc64 186 int cpu_xstate;
a39ff7e2
A
187/* Address of shadowed, partially mirrored CPU data structures located
188 * in the double mapped PML4
189 */
5c9f4661 190 void *cd_shadow;
91447636 191 struct processor *cpu_processor;
b0d623f7 192#if NCOPY_WINDOWS > 0
91447636 193 struct cpu_pmap *cpu_pmap;
b0d623f7 194#endif
5c9f4661 195 struct real_descriptor *cpu_ldtp;
a39ff7e2 196 struct cpu_desc_table *cpu_desc_tablep;
91447636 197 cpu_desc_index_t cpu_desc_index;
0c530ab8 198 int cpu_ldt;
b0d623f7 199#if NCOPY_WINDOWS > 0
2d21ac55
A
200 vm_offset_t cpu_copywindow_base;
201 uint64_t *cpu_copywindow_pdp;
202
203 vm_offset_t cpu_physwindow_base;
204 uint64_t *cpu_physwindow_ptep;
b0d623f7
A
205#endif
206
6d2010ae
A
207#define HWINTCNT_SIZE 256
208 uint32_t cpu_hwIntCnt[HWINTCNT_SIZE]; /* Interrupt counts */
bd504ef0 209 uint64_t cpu_hwIntpexits[HWINTCNT_SIZE];
0c530ab8 210 uint64_t cpu_dr7; /* debug control register */
2d21ac55 211 uint64_t cpu_int_event_time; /* intr entry/exit time */
6d2010ae 212 pal_rtc_nanotime_t *cpu_nanotime; /* Nanotime info */
39236c6e
A
213#if KPC
214 /* double-buffered performance counter data */
215 uint64_t *cpu_kpc_buf[2];
216 /* PMC shadow and reload value buffers */
217 uint64_t *cpu_kpc_shadow;
218 uint64_t *cpu_kpc_reload;
219#endif
5ba3f43e
A
220#if MONOTONIC
221 struct mt_cpu cpu_monotonic;
222#endif /* MONOTONIC */
6d2010ae
A
223 uint32_t cpu_pmap_pcid_enabled;
224 pcid_t cpu_active_pcid;
225 pcid_t cpu_last_pcid;
39037602 226 pcid_t cpu_kernel_pcid;
6d2010ae
A
227 volatile pcid_ref_t *cpu_pmap_pcid_coherentp;
228 volatile pcid_ref_t *cpu_pmap_pcid_coherentp_kernel;
5c9f4661 229 pcid_cdata_t *cpu_pcid_data;
6d2010ae
A
230#ifdef PCID_STATS
231 uint64_t cpu_pmap_pcid_flushes;
232 uint64_t cpu_pmap_pcid_preserves;
233#endif
4b17d6b6
A
234 uint64_t cpu_aperf;
235 uint64_t cpu_mperf;
236 uint64_t cpu_c3res;
237 uint64_t cpu_c6res;
238 uint64_t cpu_c7res;
239 uint64_t cpu_itime_total;
240 uint64_t cpu_rtime_total;
4b17d6b6 241 uint64_t cpu_ixtime;
bd504ef0 242 uint64_t cpu_idle_exits;
5ba3f43e
A
243 uint64_t cpu_rtimes[CPU_RTIME_BINS];
244 uint64_t cpu_itimes[CPU_ITIME_BINS];
245#if !MONOTONIC
246 uint64_t cpu_cur_insns;
247 uint64_t cpu_cur_ucc;
248 uint64_t cpu_cur_urc;
249#endif /* !MONOTONIC */
a1c7dba1 250 uint64_t cpu_gpmcs[4];
6d2010ae
A
251 uint64_t cpu_max_observed_int_latency;
252 int cpu_max_observed_int_latency_vector;
39236c6e 253 volatile boolean_t cpu_NMI_acknowledged;
060df5ea 254 uint64_t debugger_entry_time;
bd504ef0 255 uint64_t debugger_ipi_time;
060df5ea
A
256 /* A separate nested interrupt stack flag, to account
257 * for non-nested interrupts arriving while on the interrupt stack
258 * Currently only occurs when AICPM enables interrupts on the
259 * interrupt stack during processor offlining.
260 */
261 uint32_t cpu_nested_istack;
262 uint32_t cpu_nested_istack_events;
6d2010ae
A
263 x86_saved_state64_t *cpu_fatal_trap_state;
264 x86_saved_state64_t *cpu_post_fatal_trap_state;
bd504ef0
A
265#if CONFIG_VMX
266 vmx_cpu_t cpu_vmx; /* wonderful world of virtualization */
267#endif
268#if CONFIG_MCA
269 struct mca_state *cpu_mca_state; /* State at MC fault */
270#endif
fe8ab488 271 struct prngContext *cpu_prng; /* PRNG's context */
bd504ef0
A
272 int cpu_type;
273 int cpu_subtype;
274 int cpu_threadtype;
275 boolean_t cpu_iflag;
276 boolean_t cpu_boot_complete;
39037602 277 int cpu_hibernate;
5c9f4661 278#define MAX_PREEMPTION_RECORDS (8)
39037602
A
279#if DEVELOPMENT || DEBUG
280 int cpu_plri;
281 plrecord_t plrecords[MAX_PREEMPTION_RECORDS];
5c9f4661 282#endif
5c9f4661
A
283 void *cpu_console_buf;
284 struct x86_lcpu lcpu;
285 int cpu_phys_number; /* Physical CPU */
286 cpu_id_t cpu_id; /* Platform Expert */
287#if DEBUG
288 uint64_t cpu_entry_cr3;
289 uint64_t cpu_exit_cr3;
290 uint64_t cpu_pcid_last_cr3;
39037602 291#endif
55e303ae 292} cpu_data_t;
1c79356b 293
91447636 294extern cpu_data_t *cpu_data_ptr[];
9bccf70c 295
55e303ae 296/* Macro to generate inline bodies to retrieve per-cpu data fields. */
39236c6e
A
297#if defined(__clang__)
298#define GS_RELATIVE volatile __attribute__((address_space(256)))
299#ifndef offsetof
300#define offsetof(TYPE,MEMBER) __builtin_offsetof(TYPE,MEMBER)
301#endif
302
303#define CPU_DATA_GET(member,type) \
304 cpu_data_t GS_RELATIVE *cpu_data = \
305 (cpu_data_t GS_RELATIVE *)0UL; \
306 type ret; \
307 ret = cpu_data->member; \
308 return ret;
309
310#define CPU_DATA_GET_INDEX(member,index,type) \
311 cpu_data_t GS_RELATIVE *cpu_data = \
312 (cpu_data_t GS_RELATIVE *)0UL; \
313 type ret; \
314 ret = cpu_data->member[index]; \
315 return ret;
316
317#define CPU_DATA_SET(member,value) \
318 cpu_data_t GS_RELATIVE *cpu_data = \
319 (cpu_data_t GS_RELATIVE *)0UL; \
320 cpu_data->member = value;
321
322#define CPU_DATA_XCHG(member,value,type) \
323 cpu_data_t GS_RELATIVE *cpu_data = \
324 (cpu_data_t GS_RELATIVE *)0UL; \
325 type ret; \
326 ret = cpu_data->member; \
327 cpu_data->member = value; \
328 return ret;
329
330#else /* !defined(__clang__) */
331
2d21ac55 332#ifndef offsetof
55e303ae 333#define offsetof(TYPE,MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
2d21ac55 334#endif /* offsetof */
91447636 335#define CPU_DATA_GET(member,type) \
55e303ae 336 type ret; \
b0d623f7 337 __asm__ volatile ("mov %%gs:%P1,%0" \
55e303ae 338 : "=r" (ret) \
91447636 339 : "i" (offsetof(cpu_data_t,member))); \
55e303ae 340 return ret;
9bccf70c 341
6d2010ae
A
342#define CPU_DATA_GET_INDEX(member,index,type) \
343 type ret; \
344 __asm__ volatile ("mov %%gs:(%1),%0" \
345 : "=r" (ret) \
346 : "r" (offsetof(cpu_data_t,member[index]))); \
347 return ret;
348
349#define CPU_DATA_SET(member,value) \
350 __asm__ volatile ("mov %0,%%gs:%P1" \
351 : \
352 : "r" (value), "i" (offsetof(cpu_data_t,member)));
39236c6e 353
6d2010ae
A
354#define CPU_DATA_XCHG(member,value,type) \
355 type ret; \
356 __asm__ volatile ("xchg %0,%%gs:%P1" \
357 : "=r" (ret) \
358 : "i" (offsetof(cpu_data_t,member)), "0" (value)); \
359 return ret;
360
39236c6e
A
361#endif /* !defined(__clang__) */
362
1c79356b
A
363/*
364 * Everyone within the osfmk part of the kernel can use the fast
365 * inline versions of these routines. Everyone outside, must call
366 * the real thing,
367 */
91447636
A
368static inline thread_t
369get_active_thread(void)
1c79356b 370{
91447636 371 CPU_DATA_GET(cpu_active_thread,thread_t)
1c79356b 372}
91447636
A
373#define current_thread_fast() get_active_thread()
374#define current_thread() current_thread_fast()
1c79356b 375
b0d623f7 376#define cpu_mode_is64bit() TRUE
0c530ab8 377
91447636
A
378static inline int
379get_preemption_level(void)
1c79356b 380{
91447636 381 CPU_DATA_GET(cpu_preemption_level,int)
55e303ae 382}
91447636 383static inline int
91447636 384get_interrupt_level(void)
55e303ae 385{
91447636 386 CPU_DATA_GET(cpu_interrupt_level,int)
55e303ae 387}
91447636
A
388static inline int
389get_cpu_number(void)
55e303ae
A
390{
391 CPU_DATA_GET(cpu_number,int)
392}
91447636
A
393static inline int
394get_cpu_phys_number(void)
55e303ae
A
395{
396 CPU_DATA_GET(cpu_phys_number,int)
1c79356b 397}
1c79356b 398
39037602
A
399static inline cpu_data_t *
400current_cpu_datap(void) {
401 CPU_DATA_GET(cpu_this, cpu_data_t *);
402}
403
404/*
405 * Facility to diagnose preemption-level imbalances, which are otherwise
406 * challenging to debug. On each operation that enables or disables preemption,
407 * we record a backtrace into a per-CPU ring buffer, along with the current
408 * preemption level and operation type. Thus, if an imbalance is observed,
409 * one can examine these per-CPU records to determine which codepath failed
410 * to re-enable preemption, enabled premption without a corresponding
411 * disablement etc. The backtracer determines which stack is currently active,
412 * and uses that to perform bounds checks on unterminated stacks.
413 * To enable, sysctl -w machdep.pltrace=1 on DEVELOPMENT or DEBUG kernels (DRK '15)
414 * The bounds check currently doesn't account for non-default thread stack sizes.
415 */
416#if DEVELOPMENT || DEBUG
417static inline void pltrace_bt(uint64_t *rets, int maxframes, uint64_t stacklo, uint64_t stackhi) {
418 uint64_t *cfp = (uint64_t *) __builtin_frame_address(0);
419 int plbtf;
420
421 assert(stacklo !=0 && stackhi !=0);
422
423 for (plbtf = 0; plbtf < maxframes; plbtf++) {
424 if (((uint64_t)cfp == 0) || (((uint64_t)cfp < stacklo) || ((uint64_t)cfp > stackhi))) {
425 rets[plbtf] = 0;
426 continue;
427 }
428 rets[plbtf] = *(cfp + 1);
429 cfp = (uint64_t *) (*cfp);
430 }
431}
432
433
434extern uint32_t low_intstack[]; /* bottom */
435extern uint32_t low_eintstack[]; /* top */
436extern char mp_slave_stack[PAGE_SIZE];
437
438static inline void pltrace_internal(boolean_t enable) {
439 cpu_data_t *cdata = current_cpu_datap();
440 int cpli = cdata->cpu_preemption_level;
441 int cplrecord = cdata->cpu_plri;
442 uint64_t kstackb, kstackt, *plbts;
443
444 assert(cpli >= 0);
445
446 cdata->plrecords[cplrecord].pltype = enable;
447 cdata->plrecords[cplrecord].plevel = cpli;
448
449 plbts = &cdata->plrecords[cplrecord].plbt[0];
450
451 cplrecord++;
452
453 if (cplrecord >= MAX_PREEMPTION_RECORDS) {
454 cplrecord = 0;
455 }
456
457 cdata->cpu_plri = cplrecord;
458 /* Obtain the 'current' program counter, initial backtrace
459 * element. This will also indicate if we were unable to
460 * trace further up the stack for some reason
461 */
462 __asm__ volatile("leaq 1f(%%rip), %%rax; mov %%rax, %0\n1:"
463 : "=m" (plbts[0])
464 :
465 : "rax");
466
467
468 thread_t cplthread = cdata->cpu_active_thread;
469 if (cplthread) {
470 uintptr_t csp;
471 __asm__ __volatile__ ("movq %%rsp, %0": "=r" (csp):);
472 /* Determine which stack we're on to populate stack bounds.
473 * We don't need to trace across stack boundaries for this
474 * routine.
475 */
476 kstackb = cdata->cpu_active_stack;
477 kstackt = kstackb + KERNEL_STACK_SIZE;
478 if (csp < kstackb || csp > kstackt) {
479 kstackt = cdata->cpu_kernel_stack;
480 kstackb = kstackb - KERNEL_STACK_SIZE;
481 if (csp < kstackb || csp > kstackt) {
482 kstackt = cdata->cpu_int_stack_top;
483 kstackb = kstackt - INTSTACK_SIZE;
484 if (csp < kstackb || csp > kstackt) {
485 kstackt = (uintptr_t)low_eintstack;
486 kstackb = (uintptr_t)low_eintstack - INTSTACK_SIZE;
487 if (csp < kstackb || csp > kstackt) {
488 kstackb = (uintptr_t) mp_slave_stack;
489 kstackt = (uintptr_t) mp_slave_stack + PAGE_SIZE;
490 }
491 }
492 }
493 }
494
495 if (kstackb) {
496 pltrace_bt(&plbts[1], MAXPLFRAMES - 1, kstackb, kstackt);
497 }
498 }
499}
500
501extern int plctrace_enabled;
502#endif /* DEVELOPMENT || DEBUG */
503
504static inline void pltrace(boolean_t plenable) {
505#if DEVELOPMENT || DEBUG
506 if (__improbable(plctrace_enabled != 0)) {
507 pltrace_internal(plenable);
508 }
509#else
510 (void)plenable;
511#endif
512}
b0d623f7 513
91447636 514static inline void
39037602
A
515disable_preemption_internal(void) {
516 assert(get_preemption_level() >= 0);
517
39236c6e
A
518#if defined(__clang__)
519 cpu_data_t GS_RELATIVE *cpu_data = (cpu_data_t GS_RELATIVE *)0UL;
520 cpu_data->cpu_preemption_level++;
521#else
91447636 522 __asm__ volatile ("incl %%gs:%P0"
39037602
A
523 :
524 : "i" (offsetof(cpu_data_t, cpu_preemption_level)));
39236c6e 525#endif
39037602 526 pltrace(FALSE);
91447636 527}
1c79356b 528
91447636 529static inline void
39037602 530enable_preemption_internal(void) {
55e303ae 531 assert(get_preemption_level() > 0);
39037602 532 pltrace(TRUE);
39236c6e
A
533#if defined(__clang__)
534 cpu_data_t GS_RELATIVE *cpu_data = (cpu_data_t GS_RELATIVE *)0UL;
535 if (0 == --cpu_data->cpu_preemption_level)
536 kernel_preempt_check();
537#else
91447636
A
538 __asm__ volatile ("decl %%gs:%P0 \n\t"
539 "jne 1f \n\t"
540 "call _kernel_preempt_check \n\t"
541 "1:"
1c79356b 542 : /* no outputs */
91447636
A
543 : "i" (offsetof(cpu_data_t, cpu_preemption_level))
544 : "eax", "ecx", "edx", "cc", "memory");
39236c6e 545#endif
1c79356b
A
546}
547
91447636
A
548static inline void
549enable_preemption_no_check(void)
1c79356b 550{
1c79356b 551 assert(get_preemption_level() > 0);
1c79356b 552
39037602 553 pltrace(TRUE);
39236c6e
A
554#if defined(__clang__)
555 cpu_data_t GS_RELATIVE *cpu_data = (cpu_data_t GS_RELATIVE *)0UL;
556 cpu_data->cpu_preemption_level--;
557#else
91447636 558 __asm__ volatile ("decl %%gs:%P0"
1c79356b 559 : /* no outputs */
91447636 560 : "i" (offsetof(cpu_data_t, cpu_preemption_level))
1c79356b 561 : "cc", "memory");
39236c6e 562#endif
1c79356b
A
563}
564
39037602
A
565static inline void
566_enable_preemption_no_check(void) {
567 enable_preemption_no_check();
568}
569
91447636
A
570static inline void
571mp_disable_preemption(void)
1c79356b 572{
39037602 573 disable_preemption_internal();
1c79356b
A
574}
575
91447636 576static inline void
39037602 577_mp_disable_preemption(void)
1c79356b 578{
39037602 579 disable_preemption_internal();
1c79356b
A
580}
581
91447636 582static inline void
39037602 583mp_enable_preemption(void)
1c79356b 584{
39037602
A
585 enable_preemption_internal();
586}
587
588static inline void
589_mp_enable_preemption(void) {
590 enable_preemption_internal();
591}
592
593static inline void
594mp_enable_preemption_no_check(void) {
1c79356b 595 enable_preemption_no_check();
1c79356b
A
596}
597
39037602
A
598static inline void
599_mp_enable_preemption_no_check(void) {
600 enable_preemption_no_check();
91447636
A
601}
602
39037602
A
603#ifdef XNU_KERNEL_PRIVATE
604#define disable_preemption() disable_preemption_internal()
605#define enable_preemption() enable_preemption_internal()
606#define MACHINE_PREEMPTION_MACROS (1)
607#endif
608
91447636 609static inline cpu_data_t *
39037602 610cpu_datap(int cpu) {
91447636
A
611 return cpu_data_ptr[cpu];
612}
613
a39ff7e2
A
614static inline int
615cpu_is_running(int cpu) {
616 return ((cpu_datap(cpu) != NULL) && (cpu_datap(cpu)->cpu_running));
617}
618
5c9f4661
A
619#ifdef MACH_KERNEL_PRIVATE
620static inline cpu_data_t *
621cpu_shadowp(int cpu) {
622 return cpu_data_ptr[cpu]->cd_shadow;
623}
624
625#endif
91447636 626extern cpu_data_t *cpu_data_alloc(boolean_t is_boot_cpu);
316670eb 627extern void cpu_data_realloc(void);
1c79356b 628
1c79356b 629#endif /* I386_CPU_DATA */