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1c79356b 1/*
91447636 2 * Copyright (c) 2000-2004 Apple Computer, Inc. All rights reserved.
1c79356b 3 *
8ad349bb 4 * @APPLE_LICENSE_OSREFERENCE_HEADER_START@
1c79356b 5 *
8ad349bb
A		 6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the
10 * License may not be used to create, or enable the creation or
11 * redistribution of, unlawful or unlicensed copies of an Apple operating
12 * system, or to circumvent, violate, or enable the circumvention or
13 * violation of, any terms of an Apple operating system software license
14 * agreement.
15 *
16 * Please obtain a copy of the License at
17 * http://www.opensource.apple.com/apsl/ and read it before using this
18 * file.
19 *
20 * The Original Code and all software distributed under the License are
21 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
22 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
23 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
25 * Please see the License for the specific language governing rights and
26 * limitations under the License.
27 *
28 * @APPLE_LICENSE_OSREFERENCE_HEADER_END@
1c79356b
A		 29 */
30/*
31 * @OSF_COPYRIGHT@
32 */
43866e37
A		 33
34#define __APPLE_API_PRIVATE
35
1c79356b
A		 36#include <mach_kdb.h>
37#include <mach_kdp.h>
38#include <mach_kgdb.h>
39#include <ppc/asm.h>
40#include <ppc/proc_reg.h>
9bccf70c 41#include <ppc/spec_reg.h>
43866e37 42#include <machine/cpu_capabilities.h>
1c79356b
A		 43#include <mach/ppc/vm_param.h>
44#include <assym.s>
91447636
A		 45
46
47; Definitions of the processor type table format, which drives this code.
48; The table ("processor_types") is assembled in at the end of this file.
1c79356b 49
43866e37
A		 50#define ptFilter 0
51#define ptVersion 4
52#define ptRevision 6
53#define ptFeatures 8
54#define ptCPUCap 12
4a249263
A		 55#define ptPwrModes 16
56#define ptPatch 20
57#define ptInitRout 24
58#define ptRptdProc 28
483a1d10
A		 59#define ptLineSize 32
60#define ptl1iSize 36
61#define ptl1dSize 40
62#define ptPTEG 44
63#define ptMaxVAddr 48
64#define ptMaxPAddr 52
65#define ptSize 56
1c79356b 66
91447636
A		 67
68; We use cr2 for flags:
69
1c79356b
A		 70#define bootCPU 10
71#define firstInit 9
72#define firstBoot 8
0b4e3aa0 73
1c79356b
A		 74/*
75 * Interrupt and bootup stack for initial processor
76 */
77
78 .file "start.s"
79
1c79356b
A		 80/*
81 * All CPUs start here.
82 *
83 * This code is called from SecondaryLoader
84 *
85 * Various arguments are passed via a table:
55e303ae 86 * R3 = pointer to other startup parameters
1c79356b
A		 87 */
88 .text
55e303ae
A		 89
90ENTRY(resetPOR,TAG_NO_FRAME_USED)
91
92 li r12,0 ; Get a 0
93 stw r12,0xF0(0) ; Make sure the special flag is clear
94 mtmsrd r12 ; Make sure we are in 32-bit mode
95 isync ; Really make sure
96 lwz r3,0xF4(0) ; Get the boot_args pointer
97 b startJoin ; Join up...
98
99
1c79356b
A		 100ENTRY(_start_cpu,TAG_NO_FRAME_USED)
101 crclr bootCPU ; Set non-boot processor
102 crclr firstInit ; Set not first time init
91447636
A		 103 lwz r30,ppe_paddr(r3) ; Set current per_proc
104 lwz r28,ppe_paddr+4(r3) ; Set current per_proc
105 rlwinm r30,r30,0,1,0 ; Copy low 32 bits to top 32
106 rlwimi r30,r28,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
107 subi r29,r3,(ACT_PER_PROC-ppe_vaddr) ; Substract mact.PerProc offset
108 mr r3,r30 ; Set current per_proc
1c79356b
A		 109
110;
111; Note that we are just trying to get close. The real TB sync will take
112; place later. The value we are loading is set in two places. For the
113; main processor, it will be the TB at the last interrupt before we went
114; to sleep. For the others, it will be the time just before the main
115; processor woke us up.
116;
117
118 lwz r15,ruptStamp(r3) ; Get the timebase from the other processor
119 li r17,0 ; Clear this out
120 lwz r16,ruptStamp+4(r3) ; Get the timebase from the other processor
121 mtspr tbl,r17 ; Clear bottom so we do not tick
122 mtspr tbu,r15 ; Set top
123 mtspr tbl,r16 ; Then bottom again
1c79356b
A		 124 b allstart
125
126ENTRY(_start,TAG_NO_FRAME_USED)
127
55e303ae
A		 128startJoin:
129 mflr r2 ; Save the return address
91447636
A		 130 lis r28,hi16(EXT(PerProcTable)) ; Set PerProcTable
131 lis r30,hi16(EXT(BootProcInfo)) ; Set current per_proc
132 ori r28,r28,lo16(EXT(PerProcTable)) ; Set PerProcTable
133 ori r30,r30,lo16(EXT(BootProcInfo)) ; Set current per_proc
134 stw r30,ppe_paddr+4(r28) ; Set per_proc_entry
135 stw r30,ppe_vaddr(r28) ; Set per_proc_entry
136 subi r29,r28,(ACT_PER_PROC-ppe_vaddr) ; Substract mact.PerProc offset
1c79356b
A		 137 crset bootCPU ; Set boot processor
138
139 lwz r17,pfAvailable(r30) ; Get the available bits
140 rlwinm. r0,r17,0,pfValidb,pfValidb ; Have we initialized the feature flags yet?
141 crmove firstInit,cr0_eq ; Set if we are doing first time init
142 bne allstart ; Yeah, we must be waking up from sleep...
143
144;
145; Here is where we do any one time general low-level initialization
146
147 lis r20,HIGH_ADDR(fwdisplock) ; Get address of the firmware display lock
148 li r19,0 ; Zorch a register
149 ori r20,r20,LOW_ADDR(fwdisplock) ; Get address of the firmware display lock
150 stw r19,0(r20) ; Make sure the lock is free
151
43866e37
A		 152allstart:
153 mr r31,r3 ; Save away arguments
154
155 crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
156
91447636
A		 157 mtsprg 0,r30 ; Set per_proc paddr
158 mtsprg 1,r29 ; Set spr1
1c79356b 159
de355530 160 li r9,0 ; Clear out a register
de355530
A		 161 mtsprg 2,r9
162 mtsprg 3,r9
163
55e303ae
A		 164 li r7,MSR_VM_OFF ; Get real mode MSR
165 mtmsr r7 ; Set the real mode SRR
166 isync
167
1c79356b
A		 168 lis r26,hi16(processor_types) ; Point to processor table
169 ori r26,r26,lo16(processor_types) ; Other half
170 mfpvr r10 ; Get the PVR
171
172nextPVR: lwz r28,ptFilter(r26) ; Get the filter
173 lwz r27,ptVersion(r26) ; Get the version and revision codes
174 and r28,r10,r28 ; Throw away dont care bits
175 cmplw r27,r28 ; Is this the right set?
176 beq donePVR ; We have the right one...
177 addi r26,r26,ptSize ; Point to the next type
178 b nextPVR ; Check it out...
179
180donePVR: lwz r20,ptInitRout(r26) ; Grab the special init routine
181 mtlr r20 ; Setup to call the init
182
43866e37 183 bf firstBoot,notFirst ; Not first boot, go...
1c79356b
A		 184
185;
186; The following code just does a general initialization of the features just
187; after the initial first-time boot. This is not done after waking up or on
55e303ae
A		 188; any "secondary" processor. Just after the boot-processor init, we copy the
189; features to any possible per_proc.
1c79356b
A		 190;
191; We are just setting defaults. The specific initialization code will modify these
192; if necessary.
193;
55e303ae
A		 194 lis r18,hi16(EXT(_cpu_capabilities)) ; Get the address of _cpu_capabilities
195 ori r18,r18,lo16(EXT(_cpu_capabilities))
43866e37 196 lwz r17,ptCPUCap(r26) ; Get the default cpu capabilities
55e303ae 197 stw r17, 0(r18) ; Save the default value in _cpu_capabilities
1c79356b
A		 198
199 lwz r17,ptFeatures(r26) ; Pick up the features
200
55e303ae
A		 201 lwz r18,ptRptdProc(r26) ; Get the reported processor
202 sth r18,pfrptdProc(r30) ; Set the reported processor
1c79356b 203
4a249263
A		 204 lwz r13,ptPwrModes(r26) ; Get the supported power modes
205 stw r13,pfPowerModes(r30) ; Set the supported power modes
206
1c79356b
A		 207 lwz r13,ptLineSize(r26) ; Get the cache line size
208 sth r13,pflineSize(r30) ; Save it
209 lwz r13,ptl1iSize(r26) ; Get icache size
210 stw r13,pfl1iSize(r30) ; Save it
211 lwz r13,ptl1dSize(r26) ; Get dcache size
212 stw r13,pfl1dSize(r30) ; Save it
55e303ae
A		 213 lwz r13,ptPTEG(r26) ; Get PTEG size address
214 stw r13,pfPTEG(r30) ; Save it
215 lwz r13,ptMaxVAddr(r26) ; Get max virtual address
216 stw r13,pfMaxVAddr(r30) ; Save it
217 lwz r13,ptMaxPAddr(r26) ; Get max physical address
218 stw r13,pfMaxPAddr(r30) ; Save it
91447636
A		 219
220
221; Go through the patch table, changing performance sensitive kernel routines based on the
222; processor type or other things.
223
55e303ae
A		 224 lis r11,hi16(EXT(patch_table))
225 ori r11,r11,lo16(EXT(patch_table))
226 lwz r19,ptPatch(r26) ; Get ptPatch field
55e303ae
A		 227patch_loop:
228 lwz r16,patchType(r11) ; Load the patch type
229 lwz r15,patchValue(r11) ; Load the patch value
230 cmplwi cr1,r16,PATCH_FEATURE ; Is it a patch feature entry
91447636 231 cmplwi cr7,r16,PATCH_END_OF_TABLE ; end of table?
55e303ae
A		 232 and. r14,r15,r19 ; Is it set in the patch feature
233 crandc cr0_eq,cr1_eq,cr0_eq ; Do we have a match
91447636
A		 234 beq cr7,doOurInit ; end of table, Go do processor specific initialization
235 beq patch_apply ; proc feature matches, so patch memory
55e303ae
A		 236 cmplwi cr1,r16,PATCH_PROCESSOR ; Is it a patch processor entry
237 cmplw cr0,r15,r18 ; Check matching processor
238 crand cr0_eq,cr1_eq,cr0_eq ; Do we have a match
239 bne patch_skip ; No, skip patch memory
240patch_apply:
241 lwz r13,patchAddr(r11) ; Load the address to patch
242 lwz r14,patchData(r11) ; Load the patch data
243 stw r14,0(r13) ; Patch the location
244 dcbf 0,r13 ; Flush the old one
245 sync ; Make sure we see it all
246 icbi 0,r13 ; Flush the i-cache
247 isync ; Hang out
248 sync ; Hang out some more...
249patch_skip:
250 addi r11,r11,peSize ; Point to the next patch entry
91447636
A		 251 b patch_loop ; handle next
252
253
254; Additional processors join here after skipping above code.
1c79356b
A		 255
256notFirst: lwz r17,pfAvailable(r30) ; Get our features
1c79356b 257
55e303ae
A		 258doOurInit: mr. r20,r20 ; See if initialization routine
259 crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
260 bnelrl ; Do the initialization
261
262 ori r17,r17,lo16(pfValid) ; Set the valid bit
263 stw r17,pfAvailable(r30) ; Set the available features
264
91447636 265 rlwinm. r0,r17,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
de355530 266 mtsprg 2,r17 ; Remember the feature flags
55e303ae
A		 267
268 bne++ start64 ; Skip following if 64-bit...
269
270 mfspr r6,hid0 ; Get the HID0
271 rlwinm r6,r6,0,sleep+1,doze-1 ; Remove any vestiges of sleep
272 mtspr hid0,r6 ; Set the insominac HID0
273 isync
274
275; Clear the BAT registers
276
277 li r9,0 ; Clear out a register
278 sync
279 isync
280 mtdbatu 0,r9 ; Invalidate maps
281 mtdbatl 0,r9 ; Invalidate maps
282 mtdbatu 1,r9 ; Invalidate maps
283 mtdbatl 1,r9 ; Invalidate maps
284 mtdbatu 2,r9 ; Invalidate maps
285 mtdbatl 2,r9 ; Invalidate maps
286 mtdbatu 3,r9 ; Invalidate maps
287 mtdbatl 3,r9 ; Invalidate maps
288 sync
289 isync
290 mtibatu 0,r9 ; Invalidate maps
291 mtibatl 0,r9 ; Invalidate maps
292 mtibatu 1,r9 ; Invalidate maps
293 mtibatl 1,r9 ; Invalidate maps
294 mtibatu 2,r9 ; Invalidate maps
295 mtibatl 2,r9 ; Invalidate maps
296 mtibatu 3,r9 ; Invalidate maps
297 mtibatl 3,r9 ; Invalidate maps
298 sync
299 isync
300 b startcommon ; Go join up the common start routine
d7e50217 301
55e303ae
A		 302start64: lis r5,hi16(startcommon) ; Get top of address of continue point
303 mfspr r6,hid0 ; Get the HID0
304 ori r5,r5,lo16(startcommon) ; Get low of address of continue point
91447636 305 lis r9,hi16(MASK(MSR_HV)|MASK(MSR_SF)) ; ?
55e303ae 306 lis r20,hi16(dozem|napm|sleepm) ; Get mask of power saving features
91447636 307 li r7,MSR_VM_OFF ; Get real mode MSR
55e303ae
A		 308 sldi r9,r9,32 ; Slide into position
309 sldi r20,r20,32 ; Slide power stuff into position
310 or r9,r9,r7 ; Form initial MSR
311 andc r6,r6,r20 ; Remove any vestiges of sleep
312 isync
313 mtspr hid0,r6 ; Set the insominac HID0
314 mfspr r6,hid0 ; Get it
315 mfspr r6,hid0 ; Get it
316 mfspr r6,hid0 ; Get it
317 mfspr r6,hid0 ; Get it
318 mfspr r6,hid0 ; Get it
319 mfspr r6,hid0 ; Get it
320 isync
321 mtsrr0 r5 ; Set the continue point
322 mtsrr1 r9 ; Set our normal disabled MSR
323 rfid ; Tally ho...
324
325 .align 5
326
327startcommon:
1c79356b
A		 328 rlwinm. r0,r17,0,pfFloatb,pfFloatb ; See if there is floating point
329 beq- noFloat ; Nope, this is a really stupid machine...
330
331 li r0,MSR_VM_OFF|MASK(MSR_FP) ; Enable for floating point
332 mtmsr r0 /* Set the standard MSR values */
333 isync
334
335 lis r5,HIGH_ADDR(EXT(FloatInit)) /* Get top of floating point init value */
336 ori r5,r5,LOW_ADDR(EXT(FloatInit)) /* Slam bottom */
337 lfd f0,0(r5) /* Initialize FP0 */
338 fmr f1,f0 /* Ours in not */
339 fmr f2,f0 /* to wonder why, */
340 fmr f3,f0 /* ours is but to */
341 fmr f4,f0 /* do or die! */
342 fmr f5,f0
343 fmr f6,f0
344 fmr f7,f0
345 fmr f8,f0
346 fmr f9,f0
347 fmr f10,f0
348 fmr f11,f0
349 fmr f12,f0
350 fmr f13,f0
351 fmr f14,f0
352 fmr f15,f0
353 fmr f16,f0
354 fmr f17,f0
355 fmr f18,f0
356 fmr f19,f0
357 fmr f20,f0
358 fmr f21,f0
359 fmr f22,f0
360 fmr f23,f0
361 fmr f24,f0
362 fmr f25,f0
363 fmr f26,f0
364 fmr f27,f0
365 fmr f28,f0
366 fmr f29,f0
367 fmr f30,f0
368 fmr f31,f0
369
370 li r0, MSR_VM_OFF ; Turn off floating point
371 mtmsr r0
372 isync
373
374noFloat: rlwinm. r0,r17,0,pfAltivecb,pfAltivecb ; See if there is Altivec
375 beq- noVector ; Nope...
376
377 li r0,0 ; Clear out a register
378
379 lis r7,hi16(MSR_VEC_ON) ; Get real mode MSR + Altivec
380 ori r7,r7,lo16(MSR_VM_OFF) ; Get real mode MSR + Altivec
381 mtmsr r7 ; Set the real mode SRR */
382 isync ; Make sure it has happened
383
384 lis r5,hi16(EXT(QNaNbarbarian)) ; Altivec initializer
385 ori r5,r5,lo16(EXT(QNaNbarbarian)) ; Altivec initializer
386
387 mtspr vrsave,r0 ; Set that no VRs are used yet */
388
55e303ae
A		 389 vspltish v1,1 ; Turn on the non-Java bit and saturate
390 vspltisw v0,1 ; Turn on the saturate bit
391 vxor v1,v1,v0 ; Turn off saturate and leave non-Java set
1c79356b
A		 392 lvx v0,br0,r5 ; Initialize VR0
393 mtvscr v1 ; Clear the vector status register
394 vor v2,v0,v0 ; Copy into the next register
395 vor v1,v0,v0 ; Copy into the next register
396 vor v3,v0,v0 ; Copy into the next register
397 vor v4,v0,v0 ; Copy into the next register
398 vor v5,v0,v0 ; Copy into the next register
399 vor v6,v0,v0 ; Copy into the next register
400 vor v7,v0,v0 ; Copy into the next register
401 vor v8,v0,v0 ; Copy into the next register
402 vor v9,v0,v0 ; Copy into the next register
403 vor v10,v0,v0 ; Copy into the next register
404 vor v11,v0,v0 ; Copy into the next register
405 vor v12,v0,v0 ; Copy into the next register
406 vor v13,v0,v0 ; Copy into the next register
407 vor v14,v0,v0 ; Copy into the next register
408 vor v15,v0,v0 ; Copy into the next register
409 vor v16,v0,v0 ; Copy into the next register
410 vor v17,v0,v0 ; Copy into the next register
411 vor v18,v0,v0 ; Copy into the next register
412 vor v19,v0,v0 ; Copy into the next register
413 vor v20,v0,v0 ; Copy into the next register
414 vor v21,v0,v0 ; Copy into the next register
415 vor v22,v0,v0 ; Copy into the next register
416 vor v23,v0,v0 ; Copy into the next register
417 vor v24,v0,v0 ; Copy into the next register
418 vor v25,v0,v0 ; Copy into the next register
419 vor v26,v0,v0 ; Copy into the next register
420 vor v27,v0,v0 ; Copy into the next register
421 vor v28,v0,v0 ; Copy into the next register
422 vor v29,v0,v0 ; Copy into the next register
423 vor v30,v0,v0 ; Copy into the next register
424 vor v31,v0,v0 ; Copy into the next register
425
426 li r0, MSR_VM_OFF ; Turn off vectors
427 mtmsr r0
428 isync
429
91447636 430noVector:
1c79356b 431 bl EXT(cacheInit) ; Initializes all caches (including the TLB)
55e303ae 432
91447636
A		 433 bt bootCPU,run32
434
435 mfsprg r30,0 ; Phys per proc
3a60a9f5
A		 436 lwz r29,PP_HIBERNATE(r30)
437 andi. r29, r29, 1
438 beq noHashTableInit ; Skip following if not waking from from hibernate
439 bl EXT(hw_clear_maps) ; Mark all maps as absent from hash table
440 bl EXT(hw_hash_init) ; Clear hash table
441 bl EXT(save_snapshot_restore) ; Reset save area chains
442noHashTableInit:
91447636
A		 443 bl EXT(hw_setup_trans) ; Set up hardware needed for translation
444 bl EXT(hw_start_trans) ; Start translating
445
446run32:
55e303ae
A		 447 rlwinm. r0,r17,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
448 beq++ isnot64 ; Skip following if not 64-bit...
1c79356b 449
55e303ae 450 mfmsr r29 ; Get the MSR
91447636 451 rldicl r29,r29,0,MSR_SF_BIT+1 ; turn 64-bit mode off
55e303ae
A		 452 mtmsrd r29 ; Set it
453 isync ; Make sure
1c79356b 454
55e303ae 455isnot64: bf bootCPU,callcpu
1c79356b 456
91447636
A		 457 lis r29,HIGH_ADDR(EXT(intstack)) ; move onto interrupt stack
458 ori r29,r29,LOW_ADDR(EXT(intstack))
459 addi r29,r29,INTSTACK_SIZE-FM_SIZE
1c79356b
A		 460
461 li r28,0
462 stw r28,FM_BACKPTR(r29) ; store a null frame backpointer
463
464 mr r1,r29
465 mr r3,r31 ; Restore any arguments we may have trashed
466
55e303ae
A		 467; Note that we exit from here with translation still off
468
1c79356b
A		 469 bl EXT(ppc_init) ; Jump into boot init code
470 BREAKPOINT_TRAP
471
472callcpu:
91447636
A		 473 mfsprg r31,1 ; Fake activation pointer
474 lwz r31,ACT_PER_PROC(r31) ; Load per_proc
1c79356b
A		 475 lwz r29,PP_INTSTACK_TOP_SS(r31) ; move onto interrupt stack
476
477 li r28,0
478 stw r28,FM_BACKPTR(r29) ; store a null frame backpointer
479
1c79356b
A		 480 mr r1,r29 ; move onto new stack
481 mr r3,r31 ; Restore any arguments we may have trashed
482
91447636 483; Note that we exit from here with translation on
55e303ae 484
1c79356b
A		 485 bl EXT(ppc_init_cpu) ; Jump into cpu init code
486 BREAKPOINT_TRAP ; Should never return
487
488;
489; Specific processor initialization routines
490;
491
1c79356b
A		 492; 750
493
765c9de3
A		 494init750:
495 bf firstBoot, init750nb ; No init for wakeup....
1c79356b 496
765c9de3 497 mfspr r13,l2cr ; Get the L2CR
1c79356b
A		 498 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
499 bne+ i750hl2 ; Yes...
500 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
501
765c9de3
A		 502i750hl2:
503 lis r14,hi16(256*1024) ; Base L2 size
504 addis r15,r13,0x3000 ; Hah... Figure this one out...
505 rlwinm r15,r15,4,30,31 ; Isolate
506 rlwinm. r8,r13,0,l2siz,l2sizf ; Was size valid?
507 slw r14,r14,r15 ; Set 256KB, 512KB, or 1MB
508 beq- init750l2none ; Not a valid setting...
1c79356b 509
d52fe63f 510 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
765c9de3
A		 511 stw r13,pfl2cr(r30) ; Shadow the L2CR
512 stw r14,pfl2Size(r30) ; Set the L2 size
513 b init750l2done ; Done with L2
1c79356b 514
765c9de3
A		 515init750l2none:
516 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No level 2 cache
517
518init750l2done:
519 mfspr r11,hid0 ; Get the current HID0
520 stw r11,pfHID0(r30) ; Save the HID0 value
521 blr ; Return...
522
523init750nb:
d52fe63f 524 lwz r11,pfHID0(r30) ; Get HID0
765c9de3
A		 525 sync
526 mtspr hid0,r11 ; Set the HID
527 isync
528 sync
529 blr
1c79356b 530
d52fe63f
A		 531; 750CX
532
533init750CX:
534 bf firstBoot, init750 ; No init for wakeup....
535 mfspr r13,hid1 ; Get HID1
536 li r14,lo16(0xFD5F) ; Get valid
55e303ae
A		 537 rlwinm r13,r13,4,28,31 ; Isolate
538 slw r14,r14,r13 ; Position
539 rlwimi r17,r14,15-pfCanNapb,pfCanNapb,pfCanNapb ; Set it
540 b init750 ; Join common...
d52fe63f
A		 541
542
9bccf70c
A		 543; 750FX
544
545init750FX:
546 bf firstBoot, init750FXnb
547 mfspr r11, hid1
548 stw r11, pfHID1(r30) ; Save the HID1 value
549 b init750
550
551init750FXnb:
552 lwz r13, pfHID0(r30) ; Get HID0
553 lwz r11, pfHID1(r30) ; Get HID1
554
55e303ae 555 rlwinm. r0, r11, 0, hid1ps, hid1ps ; Isolate the hid1ps bit
9bccf70c 556 beq init750FXnb2 ; Clear BTIC if hid1ps set
55e303ae 557 rlwinm r13, r13, 0, btic+1, btic-1 ; Clear the BTIC bit
9bccf70c
A		 558
559init750FXnb2:
560 sync
561 mtspr hid0, r13 ; Set the HID
562 isync
563 sync
564
55e303ae 565 rlwinm r12, r11, 0, hid1ps+1, hid1ps-1 ; Select PLL0
9bccf70c 566 mtspr hid1, r12 ; Restore PLL config
55e303ae 567 mftb r13 ; Wait 5000 ticks (> 200 us)
9bccf70c
A		 568
569init750FXnbloop:
570 mftb r14
571 sub r14, r14, r13
572 cmpli cr0, r14, 5000
573 ble init750FXnbloop
574 mtspr hid1, r11 ; Select the desired PLL
575 blr
576
d12e1678
A		 577; 750FX vers 2.0 or later
578init750FXV2:
579 bf firstBoot, init750FXV2nb ; Wake from sleep
580
581 mfspr r11, hid2
582 stw r11, pfHID2(r30) ; Save the HID2 value
583 b init750FX ; Continue with 750FX init
584
585init750FXV2nb:
586 lwz r13, pfHID2(r30) ; Get HID2
587 rlwinm r13, r13, 0, hid2vmin+1, hid2vmin-1 ; Clear the vmin bit
588 mtspr hid2, r13 ; Restore HID2 value
589 sync ; Wait for it to be done
590 b init750FX
591
d52fe63f
A		 592; 7400
593
1c79356b
A		 594init7400: bf firstBoot,i7400nb ; Do different if not initial boot...
595 mfspr r13,l2cr ; Get the L2CR
596 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
597 bne+ i7400hl2 ; Yes...
598 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
599
600i7400hl2: lis r14,hi16(256*1024) ; Base L2 size
601 addis r15,r13,0x3000 ; Hah... Figure this one out...
602 rlwinm r15,r15,4,30,31
603 slw r14,r14,r15 ; Set 256KB, 512KB, 1MB, or 2MB
604
55e303ae 605 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
1c79356b
A		 606 stw r13,pfl2cr(r30) ; Shadow the L2CR
607 stw r14,pfl2Size(r30) ; Set the L2 size
608
609 mfspr r11,hid0 ; Get the current HID0
610 oris r11,r11,hi16(emcpm|eiecm) ; ?
611 mtspr hid0,r11 ; ?
612 isync
613 stw r11,pfHID0(r30) ; Save the HID0 value
614
615 mfspr r11,msscr0 ; Get the msscr0 register
616 stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
617 mfspr r11,msscr1 ; Get the msscr1 register
618 stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
619 blr ; Return...
620
765c9de3 621i7400nb:
d52fe63f 622 li r11,0
55e303ae 623 mtspr l2cr,r11 ; Make sure L2CR is zero
765c9de3 624 lwz r11,pfHID0(r30) ; Get HID0
1c79356b
A		 625 sync
626 mtspr hid0,r11 ; Set the HID
765c9de3
A		 627 isync
628 sync
1c79356b
A		 629 lwz r11,pfMSSCR0(r30) ; Get MSSCR0
630 isync
631 sync
632 mtspr msscr0,r11 ; Set the MSSCR0
633 lwz r11,pfMSSCR1(r30) ; Get msscr1
634 isync
635 sync
636 mtspr msscr1,r11 ; Set the msscr1
637 isync
638 sync
639 blr
9bccf70c
A		 640
641; 7400 (ver 2.0 - ver 2.7)
642
643init7400v2_7:
644 bf firstBoot, init7400
645 mfspr r13, hid0 ; Get the HID0
646 ori r13, r13, nopdstm ; ?
647 mtspr hid0, r13 ; Set the HID0
648 isync
649 sync
650 b init7400
651
1c79356b
A		 652; 7410
653; Note that this is the same as 7400 except we initialize the l2cr2 register
654
655init7410: li r13,0 ; Clear
656 mtspr 1016,r13 ; Turn off direct cache
657 b init7400 ; Join up with common....
1c79356b 658
d52fe63f
A		 659
660; 745X - Any 7450 family processor
661
662init745X:
55e303ae 663 bf firstBoot,init745Xnb ; Do different if not initial boot...
1c79356b
A		 664
665 mfspr r13,l2cr ; Get the L2CR
666 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
d52fe63f 667 bne+ init745Xhl2 ; Yes...
1c79356b
A		 668 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
669
43866e37 670init745Xhl2:
e5568f75
A		 671 mfpvr r14 ; Get processor version
672 rlwinm r14,r14,16,16,31 ; Isolate processor version
673 cmpli cr0, r14, PROCESSOR_VERSION_7457 ; Test for 7457 or
674 cmpli cr1, r14, PROCESSOR_VERSION_7447A ; 7447A
675 cror cr0_eq, cr1_eq, cr0_eq
43866e37 676 lis r14,hi16(512*1024) ; 512KB L2
e5568f75 677 beq init745Xhl2_2
43866e37
A		 678
679 lis r14,hi16(256*1024) ; Base L2 size
1c79356b
A		 680 rlwinm r15,r13,22,12,13 ; Convert to 256k, 512k, or 768k
681 add r14,r14,r15 ; Add in minimum
43866e37
A		 682
683init745Xhl2_2:
e5568f75 684 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
1c79356b
A		 685 stw r13,pfl2cr(r30) ; Shadow the L2CR
686 stw r14,pfl2Size(r30) ; Set the L2 size
687
688; Take care of level 3 cache
689
690 mfspr r13,l3cr ; Get the L3CR
7b1edb79 691 rlwinm. r0,r13,0,l3e,l3e ; Any L3?
d52fe63f 692 bne+ init745Xhl3 ; Yes...
7b1edb79 693 rlwinm r17,r17,0,pfL3b+1,pfL3b-1 ; No L3, turn off feature
1c79356b 694
55e303ae
A		 695init745Xhl3: cmplwi cr0,r13,0 ; No L3 if L3CR is zero
696 beq- init745Xnone ; Go turn off the features...
1c79356b
A		 697 lis r14,hi16(1024*1024) ; Base L3 size
698 rlwinm r15,r13,4,31,31 ; Get size multiplier
699 slw r14,r14,r15 ; Set 1 or 2MB
700
55e303ae 701 stw r13,pfl3crOriginal(r30) ; Shadow the L3CR
1c79356b
A		 702 stw r13,pfl3cr(r30) ; Shadow the L3CR
703 stw r14,pfl3Size(r30) ; Set the L3 size
d52fe63f 704 b init745Xfin ; Return....
1c79356b 705
d52fe63f 706init745Xnone:
55e303ae 707 rlwinm r17,r17,0,pfL3fab+1,pfL3b-1 ; No 3rd level cache or assist
0b4e3aa0
A		 708 rlwinm r11,r17,pfWillNapb-pfCanNapb,pfCanNapb,pfCanNapb ; Set pfCanNap if pfWillNap is set
709 or r17,r17,r11
1c79356b 710
d52fe63f 711init745Xfin:
55e303ae 712 rlwinm r17,r17,0,pfWillNapb+1,pfWillNapb-1 ; Make sure pfWillNap is not set
0b4e3aa0
A		 713
714 mfspr r11,hid0 ; Get the current HID0
1c79356b
A		 715 stw r11,pfHID0(r30) ; Save the HID0 value
716 mfspr r11,hid1 ; Get the current HID1
717 stw r11,pfHID1(r30) ; Save the HID1 value
718 mfspr r11,msscr0 ; Get the msscr0 register
719 stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
720 mfspr r11,msscr1 ; Get the msscr1 register
721 stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
722 mfspr r11,ictrl ; Get the ictrl register
723 stw r11,pfICTRL(r30) ; Save the ICTRL value
724 mfspr r11,ldstcr ; Get the ldstcr register
725 stw r11,pfLDSTCR(r30) ; Save the LDSTCR value
0b4e3aa0
A		 726 mfspr r11,ldstdb ; Get the ldstdb register
727 stw r11,pfLDSTDB(r30) ; Save the LDSTDB value
d52fe63f
A		 728 mfspr r11,pir ; Get the pir register
729 stw r11,pfBootConfig(r30) ; Save the BootConfig value
1c79356b
A		 730 blr ; Return....
731
732
d52fe63f 733init745Xnb: lwz r11,pfHID0(r30) ; Get HID0
1c79356b
A		 734 sync
735 mtspr hid0,r11 ; Set the HID
736 isync
737 lwz r11,pfHID1(r30) ; Get HID1
738 sync
739 mtspr hid1,r11 ; Set the HID
740 isync
741 lwz r11,pfMSSCR0(r30) ; Get MSSCR0
742 sync
743 mtspr msscr0,r11 ; Set the MSSCR0
744 isync
745 sync
746 lwz r11,pfICTRL(r30) ; Get ICTRL
747 sync
748 mtspr ictrl,r11 ; Set the ICTRL
749 isync
750 sync
751 lwz r11,pfLDSTCR(r30) ; Get LDSTCR
752 sync
753 mtspr ldstcr,r11 ; Set the LDSTCR
754 isync
755 sync
0b4e3aa0
A		 756 lwz r11,pfLDSTDB(r30) ; Get LDSTDB
757 sync
758 mtspr ldstdb,r11 ; Set the LDSTDB
759 isync
760 sync
1c79356b
A		 761 blr
762
d52fe63f
A		 763; 7450 - Specific
764
765init7450:
766 bf firstBoot, init745X ; Not boot, use standard init
767
768 mfspr r13, pir ; Get BootConfig from PIR
769 rlwinm. r14, r13, 0, 20, 23 ; Is the pdet value zero
770 bne init7450done ; No, done for now
771
772 ori r13, r13, 0x0400 ; Force pdet value to 4
773 mtspr pir, r13 ; Write back the BootConfig
774
775init7450done:
776 b init745X ; Continue with standard init
777
1c79356b 778
91447636
A		 779init970:
780 lis r20,8 ; Set up for 512K L2
781init970x:
782 li r0,0 ; Clear this
783 mtspr hior,r0 ; Make sure that 0 is interrupt prefix
55e303ae
A		 784 bf firstBoot,init970nb ; No init for wakeup or second processor....
785
786
91447636
A		 787;
788; We can not query or change the L2 size. We will just
789; phoney up a L2CR to make sysctl "happy" and set the
790; L2 size to 512K.
791;
792
793 lis r0,0x8000 ; Synthesize a "valid" but non-existant L2CR
794 stw r0,pfl2crOriginal(r30) ; Set a dummy L2CR
795 stw r0,pfl2cr(r30) ; Set a dummy L2CR
796 stw r20,pfl2Size(r30) ; Set the L2 size
797
55e303ae
A		 798 mfspr r11,hid0 ; Get original hid0
799 std r11,pfHID0(r30) ; Save original
800 mfspr r11,hid1 ; Get original hid1
801 std r11,pfHID1(r30) ; Save original
802 mfspr r11,hid4 ; Get original hid4
803 std r11,pfHID4(r30) ; Save original
804 mfspr r11,hid5 ; Get original hid5
805 std r11,pfHID5(r30) ; Save original
483a1d10
A		 806
807 lis r0, hi16(dnapm) ; Create a mask for the dnap bit
808 sldi r0, r0, 32 ; Shift to the top half
809 ld r11,pfHID0(r30) ; Load the hid0 value
810 andc r11, r11, r0 ; Clear the dnap bit
811 isync
812 mtspr hid0,r11 ; Stuff it
813 mfspr r11,hid0 ; Get it
814 mfspr r11,hid0 ; Get it
815 mfspr r11,hid0 ; Get it
816 mfspr r11,hid0 ; Get it
817 mfspr r11,hid0 ; Get it
818 mfspr r11,hid0 ; Get it
819 isync
820
91447636
A		 821 lis r0,(pcfValid|pcfLarge|pcfDedSeg)<<8 ; Set the valid bit, dedicated segment, and large page flags
822 ori r0,r0,(24<<8)|24 ; Add in the 16M page size
823 stw r0,lgpPcfg+(pcfSize*pcfLargePcfg)(0) ; Set the 16M primary large page configuration entry
55e303ae
A		 824
825 blr
826
827;
828; Start up code for second processor or wake up from sleep
829;
830
483a1d10
A		 831init970nb:
832 lis r0, hi16(dnapm) ; Create a mask for the dnap bit
833 sldi r0, r0, 32 ; Shift to the top half
834 ld r11,pfHID0(r30) ; Load the hid0 value
835 andc r11, r11, r0 ; Clear the dnap bit
55e303ae
A		 836 isync
837 mtspr hid0,r11 ; Stuff it
838 mfspr r11,hid0 ; Get it
839 mfspr r11,hid0 ; Get it
840 mfspr r11,hid0 ; Get it
841 mfspr r11,hid0 ; Get it
842 mfspr r11,hid0 ; Get it
843 mfspr r11,hid0 ; Get it
844 isync
845
5353443c 846 ld r20,pfHID1(r30) ; Get it
55e303ae 847 isync
5353443c
A		 848 mtspr hid1,r20 ; Stick it
849 mtspr hid1,r20 ; Stick it again
55e303ae
A		 850 isync
851
852 ld r11,pfHID4(r30) ; Get it
853 sync
854 mtspr hid4,r11 ; Stick it
855 isync
5353443c
A		 856
857 lis r11,0xE000 ; Get the unlikeliest ESID possible
858 srdi r11,r11,1 ; Make 0x7FFFFFFFF0000000
859 slbie r11 ; Make sure the ERAT is cleared
55e303ae
A		 860
861 ld r11,pfHID5(r30) ; Get it
862 mtspr hid5,r11 ; Set it
863 isync
5353443c
A		 864;
865; May have changed dcbz mode so kill icache
866;
867
868 eqv r13,r13,r13 ; Get a constant -1
869 mr r14,r20 ; Save HID1
870 rldimi r14,r13,54,9 ; Set force icbi match mode
871
872 li r11,0 ; Set start if ICBI range
873 isync
874 mtspr hid1,r14 ; Stick it
875 mtspr hid1,r14 ; Stick it again
876 isync
877
878inin970ki: icbi 0,r11 ; Kill I$
879 addi r11,r11,128 ; Next line
880 andis. r0,r11,1 ; Have we done them all?
881 beq++ inin970ki ; Not yet...
882
883 isync
884 mtspr hid1,r20 ; Stick it
885 mtspr hid1,r20 ; Stick it again
886 isync
887
55e303ae 888 blr ; Leave...
91447636
A		 889
890
55e303ae
A		 891
892; Unsupported Processors
893initUnsupported:
894 mtlr r2 ; Restore the return address
895 blr ; Return to the booter
896
897
1c79356b
A		 898;
899; Processor to feature table
900
901; .align 2 - Always on word boundary
902; .long ptFilter - Mask of significant bits in the Version/Revision code
903; - NOTE: Always order from most restrictive to least restrictive matching
904; .short ptVersion - Version code from PVR. Always start with 0 which is default
905; .short ptRevision - Revision code from PVR. A zero value denotes the generic attributes if not specific
906; .long ptFeatures - Available features
43866e37 907; .long ptCPUCap - Default value for _cpu_capabilities
4a249263 908; .long ptPwrModes - Available power management features
55e303ae 909; .long ptPatch - Patch features
1c79356b
A		 910; .long ptInitRout - Initilization routine. Can modify any of the other attributes.
911; .long ptRptdProc - Processor type reported
1c79356b
A		 912; .long ptLineSize - Level 1 cache line size
913; .long ptl1iSize - Level 1 instruction cache size
914; .long ptl1dSize - Level 1 data cache size
55e303ae
A		 915; .long ptPTEG - Size of PTEG
916; .long ptMaxVAddr - Maximum effective address
917; .long ptMaxPAddr - Maximum physical address
918;
1c79356b
A		 919
920 .align 2
921processor_types:
922
1c79356b
A		 923; 750CX (ver 2.x)
924
55e303ae
A		 925 .align 2
926 .long 0xFFFF0F00 ; 2.x vers
927 .short PROCESSOR_VERSION_750
928 .short 0x0200
929 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2
930 .long kCache32 | kHasGraphicsOps | kHasStfiwx
4a249263 931 .long 0
55e303ae
A		 932 .long PatchExt32
933 .long init750CX
934 .long CPU_SUBTYPE_POWERPC_750
55e303ae
A		 935 .long 32
936 .long 32*1024
937 .long 32*1024
938 .long 64
939 .long 52
940 .long 32
941
1c79356b
A		 942; 750 (generic)
943
55e303ae
A		 944 .align 2
945 .long 0xFFFF0000 ; All revisions
946 .short PROCESSOR_VERSION_750
947 .short 0
483a1d10 948 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2
55e303ae 949 .long kCache32 | kHasGraphicsOps | kHasStfiwx
4a249263 950 .long 0
55e303ae
A		 951 .long PatchExt32
952 .long init750
953 .long CPU_SUBTYPE_POWERPC_750
55e303ae
A		 954 .long 32
955 .long 32*1024
956 .long 32*1024
957 .long 64
958 .long 52
959 .long 32
960
d12e1678
A		 961; 750FX (ver 1.x)
962
55e303ae
A		 963 .align 2
964 .long 0xFFFF0F00 ; 1.x vers
965 .short PROCESSOR_VERSION_750FX
966 .short 0x0100
967 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pf32Byte | pfL2
968 .long kCache32 | kHasGraphicsOps | kHasStfiwx
4a249263 969 .long pmDualPLL
55e303ae
A		 970 .long PatchExt32
971 .long init750FX
972 .long CPU_SUBTYPE_POWERPC_750
55e303ae
A		 973 .long 32
974 .long 32*1024
975 .long 32*1024
976 .long 64
977 .long 52
978 .long 32
979
9bccf70c 980; 750FX (generic)
0b4e3aa0 981
55e303ae
A		 982 .align 2
983 .long 0xFFFF0000 ; All revisions
984 .short PROCESSOR_VERSION_750FX
985 .short 0
986 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pf32Byte | pfL2
987 .long kCache32 | kHasGraphicsOps | kHasStfiwx
4a249263 988 .long pmDualPLL | pmDPLLVmin
55e303ae
A		 989 .long PatchExt32
990 .long init750FXV2
991 .long CPU_SUBTYPE_POWERPC_750
55e303ae
A		 992 .long 32
993 .long 32*1024
994 .long 32*1024
995 .long 64
996 .long 52
997 .long 32
998
9bccf70c
A		 999; 7400 (ver 2.0 - ver 2.7)
1000
55e303ae
A		 1001 .align 2
1002 .long 0xFFFFFFF8 ; ver 2.0 - 2.7
1003 .short PROCESSOR_VERSION_7400
1004 .short 0x0200
483a1d10 1005 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
55e303ae 1006 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
4a249263 1007 .long 0
55e303ae
A		 1008 .long PatchExt32
1009 .long init7400v2_7
1010 .long CPU_SUBTYPE_POWERPC_7400
55e303ae
A		 1011 .long 32
1012 .long 32*1024
1013 .long 32*1024
1014 .long 64
1015 .long 52
1016 .long 32
1017
1c79356b
A		 1018; 7400 (generic)
1019
55e303ae
A		 1020 .align 2
1021 .long 0xFFFF0000 ; All revisions
1022 .short PROCESSOR_VERSION_7400
1023 .short 0
483a1d10 1024 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
55e303ae 1025 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
4a249263 1026 .long 0
55e303ae
A		 1027 .long PatchExt32
1028 .long init7400
1029 .long CPU_SUBTYPE_POWERPC_7400
55e303ae
A		 1030 .long 32
1031 .long 32*1024
1032 .long 32*1024
1033 .long 64
1034 .long 52
1035 .long 36
1036
1c79356b
A		 1037; 7410 (ver 1.1)
1038
55e303ae
A		 1039 .align 2
1040 .long 0xFFFFFFFF ; Exact match
1041 .short PROCESSOR_VERSION_7400
1042 .short 0x1101
1043 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1044 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
4a249263 1045 .long 0
55e303ae
A		 1046 .long PatchExt32
1047 .long init7410
1048 .long CPU_SUBTYPE_POWERPC_7400
55e303ae
A		 1049 .long 32
1050 .long 32*1024
1051 .long 32*1024
1052 .long 64
1053 .long 52
1054 .long 36
1c79356b
A		 1055
1056; 7410 (generic)
1057
55e303ae
A		 1058 .align 2
1059 .long 0xFFFF0000 ; All other revisions
1060 .short PROCESSOR_VERSION_7410
1061 .short 0
1062 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba
1063 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
4a249263 1064 .long 0
55e303ae
A		 1065 .long PatchExt32
1066 .long init7410
1067 .long CPU_SUBTYPE_POWERPC_7400
55e303ae
A		 1068 .long 32
1069 .long 32*1024
1070 .long 32*1024
1071 .long 64
1072 .long 52
1073 .long 36
1c79356b
A		 1074
1075; 7450 (ver 1.xx)
1076
55e303ae
A		 1077 .align 2
1078 .long 0xFFFFFF00 ; Just revisions 1.xx
1079 .short PROCESSOR_VERSION_7450
1080 .short 0x0100
1081 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1082 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
4a249263 1083 .long 0
55e303ae
A		 1084 .long PatchExt32
1085 .long init7450
1086 .long CPU_SUBTYPE_POWERPC_7450
55e303ae
A		 1087 .long 32
1088 .long 32*1024
1089 .long 32*1024
1090 .long 64
1091 .long 52
1092 .long 36
1c79356b 1093
0b4e3aa0
A		 1094; 7450 (2.0)
1095
55e303ae
A		 1096 .align 2
1097 .long 0xFFFFFFFF ; Just revision 2.0
1098 .short PROCESSOR_VERSION_7450
1099 .short 0x0200
1100 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1101 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
4a249263 1102 .long 0
55e303ae
A		 1103 .long PatchExt32
1104 .long init7450
1105 .long CPU_SUBTYPE_POWERPC_7450
55e303ae
A		 1106 .long 32
1107 .long 32*1024
1108 .long 32*1024
1109 .long 64
1110 .long 52
1111 .long 36
0b4e3aa0
A		 1112
1113; 7450 (2.1)
1c79356b 1114
55e303ae
A		 1115 .align 2
1116 .long 0xFFFF0000 ; All other revisions
1117 .short PROCESSOR_VERSION_7450
1118 .short 0
1119 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1120 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
4a249263 1121 .long 0
55e303ae
A		 1122 .long PatchExt32
1123 .long init7450
1124 .long CPU_SUBTYPE_POWERPC_7450
55e303ae
A		 1125 .long 32
1126 .long 32*1024
1127 .long 32*1024
1128 .long 64
1129 .long 52
1130 .long 36
1c79356b 1131
d52fe63f
A		 1132; 7455 (1.xx) Just like 7450 2.0
1133
55e303ae
A		 1134 .align 2
1135 .long 0xFFFFFF00 ; Just revisions 1.xx
1136 .short PROCESSOR_VERSION_7455
1137 .short 0x0100
1138 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1139 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
4a249263 1140 .long 0
55e303ae
A		 1141 .long PatchExt32
1142 .long init745X
1143 .long CPU_SUBTYPE_POWERPC_7450
55e303ae
A		 1144 .long 32
1145 .long 32*1024
1146 .long 32*1024
1147 .long 64
1148 .long 52
1149 .long 36
d52fe63f
A		 1150
1151; 7455 (2.0)
1152
55e303ae
A		 1153 .align 2
1154 .long 0xFFFFFFFF ; Just revision 2.0
1155 .short PROCESSOR_VERSION_7455
1156 .short 0x0200
1157 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1158 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
4a249263 1159 .long 0
55e303ae
A		 1160 .long PatchExt32
1161 .long init745X
1162 .long CPU_SUBTYPE_POWERPC_7450
55e303ae
A		 1163 .long 32
1164 .long 32*1024
1165 .long 32*1024
1166 .long 64
1167 .long 52
1168 .long 36
d52fe63f
A		 1169
1170; 7455 (2.1)
1171
55e303ae
A		 1172 .align 2
1173 .long 0xFFFF0000 ; All other revisions
1174 .short PROCESSOR_VERSION_7455
1175 .short 0
1176 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1177 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
4a249263 1178 .long 0
55e303ae
A		 1179 .long PatchExt32
1180 .long init745X
1181 .long CPU_SUBTYPE_POWERPC_7450
55e303ae
A		 1182 .long 32
1183 .long 32*1024
1184 .long 32*1024
1185 .long 64
1186 .long 52
1187 .long 36
43866e37
A		 1188
1189; 7457
1190
55e303ae
A		 1191 .align 2
1192 .long 0xFFFF0000 ; All revisions
1193 .short PROCESSOR_VERSION_7457
1194 .short 0
1195 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1196 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
4a249263 1197 .long 0
55e303ae
A		 1198 .long PatchExt32
1199 .long init745X
1200 .long CPU_SUBTYPE_POWERPC_7450
55e303ae
A		 1201 .long 32
1202 .long 32*1024
1203 .long 32*1024
1204 .long 64
1205 .long 52
1206 .long 36
1207
e5568f75
A		 1208; 7447A
1209
1210 .align 2
1211 .long 0xFFFF0000 ; All revisions
1212 .short PROCESSOR_VERSION_7447A
1213 .short 0
1214 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba
1215 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
1216 .long pmDFS
1217 .long PatchExt32
1218 .long init745X
1219 .long CPU_SUBTYPE_POWERPC_7450
e5568f75
A		 1220 .long 32
1221 .long 32*1024
1222 .long 32*1024
1223 .long 64
1224 .long 52
1225 .long 36
1226
55e303ae
A		 1227; 970
1228
1229 .align 2
1230 .long 0xFFFF0000 ; All versions so far
1231 .short PROCESSOR_VERSION_970
1232 .short 0
1233 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pf128Byte | pf64Bit | pfL2 | pfSCOMFixUp
1234 .long kHasAltivec | k64Bit | kCache128 | kDataStreamsAvailable | kDcbtStreamsRecommended | kDcbtStreamsAvailable | kHasGraphicsOps | kHasStfiwx | kHasFsqrt
4a249263
A		 1235 .long 0
1236 .long PatchLwsync
1237 .long init970
1238 .long CPU_SUBTYPE_POWERPC_970
4a249263
A		 1239 .long 128
1240 .long 64*1024
1241 .long 32*1024
1242 .long 128
1243 .long 65
1244 .long 42
1245
1246; 970FX
1247
1248 .align 2
1249 .long 0xFFFF0000 ; All versions so far
1250 .short PROCESSOR_VERSION_970FX
1251 .short 0
1252 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pf128Byte | pf64Bit | pfL2
1253 .long kHasAltivec | k64Bit | kCache128 | kDataStreamsAvailable | kDcbtStreamsRecommended | kDcbtStreamsAvailable | kHasGraphicsOps | kHasStfiwx | kHasFsqrt
1254 .long pmPowerTune
55e303ae
A		 1255 .long PatchLwsync
1256 .long init970
1257 .long CPU_SUBTYPE_POWERPC_970
55e303ae
A		 1258 .long 128
1259 .long 64*1024
1260 .long 32*1024
1261 .long 128
1262 .long 65
1263 .long 42
1264
91447636 1265
55e303ae
A		 1266; All other processors are not supported
1267
1268 .align 2
1269 .long 0x00000000 ; Matches everything
1270 .short 0
1271 .short 0
1272 .long pfFloat | pf32Byte
1273 .long kCache32 | kHasGraphicsOps | kHasStfiwx
4a249263 1274 .long 0
55e303ae
A		 1275 .long PatchExt32
1276 .long initUnsupported
1277 .long CPU_SUBTYPE_POWERPC_ALL
55e303ae
A		 1278 .long 32
1279 .long 32*1024
1280 .long 32*1024
1281 .long 64
1282 .long 52
1283 .long 32
1c79356b 1284
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