]> git.saurik.com Git - apple/xnu.git/blame - osfmk/ppc/start.s
projects / apple / xnu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
xnu-344.49.tar.gz
[apple/xnu.git] / osfmk / ppc / start.s
CommitLineData
1c79356b
A		 1/*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
43866e37 6 * Copyright (c) 1999-2003 Apple Computer, Inc. All Rights Reserved.
1c79356b 7 *
43866e37
A		 8 * This file contains Original Code and/or Modifications of Original Code
9 * as defined in and that are subject to the Apple Public Source License
10 * Version 2.0 (the 'License'). You may not use this file except in
11 * compliance with the License. Please obtain a copy of the License at
12 * http://www.opensource.apple.com/apsl/ and read it before using this
13 * file.
14 *
15 * The Original Code and all software distributed under the License are
16 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
1c79356b
A		 17 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
18 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
43866e37
A		 19 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
20 * Please see the License for the specific language governing rights and
21 * limitations under the License.
1c79356b
A		 22 *
23 * @APPLE_LICENSE_HEADER_END@
24 */
25/*
26 * @OSF_COPYRIGHT@
27 */
43866e37
A		 28
29#define __APPLE_API_PRIVATE
30
1c79356b
A		 31#include <cpus.h>
32#include <mach_kdb.h>
33#include <mach_kdp.h>
34#include <mach_kgdb.h>
35#include <ppc/asm.h>
36#include <ppc/proc_reg.h>
9bccf70c 37#include <ppc/spec_reg.h>
43866e37 38#include <machine/cpu_capabilities.h>
1c79356b
A		 39#include <mach/ppc/vm_param.h>
40#include <assym.s>
41
43866e37
A		 42#define ptFilter 0
43#define ptVersion 4
44#define ptRevision 6
45#define ptFeatures 8
46#define ptCPUCap 12
47#define ptInitRout 16
48#define ptRptdProc 20
49#define ptTempMax 24
50#define ptTempThr 28
51#define ptLineSize 32
52#define ptl1iSize 36
53#define ptl1dSize 40
54#define ptSize 44
1c79356b
A		 55
56#define bootCPU 10
57#define firstInit 9
58#define firstBoot 8
0b4e3aa0 59
1c79356b
A		 60/*
61 * Interrupt and bootup stack for initial processor
62 */
63
64 .file "start.s"
65
de355530
A		 66 .data
67
68 /* Align on page boundry */
69 .align PPC_PGSHIFT
70 /* Red zone for interrupt stack, one page (will be unmapped)*/
71 .set ., .+PPC_PGBYTES
72 /* intstack itself */
73
74 .globl EXT(FixedStackStart)
75EXT(FixedStackStart):
76
77 .globl EXT(intstack)
78EXT(intstack):
79 .set ., .+INTSTACK_SIZE*NCPUS
80
81 /* Debugger stack - used by the debugger if present */
82 /* NOTE!!! Keep the debugger stack right after the interrupt stack */
83#if MACH_KDP || MACH_KDB
84 .globl EXT(debstack)
85EXT(debstack):
86 .set ., .+KERNEL_STACK_SIZE*NCPUS
87
88 .globl EXT(FixedStackEnd)
89EXT(FixedStackEnd):
90
91 .align ALIGN
92 .globl EXT(intstack_top_ss)
93EXT(intstack_top_ss):
94 .long EXT(intstack)+INTSTACK_SIZE-FM_SIZE /* intstack_top_ss points to the top of interrupt stack */
95
96 .align ALIGN
97 .globl EXT(debstack_top_ss)
98EXT(debstack_top_ss):
99
100 .long EXT(debstack)+KERNEL_STACK_SIZE-FM_SIZE /* debstack_top_ss points to the top of debug stack */
101
102 .globl EXT(debstackptr)
103EXT(debstackptr):
104 .long EXT(debstack)+KERNEL_STACK_SIZE-FM_SIZE
105
106#endif /* MACH_KDP || MACH_KDB */
107
43866e37 108
1c79356b
A		 109/*
110 * All CPUs start here.
111 *
112 * This code is called from SecondaryLoader
113 *
114 * Various arguments are passed via a table:
de355530 115 * ARG0 = pointer to other startup parameters
1c79356b
A		 116 */
117 .text
de355530 118
1c79356b
A		 119ENTRY(_start_cpu,TAG_NO_FRAME_USED)
120 crclr bootCPU ; Set non-boot processor
121 crclr firstInit ; Set not first time init
122 mr r30,r3 ; Set current per_proc
123
124;
125; Note that we are just trying to get close. The real TB sync will take
126; place later. The value we are loading is set in two places. For the
127; main processor, it will be the TB at the last interrupt before we went
128; to sleep. For the others, it will be the time just before the main
129; processor woke us up.
130;
131
132 lwz r15,ruptStamp(r3) ; Get the timebase from the other processor
133 li r17,0 ; Clear this out
134 lwz r16,ruptStamp+4(r3) ; Get the timebase from the other processor
135 mtspr tbl,r17 ; Clear bottom so we do not tick
136 mtspr tbu,r15 ; Set top
137 mtspr tbl,r16 ; Then bottom again
de355530 138
1c79356b
A		 139 b allstart
140
141ENTRY(_start,TAG_NO_FRAME_USED)
142
143 lis r30,hi16(EXT(per_proc_info)) ; Set current per_proc
144 ori r30,r30,lo16(EXT(per_proc_info)) ; Set current per_proc
145 crset bootCPU ; Set boot processor
146
147 lwz r17,pfAvailable(r30) ; Get the available bits
148 rlwinm. r0,r17,0,pfValidb,pfValidb ; Have we initialized the feature flags yet?
149 crmove firstInit,cr0_eq ; Set if we are doing first time init
150 bne allstart ; Yeah, we must be waking up from sleep...
151
152;
153; Here is where we do any one time general low-level initialization
154
155 lis r20,HIGH_ADDR(fwdisplock) ; Get address of the firmware display lock
156 li r19,0 ; Zorch a register
157 ori r20,r20,LOW_ADDR(fwdisplock) ; Get address of the firmware display lock
158 stw r19,0(r20) ; Make sure the lock is free
159
43866e37
A		 160allstart:
161 mr r31,r3 ; Save away arguments
162
163 crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
164
de355530
A		 165 lis r23,hi16(EXT(per_proc_info)) ; Set base per_proc
166 ori r23,r23,lo16(EXT(per_proc_info)) ; Set base per_proc
1c79356b 167
d7e50217 168 mtsprg 0,r30 ; Set the per_proc
1c79356b 169
de355530 170 mfspr r6,hid0 ; Get the HID0
d7e50217 171 li r7,MSR_VM_OFF ; Get real mode MSR
de355530
A		 172 rlwinm r6,r6,0,sleep+1,doze-1 ; Remove any vestiges of sleep
173 mtspr hid0,r6 ; Set the insominac HID0
d7e50217
A		 174 mtmsr r7 ; Set the real mode SRR
175 isync
176
de355530
A		 177; Map in the first 256Mb in both instruction and data BATs
178
179 li r7,((0x7FF<<2)|2) ; Set up for V=R 256MB in supervisor space
180 li r8,((2<<3)|2) ; Physical address = 0, coherent, R/W
181 li r9,0 ; Clear out a register
182
183 mtsprg 1,r9 ; Clear the extra SPRGs
184 mtsprg 2,r9
185 mtsprg 3,r9
186
187 sync
188 isync
189 mtdbatu 0,r7 ; Map bottom 256MB
190 mtdbatl 0,r8 ; Map bottom 256MB
191 mtdbatu 1,r9 ; Invalidate maps
192 mtdbatl 1,r9 ; Invalidate maps
193 mtdbatu 2,r9 ; Invalidate maps
194 mtdbatl 2,r9 ; Invalidate maps
195 mtdbatu 3,r9 ; Invalidate maps
196 mtdbatl 3,r9 ; Invalidate maps
197 sync
198 isync
199 mtibatu 0,r7 ; Map bottom 256MB
200 mtibatl 0,r8 ; Map bottom 256MB
201 mtibatu 1,r9 ; Invalidate maps
202 mtibatl 1,r9 ; Invalidate maps
203 mtibatu 2,r9 ; Invalidate maps
204 mtibatl 2,r9 ; Invalidate maps
205 mtibatu 3,r9 ; Invalidate maps
206 mtibatl 3,r9 ; Invalidate maps
207 sync
208 isync
209
1c79356b
A		 210 lis r26,hi16(processor_types) ; Point to processor table
211 ori r26,r26,lo16(processor_types) ; Other half
212 mfpvr r10 ; Get the PVR
213
214nextPVR: lwz r28,ptFilter(r26) ; Get the filter
215 lwz r27,ptVersion(r26) ; Get the version and revision codes
216 and r28,r10,r28 ; Throw away dont care bits
217 cmplw r27,r28 ; Is this the right set?
218 beq donePVR ; We have the right one...
219 addi r26,r26,ptSize ; Point to the next type
220 b nextPVR ; Check it out...
221
222donePVR: lwz r20,ptInitRout(r26) ; Grab the special init routine
223 mtlr r20 ; Setup to call the init
224
43866e37 225 bf firstBoot,notFirst ; Not first boot, go...
1c79356b
A		 226
227;
228; The following code just does a general initialization of the features just
229; after the initial first-time boot. This is not done after waking up or on
de355530 230; any "secondary" processor.
1c79356b
A		 231;
232; We are just setting defaults. The specific initialization code will modify these
233; if necessary.
234;
43866e37
A		 235 lis r13,hi16(EXT(_cpu_capabilities)) ; Get the address of _cpu_capabilities
236 ori r13,r13,lo16(EXT(_cpu_capabilities))
237 lwz r17,ptCPUCap(r26) ; Get the default cpu capabilities
238 stw r17, 0(r13) ; Save the default value in _cpu_capabilities
1c79356b
A		 239
240 lwz r17,ptFeatures(r26) ; Pick up the features
241
de355530
A		 242 lwz r13,ptRptdProc(r26) ; Get the reported processor
243 sth r13,pfrptdProc(r30) ; Set the reported processor
1c79356b
A		 244
245 lwz r13,ptTempMax(r26) ; Get maximum operating temperature
246 stw r13,thrmmaxTemp(r30) ; Set the maximum
247 lwz r13,ptTempThr(r26) ; Get temprature to throttle down when exceeded
248 stw r13,thrmthrottleTemp(r30) ; Set the temperature that we throttle
249
250 lwz r13,ptLineSize(r26) ; Get the cache line size
251 sth r13,pflineSize(r30) ; Save it
252 lwz r13,ptl1iSize(r26) ; Get icache size
253 stw r13,pfl1iSize(r30) ; Save it
254 lwz r13,ptl1dSize(r26) ; Get dcache size
255 stw r13,pfl1dSize(r30) ; Save it
256 b doOurInit ; Go do processor specific initialization...
257
258notFirst: lwz r17,pfAvailable(r30) ; Get our features
de355530
A		 259 rlwinm. r0,r17,0,pfValidb,pfValidb ; Have we set up this CPU yet?
260 bne doOurInit ; Yeah, must be wakeup...
1c79356b
A		 261
262 lis r23,hi16(EXT(per_proc_info)) ; Set base per_proc
263 ori r23,r23,lo16(EXT(per_proc_info)) ; Set base per_proc
264
de355530 265 la r7,pfAvailable(r30) ; Point to features of our processor
1c79356b
A		 266 la r8,pfAvailable(r23) ; Point to features of boot processor
267 li r9,(pfSize+thrmSize)/4 ; Get size of a features area
268
269cpyFeat: subi r9,r9,1 ; Count word
270 lwz r0,0(r8) ; Get boot cpu features
271 stw r0,0(r7) ; Copy to ours
272 mr. r9,r9 ; Finished?
273 addi r7,r7,4 ; Next out
274 addi r8,r8,4 ; Next in
275 bgt cpyFeat ; Copy all boot cpu features to us...
1c79356b 276
de355530 277 lwz r17,pfAvailable(r30) ; Get our newly initialized features
d7e50217 278
de355530
A		 279doOurInit:
280 mr. r20,r20 ; See if initialization routine
de355530 281 bnelrl ; Do the initialization
1c79356b 282
de355530
A		 283 ori r17,r17,lo16(pfValid) ; Set the valid bit
284 stw r17,pfAvailable(r30) ; Set the available features
285 mtsprg 2,r17 ; Remember the feature flags
d7e50217 286
1c79356b
A		 287 rlwinm. r0,r17,0,pfFloatb,pfFloatb ; See if there is floating point
288 beq- noFloat ; Nope, this is a really stupid machine...
289
290 li r0,MSR_VM_OFF|MASK(MSR_FP) ; Enable for floating point
291 mtmsr r0 /* Set the standard MSR values */
292 isync
293
294 lis r5,HIGH_ADDR(EXT(FloatInit)) /* Get top of floating point init value */
295 ori r5,r5,LOW_ADDR(EXT(FloatInit)) /* Slam bottom */
296 lfd f0,0(r5) /* Initialize FP0 */
297 fmr f1,f0 /* Ours in not */
298 fmr f2,f0 /* to wonder why, */
299 fmr f3,f0 /* ours is but to */
300 fmr f4,f0 /* do or die! */
301 fmr f5,f0
302 fmr f6,f0
303 fmr f7,f0
304 fmr f8,f0
305 fmr f9,f0
306 fmr f10,f0
307 fmr f11,f0
308 fmr f12,f0
309 fmr f13,f0
310 fmr f14,f0
311 fmr f15,f0
312 fmr f16,f0
313 fmr f17,f0
314 fmr f18,f0
315 fmr f19,f0
316 fmr f20,f0
317 fmr f21,f0
318 fmr f22,f0
319 fmr f23,f0
320 fmr f24,f0
321 fmr f25,f0
322 fmr f26,f0
323 fmr f27,f0
324 fmr f28,f0
325 fmr f29,f0
326 fmr f30,f0
327 fmr f31,f0
328
329 li r0, MSR_VM_OFF ; Turn off floating point
330 mtmsr r0
331 isync
332
333noFloat: rlwinm. r0,r17,0,pfAltivecb,pfAltivecb ; See if there is Altivec
334 beq- noVector ; Nope...
335
336 li r0,0 ; Clear out a register
337
338 lis r7,hi16(MSR_VEC_ON) ; Get real mode MSR + Altivec
339 ori r7,r7,lo16(MSR_VM_OFF) ; Get real mode MSR + Altivec
340 mtmsr r7 ; Set the real mode SRR */
341 isync ; Make sure it has happened
342
343 lis r5,hi16(EXT(QNaNbarbarian)) ; Altivec initializer
344 ori r5,r5,lo16(EXT(QNaNbarbarian)) ; Altivec initializer
345
346 mtspr vrsave,r0 ; Set that no VRs are used yet */
347
de355530 348 vspltisw v1,0 ; Clear a register
1c79356b
A		 349 lvx v0,br0,r5 ; Initialize VR0
350 mtvscr v1 ; Clear the vector status register
351 vor v2,v0,v0 ; Copy into the next register
352 vor v1,v0,v0 ; Copy into the next register
353 vor v3,v0,v0 ; Copy into the next register
354 vor v4,v0,v0 ; Copy into the next register
355 vor v5,v0,v0 ; Copy into the next register
356 vor v6,v0,v0 ; Copy into the next register
357 vor v7,v0,v0 ; Copy into the next register
358 vor v8,v0,v0 ; Copy into the next register
359 vor v9,v0,v0 ; Copy into the next register
360 vor v10,v0,v0 ; Copy into the next register
361 vor v11,v0,v0 ; Copy into the next register
362 vor v12,v0,v0 ; Copy into the next register
363 vor v13,v0,v0 ; Copy into the next register
364 vor v14,v0,v0 ; Copy into the next register
365 vor v15,v0,v0 ; Copy into the next register
366 vor v16,v0,v0 ; Copy into the next register
367 vor v17,v0,v0 ; Copy into the next register
368 vor v18,v0,v0 ; Copy into the next register
369 vor v19,v0,v0 ; Copy into the next register
370 vor v20,v0,v0 ; Copy into the next register
371 vor v21,v0,v0 ; Copy into the next register
372 vor v22,v0,v0 ; Copy into the next register
373 vor v23,v0,v0 ; Copy into the next register
374 vor v24,v0,v0 ; Copy into the next register
375 vor v25,v0,v0 ; Copy into the next register
376 vor v26,v0,v0 ; Copy into the next register
377 vor v27,v0,v0 ; Copy into the next register
378 vor v28,v0,v0 ; Copy into the next register
379 vor v29,v0,v0 ; Copy into the next register
380 vor v30,v0,v0 ; Copy into the next register
381 vor v31,v0,v0 ; Copy into the next register
382
383 li r0, MSR_VM_OFF ; Turn off vectors
384 mtmsr r0
385 isync
386
387noVector: rlwinm. r0,r17,0,pfSMPcapb,pfSMPcapb ; See if we can do SMP
388 beq- noSMP ; Nope...
389
390 lhz r13,PP_CPU_NUMBER(r30) ; Get the CPU number
391 mtspr pir,r13 ; Set the PIR
392
393noSMP: rlwinm. r0,r17,0,pfThermalb,pfThermalb ; See if there is an TAU
394 beq- noThermometer ; Nope...
395
396 li r13,0 ; Disable thermals for now
397 mtspr thrm3,r13 ; Do it
398 li r13,lo16(thrmtidm|thrmvm) ; Set for lower-than thermal event at 0 degrees
399 mtspr thrm1,r13 ; Do it
400 lis r13,hi16(thrmthrm) ; Set 127 degrees
401 ori r13,r13,lo16(thrmvm) ; Set for higher-than event
402 mtspr thrm2,r13 ; Set it
403
404noThermometer:
405
406 bl EXT(cacheInit) ; Initializes all caches (including the TLB)
407
de355530
A		 408 li r0,MSR_SUPERVISOR_INT_OFF ; Make sure we do not have FP enabled
409 mtmsr r0 ; Set the standard MSR values
410 isync
1c79356b 411
de355530 412 bf bootCPU,callcpu ; Not the boot processor...
1c79356b
A		 413
414 lis r29,HIGH_ADDR(EXT(intstack_top_ss)) ; move onto interrupt stack
415 ori r29,r29,LOW_ADDR(EXT(intstack_top_ss))
416 lwz r29,0(r29)
417
418 li r28,0
419 stw r28,FM_BACKPTR(r29) ; store a null frame backpointer
420
421 mr r1,r29
422 mr r3,r31 ; Restore any arguments we may have trashed
423
424 bl EXT(ppc_init) ; Jump into boot init code
425 BREAKPOINT_TRAP
426
427callcpu:
428 lwz r29,PP_INTSTACK_TOP_SS(r31) ; move onto interrupt stack
429
430 li r28,0
431 stw r28,FM_BACKPTR(r29) ; store a null frame backpointer
432
433
434 mr r1,r29 ; move onto new stack
435 mr r3,r31 ; Restore any arguments we may have trashed
436
437 bl EXT(ppc_init_cpu) ; Jump into cpu init code
438 BREAKPOINT_TRAP ; Should never return
439
440;
441; Specific processor initialization routines
442;
443
1c79356b
A		 444; 750
445
765c9de3
A		 446init750:
447 bf firstBoot, init750nb ; No init for wakeup....
1c79356b 448
765c9de3 449 mfspr r13,l2cr ; Get the L2CR
1c79356b
A		 450 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
451 bne+ i750hl2 ; Yes...
452 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
453
765c9de3
A		 454i750hl2:
455 lis r14,hi16(256*1024) ; Base L2 size
456 addis r15,r13,0x3000 ; Hah... Figure this one out...
457 rlwinm r15,r15,4,30,31 ; Isolate
458 rlwinm. r8,r13,0,l2siz,l2sizf ; Was size valid?
459 slw r14,r14,r15 ; Set 256KB, 512KB, or 1MB
460 beq- init750l2none ; Not a valid setting...
1c79356b 461
d52fe63f 462 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
765c9de3
A		 463 stw r13,pfl2cr(r30) ; Shadow the L2CR
464 stw r14,pfl2Size(r30) ; Set the L2 size
465 b init750l2done ; Done with L2
1c79356b 466
765c9de3
A		 467init750l2none:
468 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No level 2 cache
469
470init750l2done:
471 mfspr r11,hid0 ; Get the current HID0
472 stw r11,pfHID0(r30) ; Save the HID0 value
473 blr ; Return...
474
475init750nb:
d52fe63f 476 lwz r11,pfHID0(r30) ; Get HID0
765c9de3
A		 477 sync
478 mtspr hid0,r11 ; Set the HID
479 isync
480 sync
481 blr
1c79356b 482
d52fe63f
A		 483; 750CX
484
485init750CX:
486 bf firstBoot, init750 ; No init for wakeup....
487 mfspr r13,hid1 ; Get HID1
488 li r14,lo16(0xFD5F) ; Get valid
de355530
A		 489 rlwinm r13,r13,4,28,31 ; Isolate
490 slw r14,r14,r13 ; Position
491 rlwimi r17,r14,15-pfCanNapb,pfCanNapb,pfCanNapb ; Set it
492 b init750 ; Join common...
d52fe63f
A		 493
494
9bccf70c
A		 495; 750FX
496
497init750FX:
498 bf firstBoot, init750FXnb
499 mfspr r11, hid1
500 stw r11, pfHID1(r30) ; Save the HID1 value
501 b init750
502
503init750FXnb:
504 lwz r13, pfHID0(r30) ; Get HID0
505 lwz r11, pfHID1(r30) ; Get HID1
506
de355530 507 rlwinm. r0, r11, 0, hid1ps, hid1ps ; Isolate the hid1ps bit
9bccf70c 508 beq init750FXnb2 ; Clear BTIC if hid1ps set
de355530 509 rlwinm r13, r13, 0, btic+1, btic-1 ; Clear the BTIC bit
9bccf70c
A		 510
511init750FXnb2:
512 sync
513 mtspr hid0, r13 ; Set the HID
514 isync
515 sync
516
de355530 517 rlwinm r12, r11, 0, hid1ps+1, hid1ps-1 ; Select PLL0
9bccf70c 518 mtspr hid1, r12 ; Restore PLL config
de355530 519 mftb r13 ; Wait 5000 ticks (> 200 us)
9bccf70c
A		 520
521init750FXnbloop:
522 mftb r14
523 sub r14, r14, r13
524 cmpli cr0, r14, 5000
525 ble init750FXnbloop
526 mtspr hid1, r11 ; Select the desired PLL
527 blr
528
d12e1678
A		 529; 750FX vers 2.0 or later
530init750FXV2:
531 bf firstBoot, init750FXV2nb ; Wake from sleep
532
533 mfspr r11, hid2
534 stw r11, pfHID2(r30) ; Save the HID2 value
535 b init750FX ; Continue with 750FX init
536
537init750FXV2nb:
538 lwz r13, pfHID2(r30) ; Get HID2
539 rlwinm r13, r13, 0, hid2vmin+1, hid2vmin-1 ; Clear the vmin bit
540 mtspr hid2, r13 ; Restore HID2 value
541 sync ; Wait for it to be done
542 b init750FX
543
d52fe63f
A		 544; 7400
545
1c79356b
A		 546init7400: bf firstBoot,i7400nb ; Do different if not initial boot...
547 mfspr r13,l2cr ; Get the L2CR
548 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
549 bne+ i7400hl2 ; Yes...
550 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
551
552i7400hl2: lis r14,hi16(256*1024) ; Base L2 size
553 addis r15,r13,0x3000 ; Hah... Figure this one out...
554 rlwinm r15,r15,4,30,31
555 slw r14,r14,r15 ; Set 256KB, 512KB, 1MB, or 2MB
556
de355530 557 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
1c79356b
A		 558 stw r13,pfl2cr(r30) ; Shadow the L2CR
559 stw r14,pfl2Size(r30) ; Set the L2 size
560
561 mfspr r11,hid0 ; Get the current HID0
562 oris r11,r11,hi16(emcpm|eiecm) ; ?
563 mtspr hid0,r11 ; ?
564 isync
565 stw r11,pfHID0(r30) ; Save the HID0 value
566
567 mfspr r11,msscr0 ; Get the msscr0 register
568 stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
569 mfspr r11,msscr1 ; Get the msscr1 register
570 stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
43866e37 571
1c79356b
A		 572 blr ; Return...
573
765c9de3 574i7400nb:
d52fe63f 575 li r11,0
de355530 576 mtspr l2cr,r11 ; Make sure L2CR is zero
765c9de3 577 lwz r11,pfHID0(r30) ; Get HID0
1c79356b
A		 578 sync
579 mtspr hid0,r11 ; Set the HID
765c9de3
A		 580 isync
581 sync
1c79356b
A		 582 lwz r11,pfMSSCR0(r30) ; Get MSSCR0
583 isync
584 sync
585 mtspr msscr0,r11 ; Set the MSSCR0
586 lwz r11,pfMSSCR1(r30) ; Get msscr1
587 isync
588 sync
589 mtspr msscr1,r11 ; Set the msscr1
590 isync
591 sync
592 blr
9bccf70c
A		 593
594; 7400 (ver 2.0 - ver 2.7)
595
596init7400v2_7:
597 bf firstBoot, init7400
598 mfspr r13, hid0 ; Get the HID0
599 ori r13, r13, nopdstm ; ?
600 mtspr hid0, r13 ; Set the HID0
601 isync
602 sync
603 b init7400
604
1c79356b
A		 605; 7410
606; Note that this is the same as 7400 except we initialize the l2cr2 register
607
608init7410: li r13,0 ; Clear
609 mtspr 1016,r13 ; Turn off direct cache
610 b init7400 ; Join up with common....
1c79356b 611
d52fe63f
A		 612
613; 745X - Any 7450 family processor
614
615init745X:
de355530 616 bf firstBoot,init745Xnb ; Do different if not initial boot...
1c79356b
A		 617
618 mfspr r13,l2cr ; Get the L2CR
619 rlwinm. r0,r13,0,l2e,l2e ; Any L2?
d52fe63f 620 bne+ init745Xhl2 ; Yes...
1c79356b
A		 621 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
622
43866e37
A		 623init745Xhl2:
624 mfpvr r14 ; Get processor version
625 rlwinm r14,r14,16,16,31 ; Isolate processor version
626 cmpli cr0, r14, PROCESSOR_VERSION_7457
627 lis r14,hi16(512*1024) ; 512KB L2
628 beq init745Xhl2_2
629
630 lis r14,hi16(256*1024) ; Base L2 size
1c79356b
A		 631 rlwinm r15,r13,22,12,13 ; Convert to 256k, 512k, or 768k
632 add r14,r14,r15 ; Add in minimum
43866e37
A		 633
634init745Xhl2_2:
d52fe63f 635 stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
1c79356b
A		 636 stw r13,pfl2cr(r30) ; Shadow the L2CR
637 stw r14,pfl2Size(r30) ; Set the L2 size
638
639; Take care of level 3 cache
640
641 mfspr r13,l3cr ; Get the L3CR
7b1edb79 642 rlwinm. r0,r13,0,l3e,l3e ; Any L3?
d52fe63f 643 bne+ init745Xhl3 ; Yes...
7b1edb79 644 rlwinm r17,r17,0,pfL3b+1,pfL3b-1 ; No L3, turn off feature
1c79356b 645
de355530
A		 646init745Xhl3: cmplwi cr0,r13,0 ; No L3 if L3CR is zero
647 beq- init745Xnone ; Go turn off the features...
1c79356b
A		 648 lis r14,hi16(1024*1024) ; Base L3 size
649 rlwinm r15,r13,4,31,31 ; Get size multiplier
650 slw r14,r14,r15 ; Set 1 or 2MB
651
de355530 652 stw r13,pfl3crOriginal(r30) ; Shadow the L3CR
1c79356b
A		 653 stw r13,pfl3cr(r30) ; Shadow the L3CR
654 stw r14,pfl3Size(r30) ; Set the L3 size
d52fe63f 655 b init745Xfin ; Return....
1c79356b 656
d52fe63f 657init745Xnone:
de355530 658 rlwinm r17,r17,0,pfL3fab+1,pfL3b-1 ; No 3rd level cache or assist
0b4e3aa0
A		 659 rlwinm r11,r17,pfWillNapb-pfCanNapb,pfCanNapb,pfCanNapb ; Set pfCanNap if pfWillNap is set
660 or r17,r17,r11
1c79356b 661
d52fe63f 662init745Xfin:
de355530 663 rlwinm r17,r17,0,pfWillNapb+1,pfWillNapb-1 ; Make sure pfWillNap is not set
0b4e3aa0
A		 664
665 mfspr r11,hid0 ; Get the current HID0
1c79356b
A		 666 stw r11,pfHID0(r30) ; Save the HID0 value
667 mfspr r11,hid1 ; Get the current HID1
668 stw r11,pfHID1(r30) ; Save the HID1 value
669 mfspr r11,msscr0 ; Get the msscr0 register
670 stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
671 mfspr r11,msscr1 ; Get the msscr1 register
672 stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
673 mfspr r11,ictrl ; Get the ictrl register
674 stw r11,pfICTRL(r30) ; Save the ICTRL value
675 mfspr r11,ldstcr ; Get the ldstcr register
676 stw r11,pfLDSTCR(r30) ; Save the LDSTCR value
0b4e3aa0
A		 677 mfspr r11,ldstdb ; Get the ldstdb register
678 stw r11,pfLDSTDB(r30) ; Save the LDSTDB value
d52fe63f
A		 679 mfspr r11,pir ; Get the pir register
680 stw r11,pfBootConfig(r30) ; Save the BootConfig value
43866e37 681
1c79356b
A		 682 blr ; Return....
683
684
d52fe63f 685init745Xnb: lwz r11,pfHID0(r30) ; Get HID0
1c79356b
A		 686 sync
687 mtspr hid0,r11 ; Set the HID
688 isync
689 lwz r11,pfHID1(r30) ; Get HID1
690 sync
691 mtspr hid1,r11 ; Set the HID
692 isync
693 lwz r11,pfMSSCR0(r30) ; Get MSSCR0
694 sync
695 mtspr msscr0,r11 ; Set the MSSCR0
696 isync
697 sync
698 lwz r11,pfICTRL(r30) ; Get ICTRL
699 sync
700 mtspr ictrl,r11 ; Set the ICTRL
701 isync
702 sync
703 lwz r11,pfLDSTCR(r30) ; Get LDSTCR
704 sync
705 mtspr ldstcr,r11 ; Set the LDSTCR
706 isync
707 sync
0b4e3aa0
A		 708 lwz r11,pfLDSTDB(r30) ; Get LDSTDB
709 sync
710 mtspr ldstdb,r11 ; Set the LDSTDB
711 isync
712 sync
1c79356b
A		 713 blr
714
d52fe63f
A		 715; 7450 - Specific
716
717init7450:
718 bf firstBoot, init745X ; Not boot, use standard init
719
720 mfspr r13, pir ; Get BootConfig from PIR
721 rlwinm. r14, r13, 0, 20, 23 ; Is the pdet value zero
722 bne init7450done ; No, done for now
723
724 ori r13, r13, 0x0400 ; Force pdet value to 4
725 mtspr pir, r13 ; Write back the BootConfig
726
727init7450done:
728 b init745X ; Continue with standard init
729
1c79356b
A		 730
731;
732; Processor to feature table
733
734; .align 2 - Always on word boundary
735; .long ptFilter - Mask of significant bits in the Version/Revision code
736; - NOTE: Always order from most restrictive to least restrictive matching
737; .short ptVersion - Version code from PVR. Always start with 0 which is default
738; .short ptRevision - Revision code from PVR. A zero value denotes the generic attributes if not specific
739; .long ptFeatures - Available features
43866e37 740; .long ptCPUCap - Default value for _cpu_capabilities
1c79356b
A		 741; .long ptInitRout - Initilization routine. Can modify any of the other attributes.
742; .long ptRptdProc - Processor type reported
743; .long ptTempMax - Maximum operating temprature
744; .long ptTempThr - Temprature threshold. We throttle if above
745; .long ptLineSize - Level 1 cache line size
746; .long ptl1iSize - Level 1 instruction cache size
747; .long ptl1dSize - Level 1 data cache size
748
749 .align 2
750processor_types:
751
1c79356b
A		 752; 750 (ver 2.2)
753
43866e37
A		 754 .align 2
755 .long 0xFFFFFFFF ; Exact match
756 .short PROCESSOR_VERSION_750
757 .short 0x4202
758 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfL1i | pfL1d | pfL2
759 .long kCache32 | kHasGraphicsOps | kHasStfiwx
760 .long init750
761 .long CPU_SUBTYPE_POWERPC_750
762 .long 105
763 .long 90
764 .long 32
765 .long 32*1024
766 .long 32*1024
1c79356b
A		 767
768; 750CX (ver 2.x)
769
43866e37
A		 770 .align 2
771 .long 0xFFFF0F00 ; 2.x vers
772 .short PROCESSOR_VERSION_750
773 .short 0x0200
774 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfL1i | pfL1d | pfL2
775 .long kCache32 | kHasGraphicsOps | kHasStfiwx
776 .long init750CX
777 .long CPU_SUBTYPE_POWERPC_750
778 .long 105
779 .long 90
780 .long 32
781 .long 32*1024
782 .long 32*1024
de355530 783
1c79356b
A		 784; 750 (generic)
785
de355530
A		 786 .align 2
787 .long 0xFFFF0000 ; All revisions
788 .short PROCESSOR_VERSION_750
789 .short 0
790 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfThermal | pfL1i | pfL1d | pfL2
43866e37 791 .long kCache32 | kHasGraphicsOps | kHasStfiwx
de355530
A		 792 .long init750
793 .long CPU_SUBTYPE_POWERPC_750
794 .long 105
795 .long 90
796 .long 32
797 .long 32*1024
798 .long 32*1024
799
d12e1678
A		 800; 750FX (ver 1.x)
801
43866e37
A		 802 .align 2
803 .long 0xFFFF0F00 ; 1.x vers
804 .short PROCESSOR_VERSION_750FX
805 .short 0x0100
806 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pfL1i | pfL1d | pfL2
807 .long kCache32 | kHasGraphicsOps | kHasStfiwx
808 .long init750FX
809 .long CPU_SUBTYPE_POWERPC_750
810 .long 105
811 .long 90
812 .long 32
813 .long 32*1024
814 .long 32*1024
d12e1678 815
9bccf70c 816; 750FX (generic)
0b4e3aa0 817
43866e37
A		 818 .align 2
819 .long 0xFFFF0000 ; All revisions
820 .short PROCESSOR_VERSION_750FX
821 .short 0
822 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pfL1i | pfL1d | pfL2
823 .long kCache32 | kHasGraphicsOps | kHasStfiwx
824 .long init750FXV2
825 .long CPU_SUBTYPE_POWERPC_750
826 .long 105
827 .long 90
828 .long 32
829 .long 32*1024
830 .long 32*1024
de355530 831
9bccf70c
A		 832; 7400 (ver 2.0 - ver 2.7)
833
de355530
A		 834 .align 2
835 .long 0xFFFFFFF8 ; All revisions
836 .short PROCESSOR_VERSION_7400
837 .short 0x0200
838 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfThermal | pfL1i | pfL1d | pfL1fa | pfL2 | pfL2fa
43866e37 839 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
de355530
A		 840 .long init7400v2_7
841 .long CPU_SUBTYPE_POWERPC_7400
842 .long 105
843 .long 90
844 .long 32
845 .long 32*1024
846 .long 32*1024
847
1c79356b
A		 848; 7400 (generic)
849
de355530
A		 850 .align 2
851 .long 0xFFFF0000 ; All revisions
852 .short PROCESSOR_VERSION_7400
853 .short 0
854 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfThermal | pfL1i | pfL1d | pfL1fa | pfL2 | pfL2fa
43866e37 855 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
de355530
A		 856 .long init7400
857 .long CPU_SUBTYPE_POWERPC_7400
858 .long 105
859 .long 90
860 .long 32
861 .long 32*1024
862 .long 32*1024
863
1c79356b
A		 864; 7410 (ver 1.1)
865
de355530
A		 866 .align 2
867 .long 0xFFFFFFFF ; Exact match
868 .short PROCESSOR_VERSION_7400
869 .short 0x1101
870 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfL1i | pfL1d | pfL1fa | pfL2 | pfL2fa
43866e37 871 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
de355530
A		 872 .long init7410
873 .long CPU_SUBTYPE_POWERPC_7400
874 .long 105
875 .long 90
876 .long 32
877 .long 32*1024
878 .long 32*1024
1c79356b
A		 879
880; 7410 (generic)
881
de355530
A		 882 .align 2
883 .long 0xFFFF0000 ; All other revisions
884 .short PROCESSOR_VERSION_7410
885 .short 0
886 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfL1i | pfL1d | pfL1fa | pfL2 | pfL2fa
43866e37 887 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
de355530
A		 888 .long init7410
889 .long CPU_SUBTYPE_POWERPC_7400
890 .long 105
891 .long 90
892 .long 32
893 .long 32*1024
894 .long 32*1024
1c79356b
A		 895
896; 7450 (ver 1.xx)
897
de355530
A		 898 .align 2
899 .long 0xFFFFFF00 ; Just revisions 1.xx
900 .short PROCESSOR_VERSION_7450
901 .short 0x0100
902 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
43866e37 903 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
de355530
A		 904 .long init7450
905 .long CPU_SUBTYPE_POWERPC_7450
906 .long 105
907 .long 90
908 .long 32
909 .long 32*1024
910 .long 32*1024
1c79356b 911
0b4e3aa0
A		 912; 7450 (2.0)
913
de355530
A		 914 .align 2
915 .long 0xFFFFFFFF ; Just revision 2.0
916 .short PROCESSOR_VERSION_7450
917 .short 0x0200
918 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
43866e37 919 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
de355530
A		 920 .long init7450
921 .long CPU_SUBTYPE_POWERPC_7450
922 .long 105
923 .long 90
924 .long 32
925 .long 32*1024
926 .long 32*1024
0b4e3aa0
A		 927
928; 7450 (2.1)
1c79356b 929
de355530
A		 930 .align 2
931 .long 0xFFFF0000 ; All other revisions
932 .short PROCESSOR_VERSION_7450
933 .short 0
934 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
43866e37 935 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
de355530
A		 936 .long init7450
937 .long CPU_SUBTYPE_POWERPC_7450
938 .long 105
939 .long 90
940 .long 32
941 .long 32*1024
942 .long 32*1024
1c79356b 943
d52fe63f
A		 944; 7455 (1.xx) Just like 7450 2.0
945
de355530
A		 946 .align 2
947 .long 0xFFFFFF00 ; Just revisions 1.xx
948 .short PROCESSOR_VERSION_7455
949 .short 0x0100
950 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
43866e37 951 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
de355530
A		 952 .long init745X
953 .long CPU_SUBTYPE_POWERPC_7450
954 .long 105
955 .long 90
956 .long 32
957 .long 32*1024
958 .long 32*1024
d52fe63f
A		 959
960; 7455 (2.0)
961
de355530
A		 962 .align 2
963 .long 0xFFFFFFFF ; Just revision 2.0
964 .short PROCESSOR_VERSION_7455
965 .short 0x0200
966 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
43866e37 967 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
de355530
A		 968 .long init745X
969 .long CPU_SUBTYPE_POWERPC_7450
970 .long 105
971 .long 90
972 .long 32
973 .long 32*1024
974 .long 32*1024
d52fe63f
A		 975
976; 7455 (2.1)
977
de355530
A		 978 .align 2
979 .long 0xFFFF0000 ; All other revisions
980 .short PROCESSOR_VERSION_7455
981 .short 0
982 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
43866e37
A		 983 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
984 .long init745X
985 .long CPU_SUBTYPE_POWERPC_7450
986 .long 105
987 .long 90
988 .long 32
989 .long 32*1024
990 .long 32*1024
991
992; 7457
993
994 .align 2
995 .long 0xFFFF0000 ; All other revisions
996 .short PROCESSOR_VERSION_7457
997 .short 0
998 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
999 .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
de355530
A		 1000 .long init745X
1001 .long CPU_SUBTYPE_POWERPC_7450
1002 .long 105
1003 .long 90
1004 .long 32
1005 .long 32*1024
1006 .long 32*1024
1007
1008; Default dumb loser machine
1c79356b 1009
de355530
A		 1010 .align 2
1011 .long 0x00000000 ; Matches everything
1012 .short 0
1013 .short 0
1014 .long pfFloat | pfL1i | pfL1d
43866e37 1015 .long kCache32 | kHasGraphicsOps | kHasStfiwx
de355530
A		 1016 .long 0
1017 .long CPU_SUBTYPE_POWERPC_ALL
1018 .long 105
1019 .long 90
1020 .long 32
1021 .long 32*1024
1022 .long 32*1024
mirror of XNU