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2d21ac55
A		 1/*
2 * Copyright (c) 2004-2006 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28/*
29 * @OSF_COPYRIGHT@
30 */
31
32#ifndef _MACH_I386__STRUCTS_H_
33#define _MACH_I386__STRUCTS_H_
34
35/*
36 * i386 is the structure that is exported to user threads for
37 * use in status/mutate calls. This structure should never change.
38 *
39 */
40
41#if __DARWIN_UNIX03
42#define _STRUCT_X86_THREAD_STATE32 struct __darwin_i386_thread_state
43_STRUCT_X86_THREAD_STATE32
44{
45 unsigned int __eax;
46 unsigned int __ebx;
47 unsigned int __ecx;
48 unsigned int __edx;
49 unsigned int __edi;
50 unsigned int __esi;
51 unsigned int __ebp;
52 unsigned int __esp;
53 unsigned int __ss;
54 unsigned int __eflags;
55 unsigned int __eip;
56 unsigned int __cs;
57 unsigned int __ds;
58 unsigned int __es;
59 unsigned int __fs;
60 unsigned int __gs;
61};
62#else /* !__DARWIN_UNIX03 */
63#define _STRUCT_X86_THREAD_STATE32 struct i386_thread_state
64_STRUCT_X86_THREAD_STATE32
65{
66 unsigned int eax;
67 unsigned int ebx;
68 unsigned int ecx;
69 unsigned int edx;
70 unsigned int edi;
71 unsigned int esi;
72 unsigned int ebp;
73 unsigned int esp;
74 unsigned int ss;
75 unsigned int eflags;
76 unsigned int eip;
77 unsigned int cs;
78 unsigned int ds;
79 unsigned int es;
80 unsigned int fs;
81 unsigned int gs;
82};
83#endif /* !__DARWIN_UNIX03 */
84
85/* This structure should be double-word aligned for performance */
86
87#if __DARWIN_UNIX03
88#define _STRUCT_FP_CONTROL struct __darwin_fp_control
89_STRUCT_FP_CONTROL
90{
91 unsigned short __invalid :1,
92 __denorm :1,
93 __zdiv :1,
94 __ovrfl :1,
95 __undfl :1,
96 __precis :1,
97 :2,
98 __pc :2,
99#if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
100#define FP_PREC_24B 0
101#define FP_PREC_53B 2
102#define FP_PREC_64B 3
103#endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
104 __rc :2,
105#if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
106#define FP_RND_NEAR 0
107#define FP_RND_DOWN 1
108#define FP_RND_UP 2
109#define FP_CHOP 3
110#endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
111 /*inf*/ :1,
112 :3;
113};
114typedef _STRUCT_FP_CONTROL __darwin_fp_control_t;
115#else /* !__DARWIN_UNIX03 */
116#define _STRUCT_FP_CONTROL struct fp_control
117_STRUCT_FP_CONTROL
118{
119 unsigned short invalid :1,
120 denorm :1,
121 zdiv :1,
122 ovrfl :1,
123 undfl :1,
124 precis :1,
125 :2,
126 pc :2,
127#define FP_PREC_24B 0
128#define FP_PREC_53B 2
129#define FP_PREC_64B 3
130 rc :2,
131#define FP_RND_NEAR 0
132#define FP_RND_DOWN 1
133#define FP_RND_UP 2
134#define FP_CHOP 3
135 /*inf*/ :1,
136 :3;
137};
138typedef _STRUCT_FP_CONTROL fp_control_t;
139#endif /* !__DARWIN_UNIX03 */
140
141/*
142 * Status word.
143 */
144
145#if __DARWIN_UNIX03
146#define _STRUCT_FP_STATUS struct __darwin_fp_status
147_STRUCT_FP_STATUS
148{
149 unsigned short __invalid :1,
150 __denorm :1,
151 __zdiv :1,
152 __ovrfl :1,
153 __undfl :1,
154 __precis :1,
155 __stkflt :1,
156 __errsumm :1,
157 __c0 :1,
158 __c1 :1,
159 __c2 :1,
160 __tos :3,
161 __c3 :1,
162 __busy :1;
163};
164typedef _STRUCT_FP_STATUS __darwin_fp_status_t;
165#else /* !__DARWIN_UNIX03 */
166#define _STRUCT_FP_STATUS struct fp_status
167_STRUCT_FP_STATUS
168{
169 unsigned short invalid :1,
170 denorm :1,
171 zdiv :1,
172 ovrfl :1,
173 undfl :1,
174 precis :1,
175 stkflt :1,
176 errsumm :1,
177 c0 :1,
178 c1 :1,
179 c2 :1,
180 tos :3,
181 c3 :1,
182 busy :1;
183};
184typedef _STRUCT_FP_STATUS fp_status_t;
185#endif /* !__DARWIN_UNIX03 */
186
187/* defn of 80bit x87 FPU or MMX register */
188
189#if __DARWIN_UNIX03
190#define _STRUCT_MMST_REG struct __darwin_mmst_reg
191_STRUCT_MMST_REG
192{
193 char __mmst_reg[10];
194 char __mmst_rsrv[6];
195};
196#else /* !__DARWIN_UNIX03 */
197#define _STRUCT_MMST_REG struct mmst_reg
198_STRUCT_MMST_REG
199{
200 char mmst_reg[10];
201 char mmst_rsrv[6];
202};
203#endif /* !__DARWIN_UNIX03 */
204
205
206/* defn of 128 bit XMM regs */
207
208#if __DARWIN_UNIX03
209#define _STRUCT_XMM_REG struct __darwin_xmm_reg
210_STRUCT_XMM_REG
211{
212 char __xmm_reg[16];
213};
214#else /* !__DARWIN_UNIX03 */
215#define _STRUCT_XMM_REG struct xmm_reg
216_STRUCT_XMM_REG
217{
218 char xmm_reg[16];
219};
220#endif /* !__DARWIN_UNIX03 */
221
222/*
223 * Floating point state.
224 */
225
226#if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
227#define FP_STATE_BYTES 512 /* number of chars worth of data from fpu_fcw */
228#endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
229
230#if __DARWIN_UNIX03
231#define _STRUCT_X86_FLOAT_STATE32 struct __darwin_i386_float_state
232_STRUCT_X86_FLOAT_STATE32
233{
234 int __fpu_reserved[2];
235 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
236 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
237 __uint8_t __fpu_ftw; /* x87 FPU tag word */
238 __uint8_t __fpu_rsrv1; /* reserved */
239 __uint16_t __fpu_fop; /* x87 FPU Opcode */
240 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
241 __uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
242 __uint16_t __fpu_rsrv2; /* reserved */
243 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
244 __uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
245 __uint16_t __fpu_rsrv3; /* reserved */
246 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
247 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
248 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
249 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
250 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
251 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
252 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
253 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
254 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
255 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
256 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
257 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
258 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
259 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
260 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
261 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
262 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
263 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
264 char __fpu_rsrv4[14*16]; /* reserved */
265 int __fpu_reserved1;
266};
060df5ea
A		 267
268#define _STRUCT_X86_AVX_STATE32 struct __darwin_i386_avx_state
269_STRUCT_X86_AVX_STATE32
270{
271 int __fpu_reserved[2];
272 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
273 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
274 __uint8_t __fpu_ftw; /* x87 FPU tag word */
275 __uint8_t __fpu_rsrv1; /* reserved */
276 __uint16_t __fpu_fop; /* x87 FPU Opcode */
277 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
278 __uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
279 __uint16_t __fpu_rsrv2; /* reserved */
280 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
281 __uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
282 __uint16_t __fpu_rsrv3; /* reserved */
283 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
284 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
285 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
286 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
287 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
288 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
289 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
290 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
291 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
292 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
293 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
294 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
295 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
296 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
297 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
298 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
299 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
300 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
301 char __fpu_rsrv4[14*16]; /* reserved */
302 int __fpu_reserved1;
303 char __avx_reserved1[64];
304 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
305 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
306 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
307 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
308 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
309 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
310 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
311 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
312};
313
2d21ac55
A		 314#else /* !__DARWIN_UNIX03 */
315#define _STRUCT_X86_FLOAT_STATE32 struct i386_float_state
316_STRUCT_X86_FLOAT_STATE32
317{
318 int fpu_reserved[2];
319 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
320 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
321 __uint8_t fpu_ftw; /* x87 FPU tag word */
322 __uint8_t fpu_rsrv1; /* reserved */
323 __uint16_t fpu_fop; /* x87 FPU Opcode */
324 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
325 __uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
326 __uint16_t fpu_rsrv2; /* reserved */
327 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
328 __uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
329 __uint16_t fpu_rsrv3; /* reserved */
330 __uint32_t fpu_mxcsr; /* MXCSR Register state */
331 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
332 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
333 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
334 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
335 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
336 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
337 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
338 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
339 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
340 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
341 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
342 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
343 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
344 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
345 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
346 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
347 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
348 char fpu_rsrv4[14*16]; /* reserved */
349 int fpu_reserved1;
350};
060df5ea
A		 351
352#define _STRUCT_X86_AVX_STATE32 struct i386_avx_state
353_STRUCT_X86_AVX_STATE32
354{
355 int fpu_reserved[2];
356 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
357 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
358 __uint8_t fpu_ftw; /* x87 FPU tag word */
359 __uint8_t fpu_rsrv1; /* reserved */
360 __uint16_t fpu_fop; /* x87 FPU Opcode */
361 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
362 __uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
363 __uint16_t fpu_rsrv2; /* reserved */
364 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
365 __uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
366 __uint16_t fpu_rsrv3; /* reserved */
367 __uint32_t fpu_mxcsr; /* MXCSR Register state */
368 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
369 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
370 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
371 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
372 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
373 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
374 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
375 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
376 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
377 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
378 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
379 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
380 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
381 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
382 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
383 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
384 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
385 char fpu_rsrv4[14*16]; /* reserved */
386 int fpu_reserved1;
387 char __avx_reserved1[64];
388 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
389 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
390 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
391 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
392 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
393 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
394 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
395 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
396};
397
2d21ac55
A		 398#endif /* !__DARWIN_UNIX03 */
399
400#if __DARWIN_UNIX03
401#define _STRUCT_X86_EXCEPTION_STATE32 struct __darwin_i386_exception_state
402_STRUCT_X86_EXCEPTION_STATE32
403{
6d2010ae
A		 404 __uint16_t __trapno;
405 __uint16_t __cpu;
406 __uint32_t __err;
407 __uint32_t __faultvaddr;
2d21ac55
A		 408};
409#else /* !__DARWIN_UNIX03 */
410#define _STRUCT_X86_EXCEPTION_STATE32 struct i386_exception_state
411_STRUCT_X86_EXCEPTION_STATE32
412{
6d2010ae
A		 413 __uint16_t trapno;
414 __uint16_t cpu;
415 __uint32_t err;
416 __uint32_t faultvaddr;
2d21ac55
A		 417};
418#endif /* !__DARWIN_UNIX03 */
419
420#if __DARWIN_UNIX03
421#define _STRUCT_X86_DEBUG_STATE32 struct __darwin_x86_debug_state32
422_STRUCT_X86_DEBUG_STATE32
423{
424 unsigned int __dr0;
425 unsigned int __dr1;
426 unsigned int __dr2;
427 unsigned int __dr3;
428 unsigned int __dr4;
429 unsigned int __dr5;
430 unsigned int __dr6;
431 unsigned int __dr7;
432};
433#else /* !__DARWIN_UNIX03 */
434#define _STRUCT_X86_DEBUG_STATE32 struct x86_debug_state32
435_STRUCT_X86_DEBUG_STATE32
436{
437 unsigned int dr0;
438 unsigned int dr1;
439 unsigned int dr2;
440 unsigned int dr3;
441 unsigned int dr4;
442 unsigned int dr5;
443 unsigned int dr6;
444 unsigned int dr7;
445};
446#endif /* !__DARWIN_UNIX03 */
447
448/*
449 * 64 bit versions of the above
450 */
451
452#if __DARWIN_UNIX03
453#define _STRUCT_X86_THREAD_STATE64 struct __darwin_x86_thread_state64
454_STRUCT_X86_THREAD_STATE64
455{
456 __uint64_t __rax;
457 __uint64_t __rbx;
458 __uint64_t __rcx;
459 __uint64_t __rdx;
460 __uint64_t __rdi;
461 __uint64_t __rsi;
462 __uint64_t __rbp;
463 __uint64_t __rsp;
464 __uint64_t __r8;
465 __uint64_t __r9;
466 __uint64_t __r10;
467 __uint64_t __r11;
468 __uint64_t __r12;
469 __uint64_t __r13;
470 __uint64_t __r14;
471 __uint64_t __r15;
472 __uint64_t __rip;
473 __uint64_t __rflags;
474 __uint64_t __cs;
475 __uint64_t __fs;
476 __uint64_t __gs;
477};
478#else /* !__DARWIN_UNIX03 */
479#define _STRUCT_X86_THREAD_STATE64 struct x86_thread_state64
480_STRUCT_X86_THREAD_STATE64
481{
482 __uint64_t rax;
483 __uint64_t rbx;
484 __uint64_t rcx;
485 __uint64_t rdx;
486 __uint64_t rdi;
487 __uint64_t rsi;
488 __uint64_t rbp;
489 __uint64_t rsp;
490 __uint64_t r8;
491 __uint64_t r9;
492 __uint64_t r10;
493 __uint64_t r11;
494 __uint64_t r12;
495 __uint64_t r13;
496 __uint64_t r14;
497 __uint64_t r15;
498 __uint64_t rip;
499 __uint64_t rflags;
500 __uint64_t cs;
501 __uint64_t fs;
502 __uint64_t gs;
503};
504#endif /* !__DARWIN_UNIX03 */
505
506
507#if __DARWIN_UNIX03
508#define _STRUCT_X86_FLOAT_STATE64 struct __darwin_x86_float_state64
509_STRUCT_X86_FLOAT_STATE64
510{
511 int __fpu_reserved[2];
512 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
513 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
514 __uint8_t __fpu_ftw; /* x87 FPU tag word */
515 __uint8_t __fpu_rsrv1; /* reserved */
516 __uint16_t __fpu_fop; /* x87 FPU Opcode */
517
518 /* x87 FPU Instruction Pointer */
519 __uint32_t __fpu_ip; /* offset */
520 __uint16_t __fpu_cs; /* Selector */
521
522 __uint16_t __fpu_rsrv2; /* reserved */
523
524 /* x87 FPU Instruction Operand(Data) Pointer */
525 __uint32_t __fpu_dp; /* offset */
526 __uint16_t __fpu_ds; /* Selector */
527
528 __uint16_t __fpu_rsrv3; /* reserved */
529 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
530 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
531 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
532 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
533 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
534 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
535 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
536 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
537 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
538 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
539 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
540 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
541 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
542 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
543 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
544 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
545 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
546 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
547 _STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
548 _STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
549 _STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
550 _STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
551 _STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
552 _STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
553 _STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
554 _STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
555 char __fpu_rsrv4[6*16]; /* reserved */
556 int __fpu_reserved1;
557};
060df5ea
A		 558
559#define _STRUCT_X86_AVX_STATE64 struct __darwin_x86_avx_state64
560_STRUCT_X86_AVX_STATE64
561{
562 int __fpu_reserved[2];
563 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
564 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
565 __uint8_t __fpu_ftw; /* x87 FPU tag word */
566 __uint8_t __fpu_rsrv1; /* reserved */
567 __uint16_t __fpu_fop; /* x87 FPU Opcode */
568
569 /* x87 FPU Instruction Pointer */
570 __uint32_t __fpu_ip; /* offset */
571 __uint16_t __fpu_cs; /* Selector */
572
573 __uint16_t __fpu_rsrv2; /* reserved */
574
575 /* x87 FPU Instruction Operand(Data) Pointer */
576 __uint32_t __fpu_dp; /* offset */
577 __uint16_t __fpu_ds; /* Selector */
578
579 __uint16_t __fpu_rsrv3; /* reserved */
580 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
581 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
582 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
583 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
584 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
585 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
586 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
587 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
588 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
589 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
590 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
591 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
592 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
593 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
594 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
595 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
596 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
597 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
598 _STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
599 _STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
600 _STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
601 _STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
602 _STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
603 _STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
604 _STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
605 _STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
606 char __fpu_rsrv4[6*16]; /* reserved */
607 int __fpu_reserved1;
608 char __avx_reserved1[64];
609 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
610 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
611 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
612 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
613 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
614 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
615 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
616 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
617 _STRUCT_XMM_REG __fpu_ymmh8; /* YMMH 8 */
618 _STRUCT_XMM_REG __fpu_ymmh9; /* YMMH 9 */
619 _STRUCT_XMM_REG __fpu_ymmh10; /* YMMH 10 */
620 _STRUCT_XMM_REG __fpu_ymmh11; /* YMMH 11 */
621 _STRUCT_XMM_REG __fpu_ymmh12; /* YMMH 12 */
622 _STRUCT_XMM_REG __fpu_ymmh13; /* YMMH 13 */
623 _STRUCT_XMM_REG __fpu_ymmh14; /* YMMH 14 */
624 _STRUCT_XMM_REG __fpu_ymmh15; /* YMMH 15 */
625};
626
2d21ac55
A		 627#else /* !__DARWIN_UNIX03 */
628#define _STRUCT_X86_FLOAT_STATE64 struct x86_float_state64
629_STRUCT_X86_FLOAT_STATE64
630{
631 int fpu_reserved[2];
632 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
633 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
634 __uint8_t fpu_ftw; /* x87 FPU tag word */
635 __uint8_t fpu_rsrv1; /* reserved */
636 __uint16_t fpu_fop; /* x87 FPU Opcode */
637
638 /* x87 FPU Instruction Pointer */
639 __uint32_t fpu_ip; /* offset */
640 __uint16_t fpu_cs; /* Selector */
641
642 __uint16_t fpu_rsrv2; /* reserved */
643
644 /* x87 FPU Instruction Operand(Data) Pointer */
645 __uint32_t fpu_dp; /* offset */
646 __uint16_t fpu_ds; /* Selector */
647
648 __uint16_t fpu_rsrv3; /* reserved */
649 __uint32_t fpu_mxcsr; /* MXCSR Register state */
650 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
651 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
652 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
653 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
654 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
655 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
656 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
657 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
658 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
659 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
660 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
661 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
662 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
663 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
664 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
665 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
666 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
667 _STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
668 _STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
669 _STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
670 _STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
671 _STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
672 _STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
673 _STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
674 _STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
675 char fpu_rsrv4[6*16]; /* reserved */
676 int fpu_reserved1;
677};
060df5ea
A		 678
679#define _STRUCT_X86_AVX_STATE64 struct x86_avx_state64
680_STRUCT_X86_AVX_STATE64
681{
682 int fpu_reserved[2];
683 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
684 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
685 __uint8_t fpu_ftw; /* x87 FPU tag word */
686 __uint8_t fpu_rsrv1; /* reserved */
687 __uint16_t fpu_fop; /* x87 FPU Opcode */
688
689 /* x87 FPU Instruction Pointer */
690 __uint32_t fpu_ip; /* offset */
691 __uint16_t fpu_cs; /* Selector */
692
693 __uint16_t fpu_rsrv2; /* reserved */
694
695 /* x87 FPU Instruction Operand(Data) Pointer */
696 __uint32_t fpu_dp; /* offset */
697 __uint16_t fpu_ds; /* Selector */
698
699 __uint16_t fpu_rsrv3; /* reserved */
700 __uint32_t fpu_mxcsr; /* MXCSR Register state */
701 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
702 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
703 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
704 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
705 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
706 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
707 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
708 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
709 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
710 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
711 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
712 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
713 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
714 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
715 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
716 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
717 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
718 _STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
719 _STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
720 _STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
721 _STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
722 _STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
723 _STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
724 _STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
725 _STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
726 char fpu_rsrv4[6*16]; /* reserved */
727 int fpu_reserved1;
728 char __avx_reserved1[64];
729 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
730 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
731 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
732 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
733 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
734 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
735 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
736 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
737 _STRUCT_XMM_REG __fpu_ymmh8; /* YMMH 8 */
738 _STRUCT_XMM_REG __fpu_ymmh9; /* YMMH 9 */
739 _STRUCT_XMM_REG __fpu_ymmh10; /* YMMH 10 */
740 _STRUCT_XMM_REG __fpu_ymmh11; /* YMMH 11 */
741 _STRUCT_XMM_REG __fpu_ymmh12; /* YMMH 12 */
742 _STRUCT_XMM_REG __fpu_ymmh13; /* YMMH 13 */
743 _STRUCT_XMM_REG __fpu_ymmh14; /* YMMH 14 */
744 _STRUCT_XMM_REG __fpu_ymmh15; /* YMMH 15 */
745};
746
2d21ac55
A		 747#endif /* !__DARWIN_UNIX03 */
748
749#if __DARWIN_UNIX03
750#define _STRUCT_X86_EXCEPTION_STATE64 struct __darwin_x86_exception_state64
751_STRUCT_X86_EXCEPTION_STATE64
752{
6d2010ae
A		 753 __uint16_t __trapno;
754 __uint16_t __cpu;
755 __uint32_t __err;
756 __uint64_t __faultvaddr;
2d21ac55
A		 757};
758#else /* !__DARWIN_UNIX03 */
759#define _STRUCT_X86_EXCEPTION_STATE64 struct x86_exception_state64
760_STRUCT_X86_EXCEPTION_STATE64
761{
6d2010ae
A		 762 __uint16_t trapno;
763 __uint16_t cpu;
764 __uint32_t err;
765 __uint64_t faultvaddr;
2d21ac55
A		 766};
767#endif /* !__DARWIN_UNIX03 */
768
769#if __DARWIN_UNIX03
770#define _STRUCT_X86_DEBUG_STATE64 struct __darwin_x86_debug_state64
771_STRUCT_X86_DEBUG_STATE64
772{
773 __uint64_t __dr0;
774 __uint64_t __dr1;
775 __uint64_t __dr2;
776 __uint64_t __dr3;
777 __uint64_t __dr4;
778 __uint64_t __dr5;
779 __uint64_t __dr6;
780 __uint64_t __dr7;
781};
782#else /* !__DARWIN_UNIX03 */
783#define _STRUCT_X86_DEBUG_STATE64 struct x86_debug_state64
784_STRUCT_X86_DEBUG_STATE64
785{
786 __uint64_t dr0;
787 __uint64_t dr1;
788 __uint64_t dr2;
789 __uint64_t dr3;
790 __uint64_t dr4;
791 __uint64_t dr5;
792 __uint64_t dr6;
793 __uint64_t dr7;
794};
795#endif /* !__DARWIN_UNIX03 */
796
797#endif /* _MACH_I386__STRUCTS_H_ */
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