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1c79356b 1/*
2d21ac55 2 * Copyright (c) 2000-2007 Apple Computer, Inc. All rights reserved.
1c79356b 3 *
2d21ac55 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
1c79356b 5 *
2d21ac55
A		 6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
8f6c56a5 14 *
2d21ac55
A		 15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5
A		 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55
A		 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
8f6c56a5 25 *
2d21ac55 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
1c79356b
A		 27 */
28/*
29 * @OSF_COPYRIGHT@
30 */
31
32/* Miscellaneous constants and structures used by the exception
33 * handlers
34 */
35
36#ifndef _PPC_EXCEPTION_H_
37#define _PPC_EXCEPTION_H_
38
9bccf70c
A		 39#include <ppc/savearea.h>
40
1c79356b
A		 41#ifndef ASSEMBLER
42
1c79356b
A		 43#include <mach_kdb.h>
44#include <mach_kdp.h>
45
46#include <mach/machine/vm_types.h>
47#include <mach/boolean.h>
91447636 48#include <kern/ast.h>
9bccf70c 49#include <kern/cpu_data.h>
0c530ab8 50#include <kern/pms.h>
1c79356b
A		 51#include <pexpert/pexpert.h>
52#include <IOKit/IOInterrupts.h>
53#include <ppc/machine_routines.h>
3a60a9f5 54#include <ppc/rtclock.h>
1c79356b
A		 55
56/* Per processor CPU features */
55e303ae 57#pragma pack(4) /* Make sure the structure stays as we defined it */
1c79356b 58struct procFeatures {
55e303ae 59 unsigned int Available; /* 0x000 */
1c79356b
A		 60#define pfFloat 0x80000000
61#define pfFloatb 0
62#define pfAltivec 0x40000000
63#define pfAltivecb 1
64#define pfAvJava 0x20000000
65#define pfAvJavab 2
66#define pfSMPcap 0x10000000
67#define pfSMPcapb 3
68#define pfCanSleep 0x08000000
69#define pfCanSleepb 4
70#define pfCanNap 0x04000000
71#define pfCanNapb 5
72#define pfCanDoze 0x02000000
73#define pfCanDozeb 6
55e303ae
A		 74#define pfSlowNap 0x00400000
75#define pfSlowNapb 9
76#define pfNoMuMMCK 0x00200000
77#define pfNoMuMMCKb 10
78#define pfNoL2PFNap 0x00100000
79#define pfNoL2PFNapb 11
80#define pfSCOMFixUp 0x00080000
81#define pfSCOMFixUpb 12
82#define pfHasDcba 0x00040000
83#define pfHasDcbab 13
84#define pfL1fa 0x00010000
85#define pfL1fab 15
86#define pfL2 0x00008000
87#define pfL2b 16
88#define pfL2fa 0x00004000
89#define pfL2fab 17
90#define pfL2i 0x00002000
91#define pfL2ib 18
0b4e3aa0
A		 92#define pfLClck 0x00001000
93#define pfLClckb 19
1c79356b
A		 94#define pfWillNap 0x00000800
95#define pfWillNapb 20
96#define pfNoMSRir 0x00000400
97#define pfNoMSRirb 21
7b1edb79
A		 98#define pfL3pdet 0x00000200
99#define pfL3pdetb 22
55e303ae
A		 100#define pf128Byte 0x00000080
101#define pf128Byteb 24
102#define pf32Byte 0x00000020
103#define pf32Byteb 26
104#define pf64Bit 0x00000010
105#define pf64Bitb 27
1c79356b
A		 106#define pfL3 0x00000004
107#define pfL3b 29
108#define pfL3fa 0x00000002
109#define pfL3fab 30
110#define pfValid 0x00000001
111#define pfValidb 31
55e303ae
A		 112 unsigned short rptdProc; /* 0x004 */
113 unsigned short lineSize; /* 0x006 */
114 unsigned int l1iSize; /* 0x008 */
115 unsigned int l1dSize; /* 0x00C */
116 unsigned int l2cr; /* 0x010 */
117 unsigned int l2Size; /* 0x014 */
118 unsigned int l3cr; /* 0x018 */
119 unsigned int l3Size; /* 0x01C */
120 unsigned int pfMSSCR0; /* 0x020 */
121 unsigned int pfMSSCR1; /* 0x024 */
122 unsigned int pfICTRL; /* 0x028 */
123 unsigned int pfLDSTCR; /* 0x02C */
124 unsigned int pfLDSTDB; /* 0x030 */
125 unsigned int pfMaxVAddr; /* 0x034 */
126 unsigned int pfMaxPAddr; /* 0x038 */
127 unsigned int pfPTEG; /* 0x03C */
128 uint64_t pfHID0; /* 0x040 */
129 uint64_t pfHID1; /* 0x048 */
130 uint64_t pfHID2; /* 0x050 */
131 uint64_t pfHID3; /* 0x058 */
132 uint64_t pfHID4; /* 0x060 */
133 uint64_t pfHID5; /* 0x068 */
134 unsigned int l2crOriginal; /* 0x070 */
135 unsigned int l3crOriginal; /* 0x074 */
4a249263
A		 136 unsigned int pfBootConfig; /* 0x078 */
137 unsigned int pfPowerModes; /* 0x07C */
138#define pmDPLLVmin 0x00010000
139#define pmDPLLVminb 15
3a60a9f5
A		 140#define pmType 0x000000FF
141#define pmPowerTune 0x00000003
e5568f75 142#define pmDFS 0x00000002
4a249263 143#define pmDualPLL 0x00000001
483a1d10
A		 144 unsigned int pfPowerTune0; /* 0x080 */
145 unsigned int pfPowerTune1; /* 0x084 */
146 unsigned int rsrvd88[6]; /* 0x088 */
1c79356b 147};
55e303ae 148#pragma pack()
1c79356b
A		 149
150typedef struct procFeatures procFeatures;
151
1c79356b 152
55e303ae
A		 153/*
154 *
155 * Various performance counters
156 */
157#pragma pack(4) /* Make sure the structure stays as we defined it */
158struct hwCtrs {
159
160 unsigned int hwInVains; /* In vain */
161 unsigned int hwResets; /* Reset */
162 unsigned int hwMachineChecks; /* Machine check */
163 unsigned int hwDSIs; /* DSIs */
164 unsigned int hwISIs; /* ISIs */
165 unsigned int hwExternals; /* Externals */
166 unsigned int hwAlignments; /* Alignment */
167 unsigned int hwPrograms; /* Program */
168 unsigned int hwFloatPointUnavailable; /* Floating point */
169 unsigned int hwDecrementers; /* Decrementer */
170 unsigned int hwIOErrors; /* I/O error */
171 unsigned int hwrsvd0; /* Reserved */
172 unsigned int hwSystemCalls; /* System call */
173 unsigned int hwTraces; /* Trace */
174 unsigned int hwFloatingPointAssists; /* Floating point assist */
175 unsigned int hwPerformanceMonitors; /* Performance monitor */
176 unsigned int hwAltivecs; /* VMX */
177 unsigned int hwrsvd1; /* Reserved */
178 unsigned int hwrsvd2; /* Reserved */
179 unsigned int hwrsvd3; /* Reserved */
180 unsigned int hwInstBreakpoints; /* Instruction breakpoint */
181 unsigned int hwSystemManagements; /* System management */
182 unsigned int hwAltivecAssists; /* Altivec Assist */
183 unsigned int hwThermal; /* Thermals */
184 unsigned int hwrsvd5; /* Reserved */
185 unsigned int hwrsvd6; /* Reserved */
186 unsigned int hwrsvd7; /* Reserved */
187 unsigned int hwrsvd8; /* Reserved */
188 unsigned int hwrsvd9; /* Reserved */
189 unsigned int hwrsvd10; /* Reserved */
190 unsigned int hwrsvd11; /* Reserved */
191 unsigned int hwrsvd12; /* Reserved */
192 unsigned int hwrsvd13; /* Reserved */
193 unsigned int hwTrace601; /* Trace */
194 unsigned int hwSIGPs; /* SIGP */
195 unsigned int hwPreemptions; /* Preemption */
196 unsigned int hwContextSwitchs; /* Context switch */
197 unsigned int hwShutdowns; /* Shutdowns */
198 unsigned int hwChokes; /* System ABENDs */
199 unsigned int hwDataSegments; /* Data Segment Interruptions */
200 unsigned int hwInstructionSegments; /* Instruction Segment Interruptions */
201 unsigned int hwSoftPatches; /* Soft Patch interruptions */
202 unsigned int hwMaintenances; /* Maintenance interruptions */
203 unsigned int hwInstrumentations; /* Instrumentation interruptions */
a3d08fcd
A		 204 unsigned int hwrsvd14; /* Reserved */
205 unsigned int hwhdec; /* 0B4 Hypervisor decrementer */
206
207 unsigned int hwspare0[11]; /* 0B8 Reserved */
208 unsigned int hwspare0a; /* 0E4 Reserved */
209 unsigned int hwspare0b; /* 0E8 Reserved */
210 unsigned int hwspare0c; /* 0EC Reserved */
211 unsigned int hwspare0d; /* 0F0 Reserved */
212 unsigned int hwIgnored; /* 0F4 Interruptions ignored */
213 unsigned int hwRedrives; /* 0F8 Number of redriven interrupts */
214 unsigned int hwSteals; /* 0FC Steals */
215/* 100 */
55e303ae
A		 216
217 unsigned int hwMckHang; /* ? */
218 unsigned int hwMckSLBPE; /* ? */
219 unsigned int hwMckTLBPE; /* ? */
220 unsigned int hwMckERCPE; /* ? */
221 unsigned int hwMckL1DPE; /* ? */
222 unsigned int hwMckL1TPE; /* ? */
223 unsigned int hwMckUE; /* ? */
224 unsigned int hwMckIUE; /* ? */
225 unsigned int hwMckIUEr; /* ? */
226 unsigned int hwMckDUE; /* ? */
227 unsigned int hwMckDTW; /* ? */
228 unsigned int hwMckUnk; /* ? */
229 unsigned int hwMckExt; /* ? */
230 unsigned int hwMckICachePE; /* ? */
231 unsigned int hwMckITagPE; /* ? */
232 unsigned int hwMckIEratPE; /* ? */
233 unsigned int hwMckDEratPE; /* ? */
234 unsigned int hwspare2[15]; /* Pad to next 128 bndry */
235/* 0x180 */
236
237 unsigned int napStamp[2]; /* Time base when we napped */
238 unsigned int napTotal[2]; /* Total nap time in ticks */
239 unsigned int numSIGPast; /* Number of SIGP asts recieved */
240 unsigned int numSIGPcpureq; /* Number of SIGP cpu requests recieved */
241 unsigned int numSIGPdebug; /* Number of SIGP debugs recieved */
242 unsigned int numSIGPwake; /* Number of SIGP wakes recieved */
243 unsigned int numSIGPtimo; /* Number of SIGP send timeouts */
244 unsigned int numSIGPmast; /* Number of SIGPast messages merged */
245 unsigned int numSIGPmwake; /* Number of SIGPwake messages merged */
91447636
A		 246
247 unsigned int hwWalkPhys; /* Number of entries to hw_walk_phys */
248 unsigned int hwWalkFull; /* Full purge of connected PTE's */
249 unsigned int hwWalkMerge; /* RC merge of connected PTE's */
250 unsigned int hwWalkQuick; /* Quick scan of connected PTE's */
a3d08fcd 251 unsigned int numSIGPcall; /* Number of SIGPcall messages received */
55e303ae 252
91447636 253 unsigned int hwspare3[16]; /* Pad to 512 */
55e303ae
A		 254
255};
256#pragma pack()
257
258typedef struct hwCtrs hwCtrs;
259
260struct patch_entry {
261 unsigned int *addr;
262 unsigned int data;
263 unsigned int type;
264 unsigned int value;
265};
266
267typedef struct patch_entry patch_entry_t;
268
269#define PATCH_INVALID 0
270#define PATCH_PROCESSOR 1
271#define PATCH_FEATURE 2
91447636 272#define PATCH_END_OF_TABLE 3
55e303ae
A		 273
274#define PatchExt32 0x80000000
275#define PatchExt32b 0
276#define PatchLwsync 0x40000000
277#define PatchLwsyncb 1
278
1c79356b
A		 279/* When an exception is taken, this info is accessed via sprg0 */
280/* We should always have this one on a cache line boundary */
55e303ae
A		 281
282#pragma pack(4) /* Make sure the structure stays as we defined it */
1c79356b
A		 283struct per_proc_info {
284 unsigned short cpu_number;
285 unsigned short cpu_flags; /* Various low-level flags */
286 vm_offset_t istackptr;
287 vm_offset_t intstack_top_ss;
288
1c79356b
A		 289 vm_offset_t debstackptr;
290 vm_offset_t debstack_top_ss;
1c79356b 291
55e303ae 292 unsigned int spcFlags; /* Special thread flags */
1c79356b 293 unsigned int old_thread;
91447636 294 ast_t pending_ast; /* mask of pending ast(s) */
1c79356b
A		 295
296 /* PPC cache line boundary here - 020 */
297
91447636
A		 298 int cpu_type;
299 int cpu_subtype;
300 int cpu_threadtype;
1c79356b
A		 301/*
302 * Note: the following two pairs of words need to stay in order and each pair must
303 * be in the same reservation (line) granule
304 */
55e303ae
A		 305 struct facility_context *FPU_owner; /* Owner of the FPU on this cpu */
306 unsigned int liveVRSave; /* VRSave assiciated with live vector registers */
307 struct facility_context *VMX_owner; /* Owner of the VMX on this cpu */
91447636
A		 308 unsigned int spcTRc; /* Special trace count */
309 unsigned int spcTRp; /* Special trace buffer pointer */
1c79356b
A		 310
311 /* PPC cache line boundary here - 040 */
55e303ae
A		 312 addr64_t quickfret; /* List of saveareas to release */
313 addr64_t lclfree; /* Pointer to local savearea list */
9bccf70c 314 unsigned int lclfreecnt; /* Entries in local savearea list */
91447636
A		 315 unsigned int holdQFret; /* Hold off releasing quickfret list */
316 uint64_t rtcPop; /* Real Time Clock pop */
1c79356b
A		 317
318 /* PPC cache line boundary here - 060 */
0b4e3aa0 319 boolean_t interrupts_enabled;
1c79356b
A		 320 IOInterruptHandler interrupt_handler;
321 void * interrupt_nub;
322 unsigned int interrupt_source;
323 void * interrupt_target;
324 void * interrupt_refCon;
55e303ae 325 uint64_t next_savearea; /* pointer to the next savearea */
1c79356b
A		 326
327 /* PPC cache line boundary here - 080 */
328 unsigned int MPsigpStat; /* Signal Processor status (interlocked update for this one) */
9bccf70c 329#define MPsigpMsgp 0xC0000000 /* Message pending (busy + pass ) */
1c79356b
A		 330#define MPsigpBusy 0x80000000 /* Processor area busy, i.e., locked */
331#define MPsigpPass 0x40000000 /* Busy lock passed to receiving processor */
9bccf70c 332#define MPsigpAck 0x20000000 /* Ack Busy lock passed to receiving processor */
1c79356b
A		 333#define MPsigpSrc 0x000000FF /* Processor that owns busy, i.e., the ID of */
334 /* whomever set busy. When a busy is passed, */
335 /* this is the requestor of the function. */
336#define MPsigpFunc 0x0000FF00 /* Current function */
337#define MPsigpIdle 0x00 /* No function pending */
338#define MPsigpSigp 0x04 /* Signal a processor */
1c79356b
A		 339 unsigned int MPsigpParm0; /* SIGP parm 0 */
340 unsigned int MPsigpParm1; /* SIGP parm 1 */
341 unsigned int MPsigpParm2; /* SIGP parm 2 */
342 cpu_id_t cpu_id;
343 vm_offset_t start_paddr;
344 unsigned int ruptStamp[2]; /* Timebase at last interruption */
345
346 /* PPC cache line boundary here - 0A0 */
347 procFeatures pf; /* Processor features */
348
0b4e3aa0 349 /* PPC cache line boundary here - 140 */
91447636
A		 350 void * pp_cbfr;
351 void * pp_chud;
0c530ab8 352 uint64_t rtclock_intr_deadline;
3a60a9f5 353 rtclock_timer_t rtclock_timer;
91447636
A		 354 unsigned int ppbbTaskEnv; /* BlueBox Task Environment */
355
1c79356b 356 /* PPC cache line boundary here - 160 */
91447636 357 struct savearea * db_saved_state;
55e303ae 358 time_base_enable_t time_base_enable;
2d21ac55 359 uint32_t ppXFlags;
91447636
A		 360 int running;
361 int debugger_is_slave;
362 int debugger_active;
363 int debugger_pending;
2d21ac55 364 uint32_t debugger_holdoff;
1c79356b
A		 365
366 /* PPC cache line boundary here - 180 */
91447636 367 uint64_t Uassist; /* User Assist DoubleWord */
55e303ae
A		 368 uint64_t validSegs; /* Valid SR/STB slots */
369 addr64_t ppUserPmap; /* Current user state pmap (physical address) */
370 unsigned int ppUserPmapVirt; /* Current user state pmap (virtual address) */
371 unsigned int ppMapFlags; /* Mapping flags */
1c79356b
A		 372
373 /* PPC cache line boundary here - 1A0 */
55e303ae
A		 374 unsigned short ppInvSeg; /* Forces complete invalidate of SRs/SLB (this must stay with ppInvSeg) */
375 unsigned short ppCurSeg; /* Set to 1 if user segments, 0 if kernel (this must stay with ppInvSeg) */
376 unsigned int ppSegSteal; /* Count of segment slot steals */
377 ppnum_t VMMareaPhys; /* vmm state page physical addr */
378 unsigned int VMMXAFlgs; /* vmm extended flags */
379 unsigned int FAMintercept; /* vmm FAM Exceptions to intercept */
3a60a9f5 380 unsigned int hibernate; /* wake from hibernate */
91447636
A		 381 uint32_t save_tbl;
382 uint32_t save_tbu;
1c79356b
A		 383
384 /* PPC cache line boundary here - 1C0 */
91447636 385 unsigned int ppUMWmp[16]; /* Linkage mapping for user memory window - 64 bytes */
55e303ae
A		 386
387 /* PPC cache line boundary here - 200 */
388 uint64_t tempr0; /* temporary savearea */
389 uint64_t tempr1;
390 uint64_t tempr2;
391 uint64_t tempr3;
392
393 uint64_t tempr4;
394 uint64_t tempr5;
395 uint64_t tempr6;
396 uint64_t tempr7;
397
398 uint64_t tempr8;
399 uint64_t tempr9;
400 uint64_t tempr10;
401 uint64_t tempr11;
402
403 uint64_t tempr12;
404 uint64_t tempr13;
405 uint64_t tempr14;
406 uint64_t tempr15;
407
408 uint64_t tempr16;
409 uint64_t tempr17;
410 uint64_t tempr18;
411 uint64_t tempr19;
412
413 uint64_t tempr20;
414 uint64_t tempr21;
415 uint64_t tempr22;
416 uint64_t tempr23;
d7e50217 417
55e303ae
A		 418 uint64_t tempr24;
419 uint64_t tempr25;
420 uint64_t tempr26;
421 uint64_t tempr27;
422
423 uint64_t tempr28;
424 uint64_t tempr29;
425 uint64_t tempr30;
426 uint64_t tempr31;
427
428
429 /* PPC cache line boundary here - 300 */
1c79356b
A		 430 double emfp0; /* Copies of floating point registers */
431 double emfp1; /* Used for emulation purposes */
432 double emfp2;
433 double emfp3;
434
435 double emfp4;
436 double emfp5;
437 double emfp6;
438 double emfp7;
439
440 double emfp8;
441 double emfp9;
442 double emfp10;
443 double emfp11;
444
445 double emfp12;
446 double emfp13;
447 double emfp14;
448 double emfp15;
449
450 double emfp16;
451 double emfp17;
452 double emfp18;
453 double emfp19;
454
455 double emfp20;
456 double emfp21;
457 double emfp22;
458 double emfp23;
459
460 double emfp24;
461 double emfp25;
462 double emfp26;
463 double emfp27;
464
465 double emfp28;
466 double emfp29;
467 double emfp30;
468 double emfp31;
469
55e303ae 470/* - 400 */
1c79356b
A		 471 unsigned int emfpscr_pad;
472 unsigned int emfpscr;
473 unsigned int empadfp[6];
474
55e303ae 475/* - 420 */
1c79356b
A		 476 unsigned int emvr0[4]; /* Copies of vector registers used both */
477 unsigned int emvr1[4]; /* for full vector emulation or */
478 unsigned int emvr2[4]; /* as saveareas while assisting denorms */
479 unsigned int emvr3[4];
480 unsigned int emvr4[4];
481 unsigned int emvr5[4];
482 unsigned int emvr6[4];
483 unsigned int emvr7[4];
484 unsigned int emvr8[4];
485 unsigned int emvr9[4];
486 unsigned int emvr10[4];
487 unsigned int emvr11[4];
488 unsigned int emvr12[4];
489 unsigned int emvr13[4];
490 unsigned int emvr14[4];
491 unsigned int emvr15[4];
492 unsigned int emvr16[4];
493 unsigned int emvr17[4];
494 unsigned int emvr18[4];
495 unsigned int emvr19[4];
496 unsigned int emvr20[4];
497 unsigned int emvr21[4];
498 unsigned int emvr22[4];
499 unsigned int emvr23[4];
500 unsigned int emvr24[4];
501 unsigned int emvr25[4];
502 unsigned int emvr26[4];
503 unsigned int emvr27[4];
504 unsigned int emvr28[4];
505 unsigned int emvr29[4];
506 unsigned int emvr30[4];
507 unsigned int emvr31[4];
508 unsigned int emvscr[4];
509 unsigned int empadvr[4];
55e303ae
A		 510/* - 640 */
511/* note implicit dependence on kSkipListMaxLists, which must be <= 28 */
512 addr64_t skipListPrev[28]; /* prev ptrs saved as side effect of calling mapSearchFull() */
513
514/* - 720 */
1c79356b
A		 515
516 unsigned int patcharea[56];
55e303ae
A		 517/* - 800 */
518
519 hwCtrs hwCtr; /* Hardware exception counters */
520/* - A00 */
3a60a9f5 521 addr64_t pp2ndPage; /* Physical address of the second page of the per_proc */
2d21ac55
A		 522 addr64_t ijsave; /* Pointer to original savearea for injected code */
523 uint32_t pprsvd0A10[4];
3a60a9f5
A		 524/* - A20 */
525 pmsd pms; /* Power Management Stepper control */
2d21ac55
A		 526 unsigned int pprsvd0A40[16]; /* Reserved */
527/* - A80 */
528 uint32_t pprsvd0A80[16]; /* Reserved */
529
530 unsigned int pprsvd0AC0[336]; /* Reserved out to next page boundary */
55e303ae
A		 531/* - 1000 */
532
3a60a9f5
A		 533/*
534 * This is the start of the second page of the per_proc block. Because we do not
535 * allocate physically contiguous memory, it may be physically discontiguous from the
536 * first page. Currently there isn't anything here that is accessed translation off,
537 * but if we need it, pp2ndPage contains the physical address.
538 *
539 * Note that the boot processor's per_proc is statically allocated, so it will be a
540 * V=R contiguous area. That allows access during early boot before we turn translation on
541 * for the first time.
542 */
543
544 unsigned int processor[384]; /* processor structure */
545
546 unsigned int pprsvd1[640]; /* Reserved out to next page boundary */
547/* - 2000 */
1c79356b
A		 548
549};
550
55e303ae
A		 551#pragma pack()
552
1c79356b 553
91447636 554/*
3a60a9f5 555 * Macro to convert a processor_t processor to its attached per_proc_info_t per_proc
91447636
A		 556 */
557#define PROCESSOR_TO_PER_PROC(x) \
558 ((struct per_proc_info*)((unsigned int)(x) \
559 - (unsigned int)(((struct per_proc_info *)0)->processor)))
560
561extern struct per_proc_info BootProcInfo;
562
563#define MAX_CPUS 256
564
565struct per_proc_entry {
3a60a9f5 566 addr64_t ppe_paddr; /* Physical address of the first page of per_proc, 2nd is in pp2ndPage. */
91447636 567 unsigned int ppe_pad4[1];
3a60a9f5 568 struct per_proc_info *ppe_vaddr; /* Virtual address of the per_proc */
91447636
A		 569};
570
571extern struct per_proc_entry PerProcTable[MAX_CPUS-1];
1c79356b 572
55e303ae 573
2d21ac55 574extern const char *trap_type[];
1c79356b 575
3a60a9f5 576#endif /* ndef ASSEMBLER */ /* with this savearea should be redriven */
1c79356b
A		 577
578/* cpu_flags defs */
579#define SIGPactive 0x8000
580#define needSRload 0x4000
581#define turnEEon 0x2000
55e303ae
A		 582#define SleepState 0x0800
583#define SleepStateb 4
584#define mcountOff 0x0400
0b4e3aa0 585#define SignalReady 0x0200
55e303ae 586#define BootDone 0x0100
1c79356b
A		 587#define loadMSR 0x7FF4
588
91447636
A		 589/* ppXFlags defs */
590#define SignalReadyWait 0x00000001
591
1c79356b 592#define T_VECTOR_SIZE 4 /* function pointer size */
1c79356b
A		 593
594/* Hardware exceptions */
595
596#define T_IN_VAIN (0x00 * T_VECTOR_SIZE)
597#define T_RESET (0x01 * T_VECTOR_SIZE)
598#define T_MACHINE_CHECK (0x02 * T_VECTOR_SIZE)
599#define T_DATA_ACCESS (0x03 * T_VECTOR_SIZE)
600#define T_INSTRUCTION_ACCESS (0x04 * T_VECTOR_SIZE)
601#define T_INTERRUPT (0x05 * T_VECTOR_SIZE)
602#define T_ALIGNMENT (0x06 * T_VECTOR_SIZE)
603#define T_PROGRAM (0x07 * T_VECTOR_SIZE)
604#define T_FP_UNAVAILABLE (0x08 * T_VECTOR_SIZE)
605#define T_DECREMENTER (0x09 * T_VECTOR_SIZE)
606#define T_IO_ERROR (0x0a * T_VECTOR_SIZE)
607#define T_RESERVED (0x0b * T_VECTOR_SIZE)
608#define T_SYSTEM_CALL (0x0c * T_VECTOR_SIZE)
609#define T_TRACE (0x0d * T_VECTOR_SIZE)
610#define T_FP_ASSIST (0x0e * T_VECTOR_SIZE)
611#define T_PERF_MON (0x0f * T_VECTOR_SIZE)
612#define T_VMX (0x10 * T_VECTOR_SIZE)
613#define T_INVALID_EXCP0 (0x11 * T_VECTOR_SIZE)
614#define T_INVALID_EXCP1 (0x12 * T_VECTOR_SIZE)
615#define T_INVALID_EXCP2 (0x13 * T_VECTOR_SIZE)
616#define T_INSTRUCTION_BKPT (0x14 * T_VECTOR_SIZE)
617#define T_SYSTEM_MANAGEMENT (0x15 * T_VECTOR_SIZE)
618#define T_ALTIVEC_ASSIST (0x16 * T_VECTOR_SIZE)
619#define T_THERMAL (0x17 * T_VECTOR_SIZE)
620#define T_INVALID_EXCP5 (0x18 * T_VECTOR_SIZE)
621#define T_INVALID_EXCP6 (0x19 * T_VECTOR_SIZE)
622#define T_INVALID_EXCP7 (0x1A * T_VECTOR_SIZE)
623#define T_INVALID_EXCP8 (0x1B * T_VECTOR_SIZE)
624#define T_INVALID_EXCP9 (0x1C * T_VECTOR_SIZE)
625#define T_INVALID_EXCP10 (0x1D * T_VECTOR_SIZE)
626#define T_INVALID_EXCP11 (0x1E * T_VECTOR_SIZE)
627#define T_INVALID_EXCP12 (0x1F * T_VECTOR_SIZE)
55e303ae 628#define T_EMULATE (0x20 * T_VECTOR_SIZE)
1c79356b
A		 629
630#define T_RUNMODE_TRACE (0x21 * T_VECTOR_SIZE) /* 601 only */
631
632#define T_SIGP (0x22 * T_VECTOR_SIZE)
633#define T_PREEMPT (0x23 * T_VECTOR_SIZE)
634#define T_CSWITCH (0x24 * T_VECTOR_SIZE)
635#define T_SHUTDOWN (0x25 * T_VECTOR_SIZE)
0b4e3aa0 636#define T_CHOKE (0x26 * T_VECTOR_SIZE)
1c79356b 637
55e303ae
A		 638#define T_DATA_SEGMENT (0x27 * T_VECTOR_SIZE)
639#define T_INSTRUCTION_SEGMENT (0x28 * T_VECTOR_SIZE)
640
641#define T_SOFT_PATCH (0x29 * T_VECTOR_SIZE)
642#define T_MAINTENANCE (0x2A * T_VECTOR_SIZE)
643#define T_INSTRUMENTATION (0x2B * T_VECTOR_SIZE)
644#define T_ARCHDEP0 (0x2C * T_VECTOR_SIZE)
a3d08fcd 645#define T_HDEC (0x2D * T_VECTOR_SIZE)
2d21ac55
A		 646#define T_INJECT_EXIT (0x2E * T_VECTOR_SIZE)
647#define T_DTRACE_RET T_INJECT_EXIT
55e303ae 648
1c79356b 649#define T_AST (0x100 * T_VECTOR_SIZE)
0b4e3aa0 650#define T_MAX T_CHOKE /* Maximum exception no */
1c79356b 651
d7e50217
A		 652#define T_FAM 0x00004000
653
55e303ae 654#define EXCEPTION_VECTOR(exception) (exception * 0x100 / T_VECTOR_SIZE )
1c79356b 655
0b4e3aa0
A		 656/*
657 * System choke (failure) codes
658 */
659
660#define failDebug 0
661#define failStack 1
662#define failMapping 2
663#define failContext 3
9bccf70c
A		 664#define failNoSavearea 4
665#define failSaveareaCorr 5
666#define failBadLiveContext 6
55e303ae
A		 667#define failSkipLists 7
668#define failUnalignedStk 8
91447636 669#define failPmap 9
b36670ce 670#define failTimeout 10
0b4e3aa0
A		 671
672/* Always must be last - update failNames table in model_dep.c as well */
b36670ce 673#define failUnknown 11
0b4e3aa0 674
1c79356b
A		 675#ifndef ASSEMBLER
676
55e303ae 677#pragma pack(4) /* Make sure the structure stays as we defined it */
1c79356b
A		 678typedef struct resethandler {
679 unsigned int type;
680 vm_offset_t call_paddr;
681 vm_offset_t arg__paddr;
682} resethandler_t;
55e303ae 683#pragma pack()
1c79356b
A		 684
685extern resethandler_t ResetHandler;
686
687#endif
688
689#define RESET_HANDLER_NULL 0x0
690#define RESET_HANDLER_START 0x1
55e303ae
A		 691#define RESET_HANDLER_BUPOR 0x2
692#define RESET_HANDLER_IGNORE 0x3
1c79356b
A		 693
694#endif /* _PPC_EXCEPTION_H_ */
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