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A		 1/*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22/*
23 * @OSF_COPYRIGHT@
24 */
25
26/* Miscellaneous constants and structures used by the exception
27 * handlers
28 */
29
30#ifndef _PPC_EXCEPTION_H_
31#define _PPC_EXCEPTION_H_
32
33#ifndef ASSEMBLER
34
35#include <cpus.h>
36#include <mach_kdb.h>
37#include <mach_kdp.h>
38
39#include <mach/machine/vm_types.h>
40#include <mach/boolean.h>
41#include <pexpert/pexpert.h>
42#include <IOKit/IOInterrupts.h>
43#include <ppc/machine_routines.h>
44
45/* Per processor CPU features */
46struct procFeatures {
47 unsigned int Available;
48#define pfFloat 0x80000000
49#define pfFloatb 0
50#define pfAltivec 0x40000000
51#define pfAltivecb 1
52#define pfAvJava 0x20000000
53#define pfAvJavab 2
54#define pfSMPcap 0x10000000
55#define pfSMPcapb 3
56#define pfCanSleep 0x08000000
57#define pfCanSleepb 4
58#define pfCanNap 0x04000000
59#define pfCanNapb 5
60#define pfCanDoze 0x02000000
61#define pfCanDozeb 6
62#define pfThermal 0x01000000
63#define pfThermalb 7
64#define pfThermInt 0x00800000
65#define pfThermIntb 8
66#define pfL23lck 0x00001000
67#define pfL23lckb 19
68#define pfWillNap 0x00000800
69#define pfWillNapb 20
70#define pfNoMSRir 0x00000400
71#define pfNoMSRirb 21
72#define pfL1nnc 0x00000200
73#define pfL1nncb 22
74#define pfL1i 0x00000100
75#define pfL1ib 23
76#define pfL1d 0x00000080
77#define pfL1db 24
78#define pfL1fa 0x00000040
79#define pfL1fab 25
80#define pfL2 0x00000020
81#define pfL2b 26
82#define pfL2fa 0x00000010
83#define pfL2fab 27
84#define pfL2i 0x00000008
85#define pfL2ib 28
86#define pfL3 0x00000004
87#define pfL3b 29
88#define pfL3fa 0x00000002
89#define pfL3fab 30
90#define pfValid 0x00000001
91#define pfValidb 31
92 unsigned short rptdProc;
93 unsigned short lineSize;
94 unsigned int l1iSize;
95 unsigned int l1dSize;
96 unsigned int l2cr;
97 unsigned int l2Size;
98 unsigned int l3cr;
99 unsigned int l3Size;
100 unsigned int pfHID0;
101 unsigned int pfHID1;
102 unsigned int pfHID2;
103 unsigned int pfHID3;
104 unsigned int pfMSSCR0;
105 unsigned int pfMSSCR1;
106 unsigned int pfICTRL;
107 unsigned int pfLDSTCR;
108};
109
110typedef struct procFeatures procFeatures;
111
112struct thrmControl {
113 unsigned int maxTemp; /* Maximum temprature before damage */
114 unsigned int throttleTemp; /* Temprature at which to throttle down */
115 unsigned int lowTemp; /* Interrupt when temprature drops below */
116 unsigned int highTemp; /* Interrupt when temprature exceeds this */
117 unsigned int thrm3val; /* Value for thrm3 register */
118 unsigned int rsvd[3]; /* Pad to cache line */
119};
120
121typedef struct thrmControl thrmControl;
122
123/* When an exception is taken, this info is accessed via sprg0 */
124/* We should always have this one on a cache line boundary */
125struct per_proc_info {
126 unsigned short cpu_number;
127 unsigned short cpu_flags; /* Various low-level flags */
128 vm_offset_t istackptr;
129 vm_offset_t intstack_top_ss;
130
131#if MACH_KDP || MACH_KDB
132 vm_offset_t debstackptr;
133 vm_offset_t debstack_top_ss;
134#else
135 unsigned int ppigas1[2]; /* Take up some space if no KDP or KDB */
136#endif
137
138 unsigned int tempwork1; /* Temp work area - monitor use carefully */
139 unsigned int save_exception_type;
140 unsigned int old_thread;
141
142 /* PPC cache line boundary here - 020 */
143
144 unsigned int active_kloaded; /* pointer to active_kloaded[CPU_NO] */
145 unsigned int cpu_data; /* pointer to cpu_data[CPU_NO] */
146 unsigned int need_ast; /* pointer to need_ast[CPU_NO] */
147/*
148 * Note: the following two pairs of words need to stay in order and each pair must
149 * be in the same reservation (line) granule
150 */
151 unsigned int FPU_thread; /* Thread owning the FPU on this cpu.*/
152 unsigned int FPU_vmmCtx; /* Owing virtual machine context */
153 unsigned int VMX_thread; /* Thread owning the VMX on this cpu */
154 unsigned int VMX_vmmCtx; /* Owing virtual machine context */
155 unsigned int active_stacks; /* pointer to active_stacks[CPU_NO] */
156
157 /* PPC cache line boundary here - 040 */
158 unsigned int quickfret; /* Pointer to savearea for exception exit to free */
159 unsigned int Lastpmap; /* Last user pmap loaded */
160 unsigned int userspace; /* Last loaded user memory space ID */
161 unsigned int userpmap; /* User pmap - real address */
162 unsigned int liveVRSave; /* VRSave assiciated with live vector registers */
163 unsigned int spcFlags; /* Special thread flags */
164 unsigned int liveFPSCR; /* FPSCR which is for the live context */
165 unsigned int ppigas05C; /* Reserved area */
166
167 /* PPC cache line boundary here - 060 */
168 boolean_t (*set_interrupts_enabled)(boolean_t);
169 boolean_t (*get_interrupts_enabled)(void);
170 IOInterruptHandler interrupt_handler;
171 void * interrupt_nub;
172 unsigned int interrupt_source;
173 void * interrupt_target;
174 void * interrupt_refCon;
175 unsigned int savedSave; /* Savearea saved across sleep - must be 0 at boot */
176
177 /* PPC cache line boundary here - 080 */
178 unsigned int MPsigpStat; /* Signal Processor status (interlocked update for this one) */
179#define MPsigpMsgp 0xC0000000 /* Message pending (busy + pass) */
180#define MPsigpBusy 0x80000000 /* Processor area busy, i.e., locked */
181#define MPsigpPass 0x40000000 /* Busy lock passed to receiving processor */
182#define MPsigpSrc 0x000000FF /* Processor that owns busy, i.e., the ID of */
183 /* whomever set busy. When a busy is passed, */
184 /* this is the requestor of the function. */
185#define MPsigpFunc 0x0000FF00 /* Current function */
186#define MPsigpIdle 0x00 /* No function pending */
187#define MPsigpSigp 0x04 /* Signal a processor */
188#define SIGPast 0 /* Requests an ast on target processor */
189#define SIGPcpureq 1 /* Requests CPU specific function */
190#define SIGPdebug 2 /* Requests a debugger entry */
191#define SIGPwake 3 /* Wake up a sleeping processor */
192#define CPRQtemp 0 /* Get temprature of processor */
193#define CPRQtimebase 1 /* Get timebase of processor */
194 unsigned int MPsigpParm0; /* SIGP parm 0 */
195 unsigned int MPsigpParm1; /* SIGP parm 1 */
196 unsigned int MPsigpParm2; /* SIGP parm 2 */
197 cpu_id_t cpu_id;
198 vm_offset_t start_paddr;
199 unsigned int ruptStamp[2]; /* Timebase at last interruption */
200
201 /* PPC cache line boundary here - 0A0 */
202 procFeatures pf; /* Processor features */
203
204 /* PPC cache line boundary here - 0E0 */
205 thrmControl thrm; /* Thermal controls */
206
207 /* PPC cache line boundary here - 100 */
208 unsigned int napStamp[2]; /* Time base when we napped */
209 unsigned int napTotal[2]; /* Total nap time in ticks */
210 unsigned int numSIGPast; /* Number of SIGP asts recieved */
211 unsigned int numSIGPcpureq; /* Number of SIGP cpu requests recieved */
212 unsigned int numSIGPdebug; /* Number of SIGP debugs recieved */
213 unsigned int numSIGPwake; /* Number of SIGP wakes recieved */
214
215 /* PPC cache line boundary here - 120 */
216 unsigned int spcTRc; /* Special trace count */
217 unsigned int spcTRp; /* Special trace buffer pointer */
218 unsigned int Uassist; /* User Assist Word */
219 unsigned int rsrvd12C[5]; /* Reserved slots */
220
221 /* PPC cache line boundary here - 140 */
222 time_base_enable_t time_base_enable;
223 unsigned int rsrvd140[7]; /* Reserved slots */
224
225 /* PPC cache line boundary here - 160 */
226 unsigned int rsrvd160[8]; /* Reserved slots */
227
228 /* PPC cache line boundary here - 180 */
229 unsigned int rsrvd180[8]; /* Reserved slots */
230
231 /* PPC cache line boundary here - 1A0 */
232 unsigned int rsrvd1A0[8]; /* Reserved slots */
233
234 /* PPC cache line boundary here - 1C0 */
235 unsigned int rsrvd1C0[8]; /* Reserved slots */
236
237 /* PPC cache line boundary here - 1E0 */
238 double emfp0; /* Copies of floating point registers */
239 double emfp1; /* Used for emulation purposes */
240 double emfp2;
241 double emfp3;
242
243 double emfp4;
244 double emfp5;
245 double emfp6;
246 double emfp7;
247
248 double emfp8;
249 double emfp9;
250 double emfp10;
251 double emfp11;
252
253 double emfp12;
254 double emfp13;
255 double emfp14;
256 double emfp15;
257
258 double emfp16;
259 double emfp17;
260 double emfp18;
261 double emfp19;
262
263 double emfp20;
264 double emfp21;
265 double emfp22;
266 double emfp23;
267
268 double emfp24;
269 double emfp25;
270 double emfp26;
271 double emfp27;
272
273 double emfp28;
274 double emfp29;
275 double emfp30;
276 double emfp31;
277
278/* - 2E0 */
279 unsigned int emfpscr_pad;
280 unsigned int emfpscr;
281 unsigned int empadfp[6];
282
283/* - 300 */
284 unsigned int emvr0[4]; /* Copies of vector registers used both */
285 unsigned int emvr1[4]; /* for full vector emulation or */
286 unsigned int emvr2[4]; /* as saveareas while assisting denorms */
287 unsigned int emvr3[4];
288 unsigned int emvr4[4];
289 unsigned int emvr5[4];
290 unsigned int emvr6[4];
291 unsigned int emvr7[4];
292 unsigned int emvr8[4];
293 unsigned int emvr9[4];
294 unsigned int emvr10[4];
295 unsigned int emvr11[4];
296 unsigned int emvr12[4];
297 unsigned int emvr13[4];
298 unsigned int emvr14[4];
299 unsigned int emvr15[4];
300 unsigned int emvr16[4];
301 unsigned int emvr17[4];
302 unsigned int emvr18[4];
303 unsigned int emvr19[4];
304 unsigned int emvr20[4];
305 unsigned int emvr21[4];
306 unsigned int emvr22[4];
307 unsigned int emvr23[4];
308 unsigned int emvr24[4];
309 unsigned int emvr25[4];
310 unsigned int emvr26[4];
311 unsigned int emvr27[4];
312 unsigned int emvr28[4];
313 unsigned int emvr29[4];
314 unsigned int emvr30[4];
315 unsigned int emvr31[4];
316 unsigned int emvscr[4];
317 unsigned int empadvr[4];
318/* - 520 */
319
320 unsigned int patcharea[56];
321/* - 600 */
322
323};
324
325
326extern struct per_proc_info per_proc_info[NCPUS];
327
328typedef struct savearea {
329
330/* The following area corresponds to ppc_saved_state and ppc_thread_state */
331
332/* offset 0x0000 */
333 unsigned int save_srr0;
334 unsigned int save_srr1;
335 unsigned int save_r0;
336 unsigned int save_r1;
337 unsigned int save_r2;
338 unsigned int save_r3;
339 unsigned int save_r4;
340 unsigned int save_r5;
341
342 unsigned int save_r6;
343 unsigned int save_r7;
344 unsigned int save_r8;
345 unsigned int save_r9;
346 unsigned int save_r10;
347 unsigned int save_r11;
348 unsigned int save_r12;
349 unsigned int save_r13;
350
351 unsigned int save_r14;
352 unsigned int save_r15;
353 unsigned int save_r16;
354 unsigned int save_r17;
355 unsigned int save_r18;
356 unsigned int save_r19;
357 unsigned int save_r20;
358 unsigned int save_r21;
359
360 unsigned int save_r22;
361 unsigned int save_r23;
362 unsigned int save_r24;
363 unsigned int save_r25;
364 unsigned int save_r26;
365 unsigned int save_r27;
366 unsigned int save_r28;
367 unsigned int save_r29;
368
369 unsigned int save_r30;
370 unsigned int save_r31;
371 unsigned int save_cr;
372 unsigned int save_xer;
373 unsigned int save_lr;
374 unsigned int save_ctr;
375 unsigned int save_mq;
376 unsigned int save_vrsave;
377
378 unsigned int save_sr_copyin;
379 unsigned int save_space;
380 unsigned int save_xfpscrpad;
381 unsigned int save_xfpscr;
382 unsigned int save_pad2[4];
383
384
385/* The following corresponds to ppc_exception_state */
386
387/* offset 0x00C0 */
388 unsigned int save_dar;
389 unsigned int save_dsisr;
390 unsigned int save_exception;
391 unsigned int save_pad3[5];
392
393/* The following corresponds to ppc_float_state */
394
395/* offset 0x00E0 */
396 double save_fp0;
397 double save_fp1;
398 double save_fp2;
399 double save_fp3;
400
401 double save_fp4;
402 double save_fp5;
403 double save_fp6;
404 double save_fp7;
405
406 double save_fp8;
407 double save_fp9;
408 double save_fp10;
409 double save_fp11;
410
411 double save_fp12;
412 double save_fp13;
413 double save_fp14;
414 double save_fp15;
415
416 double save_fp16;
417 double save_fp17;
418 double save_fp18;
419 double save_fp19;
420
421 double save_fp20;
422 double save_fp21;
423 double save_fp22;
424 double save_fp23;
425
426 double save_fp24;
427 double save_fp25;
428 double save_fp26;
429 double save_fp27;
430
431 double save_fp28;
432 double save_fp29;
433 double save_fp30;
434 double save_fp31;
435
436 unsigned int save_fpscr_pad;
437 unsigned int save_fpscr;
438 unsigned int save_pad4[6];
439
440/* The following is the save area for the VMX registers */
441
442/* offset 0x0200 */
443 unsigned int save_vr0[4];
444 unsigned int save_vr1[4];
445 unsigned int save_vr2[4];
446 unsigned int save_vr3[4];
447 unsigned int save_vr4[4];
448 unsigned int save_vr5[4];
449 unsigned int save_vr6[4];
450 unsigned int save_vr7[4];
451 unsigned int save_vr8[4];
452 unsigned int save_vr9[4];
453 unsigned int save_vr10[4];
454 unsigned int save_vr11[4];
455 unsigned int save_vr12[4];
456 unsigned int save_vr13[4];
457 unsigned int save_vr14[4];
458 unsigned int save_vr15[4];
459 unsigned int save_vr16[4];
460 unsigned int save_vr17[4];
461 unsigned int save_vr18[4];
462 unsigned int save_vr19[4];
463 unsigned int save_vr20[4];
464 unsigned int save_vr21[4];
465 unsigned int save_vr22[4];
466 unsigned int save_vr23[4];
467 unsigned int save_vr24[4];
468 unsigned int save_vr25[4];
469 unsigned int save_vr26[4];
470 unsigned int save_vr27[4];
471 unsigned int save_vr28[4];
472 unsigned int save_vr29[4];
473 unsigned int save_vr30[4];
474 unsigned int save_vr31[4];
475 unsigned int save_vscr[4]; /* Note that this is always valid if VMX has been used */
476 unsigned int save_pad5[4]; /* Insures that vrvalid is on a cache line */
477 unsigned int save_vrvalid; /* VRs that have been saved */
478 unsigned int save_pad6[7];
479
480/* The following is the save area for the segment registers */
481
482/* offset 0x0440 */
483
484 unsigned int save_sr0;
485 unsigned int save_sr1;
486 unsigned int save_sr2;
487 unsigned int save_sr3;
488 unsigned int save_sr4;
489 unsigned int save_sr5;
490 unsigned int save_sr6;
491 unsigned int save_sr7;
492
493 unsigned int save_sr8;
494 unsigned int save_sr9;
495 unsigned int save_sr10;
496 unsigned int save_sr11;
497 unsigned int save_sr12;
498 unsigned int save_sr13;
499 unsigned int save_sr14;
500 unsigned int save_sr15;
501
502/* The following are the control area for this save area */
503
504/* offset 0x0480 */
505
506 struct savearea *save_prev; /* The address of the previous normal savearea */
507 struct savearea *save_prev_float; /* The address of the previous floating point savearea */
508 struct savearea *save_prev_vector; /* The address of the previous vector savearea */
509 struct savearea *save_qfret; /* The "quick release" chain */
510 struct savearea *save_phys; /* The physical address of this savearea */
511 struct thread_activation *save_act; /* Pointer to the associated activation */
512 unsigned int save_flags; /* Various flags */
513#define save_perm 0x80000000 /* Permanent area, cannot be released */
514 unsigned int save_level_fp; /* Level that floating point state belongs to */
515 unsigned int save_level_vec; /* Level that vector state belongs to */
516
517} savearea;
518
519typedef struct savectl { /* Savearea control */
520
521 unsigned int *sac_next; /* Points to next savearea page that has a free slot - real */
522 unsigned int sac_vrswap; /* XOR mask to swap V to R or vice versa */
523 unsigned int sac_alloc; /* Bitmap of allocated slots */
524 unsigned int sac_flags; /* Various flags */
525} savectl;
526
527struct Saveanchor {
528 unsigned int savelock; /* Lock word for savearea manipulation */
529 int savecount; /* The total number of save areas allocated */
530 int saveinuse; /* Number of areas in use */
531 int savemin; /* We abend if lower than this */
532 int saveneghyst; /* The negative hysteresis value */
533 int savetarget; /* The target point for free save areas */
534 int saveposhyst; /* The positive hysteresis value */
535 unsigned int savefree; /* Anchor for the freelist queue */
536 /* Cache line (32-byte) boundary */
537 int savextnd; /* Free list extention count */
538 int saveneed; /* Number of savearea's needed. So far, we assume we need 3 per activation */
539 int savemaxcount;
540 int savespare[5]; /* Spare */
541};
542
543
544extern char *trap_type[];
545
546#endif /* ndef ASSEMBLER */
547
548#define sac_empty 0xC0000000 /* Mask with all entries empty */
549#define sac_cnt 2 /* Number of entries per page */
550#define sac_busy 0x80000000 /* This page is busy - used during initial allocation */
551#define sac_perm 0x40000000 /* Page permanently assigned */
552
553#define SAVattach 0x80000000 /* Savearea is attached to a thread */
554#define SAVfpuvalid 0x40000000 /* Savearea contains FPU context */
555#define SAVvmxvalid 0x20000000 /* Savearea contains VMX context */
556#define SAVinuse 0xE0000000 /* Save area is inuse */
557#define SAVrststk 0x00010000 /* Indicates that the current stack should be reset to empty */
558#define SAVsyscall 0x00020000 /* Indicates that the savearea is associated with a syscall */
559#define SAVredrive 0x00040000 /* Indicates that the low-level fault handler associated */
560 /* with this savearea should be redriven */
561
562/* cpu_flags defs */
563#define SIGPactive 0x8000
564#define needSRload 0x4000
565#define turnEEon 0x2000
566#define traceBE 0x1000 /* user mode BE tracing in enabled */
567#define traceBEb 3 /* bit number for traceBE */
568#define BootDone 0x0100
569#define loadMSR 0x7FF4
570
571#define T_VECTOR_SIZE 4 /* function pointer size */
572#define InitialSaveMin 4 /* The initial value for the minimum number of saveareas */
573#define InitialNegHysteresis 5 /* The number off from target before we adjust upwards */
574#define InitialPosHysteresis 10 /* The number off from target before we adjust downwards */
575#define InitialSaveTarget 20 /* The number of saveareas for an initial target */
576#define InitialSaveAreas 20 /* The number of saveareas to allocate at boot */
577#define InitialSaveBloks (InitialSaveAreas+sac_cnt-1)/sac_cnt /* The number of savearea blocks to allocate at boot */
578
579/* Hardware exceptions */
580
581#define T_IN_VAIN (0x00 * T_VECTOR_SIZE)
582#define T_RESET (0x01 * T_VECTOR_SIZE)
583#define T_MACHINE_CHECK (0x02 * T_VECTOR_SIZE)
584#define T_DATA_ACCESS (0x03 * T_VECTOR_SIZE)
585#define T_INSTRUCTION_ACCESS (0x04 * T_VECTOR_SIZE)
586#define T_INTERRUPT (0x05 * T_VECTOR_SIZE)
587#define T_ALIGNMENT (0x06 * T_VECTOR_SIZE)
588#define T_PROGRAM (0x07 * T_VECTOR_SIZE)
589#define T_FP_UNAVAILABLE (0x08 * T_VECTOR_SIZE)
590#define T_DECREMENTER (0x09 * T_VECTOR_SIZE)
591#define T_IO_ERROR (0x0a * T_VECTOR_SIZE)
592#define T_RESERVED (0x0b * T_VECTOR_SIZE)
593#define T_SYSTEM_CALL (0x0c * T_VECTOR_SIZE)
594#define T_TRACE (0x0d * T_VECTOR_SIZE)
595#define T_FP_ASSIST (0x0e * T_VECTOR_SIZE)
596#define T_PERF_MON (0x0f * T_VECTOR_SIZE)
597#define T_VMX (0x10 * T_VECTOR_SIZE)
598#define T_INVALID_EXCP0 (0x11 * T_VECTOR_SIZE)
599#define T_INVALID_EXCP1 (0x12 * T_VECTOR_SIZE)
600#define T_INVALID_EXCP2 (0x13 * T_VECTOR_SIZE)
601#define T_INSTRUCTION_BKPT (0x14 * T_VECTOR_SIZE)
602#define T_SYSTEM_MANAGEMENT (0x15 * T_VECTOR_SIZE)
603#define T_ALTIVEC_ASSIST (0x16 * T_VECTOR_SIZE)
604#define T_THERMAL (0x17 * T_VECTOR_SIZE)
605#define T_INVALID_EXCP5 (0x18 * T_VECTOR_SIZE)
606#define T_INVALID_EXCP6 (0x19 * T_VECTOR_SIZE)
607#define T_INVALID_EXCP7 (0x1A * T_VECTOR_SIZE)
608#define T_INVALID_EXCP8 (0x1B * T_VECTOR_SIZE)
609#define T_INVALID_EXCP9 (0x1C * T_VECTOR_SIZE)
610#define T_INVALID_EXCP10 (0x1D * T_VECTOR_SIZE)
611#define T_INVALID_EXCP11 (0x1E * T_VECTOR_SIZE)
612#define T_INVALID_EXCP12 (0x1F * T_VECTOR_SIZE)
613#define T_INVALID_EXCP13 (0x20 * T_VECTOR_SIZE)
614
615#define T_RUNMODE_TRACE (0x21 * T_VECTOR_SIZE) /* 601 only */
616
617#define T_SIGP (0x22 * T_VECTOR_SIZE)
618#define T_PREEMPT (0x23 * T_VECTOR_SIZE)
619#define T_CSWITCH (0x24 * T_VECTOR_SIZE)
620#define T_SHUTDOWN (0x25 * T_VECTOR_SIZE)
621
622#define T_AST (0x100 * T_VECTOR_SIZE)
623#define T_MAX T_SHUTDOWN /* Maximum exception no */
624
625#define EXCEPTION_VECTOR(exception) (exception * 0x100 /T_VECTOR_SIZE )
626
627#ifndef ASSEMBLER
628
629typedef struct resethandler {
630 unsigned int type;
631 vm_offset_t call_paddr;
632 vm_offset_t arg__paddr;
633} resethandler_t;
634
635extern resethandler_t ResetHandler;
636
637#endif
638
639#define RESET_HANDLER_NULL 0x0
640#define RESET_HANDLER_START 0x1
641
642#endif /* _PPC_EXCEPTION_H_ */
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