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1c79356b | 1 | /* |
3a60a9f5 | 2 | * Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved. |
1c79356b | 3 | * |
6601e61a | 4 | * @APPLE_LICENSE_HEADER_START@ |
1c79356b | 5 | * |
6601e61a A |
6 | * The contents of this file constitute Original Code as defined in and |
7 | * are subject to the Apple Public Source License Version 1.1 (the | |
8 | * "License"). You may not use this file except in compliance with the | |
9 | * License. Please obtain a copy of the License at | |
10 | * http://www.apple.com/publicsource and read it before using this file. | |
8f6c56a5 | 11 | * |
6601e61a A |
12 | * This Original Code and all software distributed under the License are |
13 | * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER | |
8f6c56a5 A |
14 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, |
15 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, | |
6601e61a A |
16 | * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the |
17 | * License for the specific language governing rights and limitations | |
18 | * under the License. | |
8f6c56a5 | 19 | * |
6601e61a | 20 | * @APPLE_LICENSE_HEADER_END@ |
1c79356b A |
21 | */ |
22 | /* | |
23 | * @OSF_COPYRIGHT@ | |
24 | */ | |
25 | ||
26 | #include <debug.h> | |
55e303ae | 27 | #include <mach_ldebug.h> |
1c79356b A |
28 | #include <mach_kdb.h> |
29 | #include <mach_kdp.h> | |
30 | ||
31 | #include <kern/misc_protos.h> | |
32 | #include <kern/thread.h> | |
33 | #include <kern/processor.h> | |
91447636 | 34 | #include <kern/startup.h> |
1c79356b A |
35 | #include <machine/machine_routines.h> |
36 | #include <ppc/boot.h> | |
37 | #include <ppc/proc_reg.h> | |
38 | #include <ppc/misc_protos.h> | |
39 | #include <ppc/pmap.h> | |
40 | #include <ppc/new_screen.h> | |
41 | #include <ppc/exception.h> | |
91447636 | 42 | #include <ppc/asm.h> |
1c79356b A |
43 | #include <ppc/Firmware.h> |
44 | #include <ppc/savearea.h> | |
45 | #include <ppc/low_trace.h> | |
46 | #include <ppc/Diagnostics.h> | |
91447636 | 47 | #include <ppc/cpu_internal.h> |
d52fe63f | 48 | #include <ppc/mem.h> |
55e303ae | 49 | #include <ppc/mappings.h> |
91447636 | 50 | #include <ppc/locks.h> |
0c530ab8 | 51 | #include <kern/pms.h> |
3a60a9f5 | 52 | #include <ppc/rtclock.h> |
1c79356b A |
53 | |
54 | #include <pexpert/pexpert.h> | |
55 | ||
91447636 A |
56 | extern unsigned int mckFlags; |
57 | extern vm_offset_t intstack; | |
58 | extern vm_offset_t debstack; | |
1c79356b | 59 | |
1c79356b A |
60 | int pc_trace_buf[1024] = {0}; |
61 | int pc_trace_cnt = 1024; | |
62 | ||
55e303ae A |
63 | extern unsigned int extPatchMCK; |
64 | extern unsigned int extPatch32; | |
65 | extern unsigned int hwulckPatch_isync; | |
66 | extern unsigned int hwulckPatch_eieio; | |
67 | extern unsigned int hwulckbPatch_isync; | |
68 | extern unsigned int hwulckbPatch_eieio; | |
69 | extern unsigned int mulckPatch_isync; | |
70 | extern unsigned int mulckPatch_eieio; | |
91447636 A |
71 | extern unsigned int mulckePatch_isync; |
72 | extern unsigned int mulckePatch_eieio; | |
55e303ae A |
73 | extern unsigned int sulckPatch_isync; |
74 | extern unsigned int sulckPatch_eieio; | |
91447636 A |
75 | extern unsigned int rwlesPatch_isync; |
76 | extern unsigned int rwlesPatch_eieio; | |
77 | extern unsigned int rwldPatch_isync; | |
78 | extern unsigned int rwldPatch_eieio; | |
55e303ae A |
79 | extern unsigned int retfsectPatch_eieio; |
80 | extern unsigned int retfsectPatch_isync; | |
91447636 A |
81 | extern unsigned int bcopy_nop_if_32bit; |
82 | extern unsigned int bcopy_nc_nop_if_32bit; | |
83 | extern unsigned int memcpy_nop_if_32bit; | |
84 | extern unsigned int xsum_nop_if_32bit; | |
85 | extern unsigned int uft_nop_if_32bit; | |
86 | extern unsigned int uft_uaw_nop_if_32bit; | |
b36670ce | 87 | extern unsigned int uft_cuttrace; |
55e303ae A |
88 | |
89 | int forcenap = 0; | |
91447636 | 90 | int wcte = 0; /* Non-cache gather timer disabled */ |
55e303ae | 91 | |
91447636 A |
92 | patch_entry_t patch_table[] = { |
93 | {&extPatch32, 0x60000000, PATCH_FEATURE, PatchExt32}, | |
94 | {&extPatchMCK, 0x60000000, PATCH_PROCESSOR, CPU_SUBTYPE_POWERPC_970}, | |
95 | {&hwulckPatch_isync, 0x60000000, PATCH_FEATURE, PatchLwsync}, | |
96 | {&hwulckPatch_eieio, 0x7c2004ac, PATCH_FEATURE, PatchLwsync}, | |
97 | {&hwulckbPatch_isync, 0x60000000, PATCH_FEATURE, PatchLwsync}, | |
98 | {&hwulckbPatch_eieio, 0x7c2004ac, PATCH_FEATURE, PatchLwsync}, | |
99 | {&mulckPatch_isync, 0x60000000, PATCH_FEATURE, PatchLwsync}, | |
100 | {&mulckPatch_eieio, 0x7c2004ac, PATCH_FEATURE, PatchLwsync}, | |
101 | {&mulckePatch_isync, 0x60000000, PATCH_FEATURE, PatchLwsync}, | |
102 | {&mulckePatch_eieio, 0x7c2004ac, PATCH_FEATURE, PatchLwsync}, | |
103 | {&sulckPatch_isync, 0x60000000, PATCH_FEATURE, PatchLwsync}, | |
104 | {&sulckPatch_eieio, 0x7c2004ac, PATCH_FEATURE, PatchLwsync}, | |
105 | {&rwlesPatch_isync, 0x60000000, PATCH_FEATURE, PatchLwsync}, | |
106 | {&rwlesPatch_eieio, 0x7c2004ac, PATCH_FEATURE, PatchLwsync}, | |
107 | {&rwldPatch_isync, 0x60000000, PATCH_FEATURE, PatchLwsync}, | |
108 | {&rwldPatch_eieio, 0x7c2004ac, PATCH_FEATURE, PatchLwsync}, | |
109 | {&bcopy_nop_if_32bit, 0x60000000, PATCH_FEATURE, PatchExt32}, | |
110 | {&bcopy_nc_nop_if_32bit,0x60000000, PATCH_FEATURE, PatchExt32}, | |
111 | {&memcpy_nop_if_32bit, 0x60000000, PATCH_FEATURE, PatchExt32}, | |
55e303ae | 112 | #if !MACH_LDEBUG |
91447636 A |
113 | {&retfsectPatch_isync, 0x60000000, PATCH_FEATURE, PatchLwsync}, |
114 | {&retfsectPatch_eieio, 0x7c2004ac, PATCH_FEATURE, PatchLwsync}, | |
55e303ae | 115 | #endif |
91447636 A |
116 | {&xsum_nop_if_32bit, 0x60000000, PATCH_FEATURE, PatchExt32}, |
117 | {&uft_nop_if_32bit, 0x60000000, PATCH_FEATURE, PatchExt32}, | |
118 | {&uft_uaw_nop_if_32bit, 0x60000000, PATCH_FEATURE, PatchExt32}, | |
b36670ce | 119 | {&uft_cuttrace, 0x60000000, PATCH_FEATURE, PatchExt32}, |
91447636 | 120 | {NULL, 0x00000000, PATCH_END_OF_TABLE, 0} |
55e303ae A |
121 | }; |
122 | ||
3a60a9f5 | 123 | |
91447636 A |
124 | /* |
125 | * Forward definition | |
126 | */ | |
127 | void ppc_init( | |
128 | boot_args *args); | |
129 | ||
130 | void ppc_init_cpu( | |
131 | struct per_proc_info *proc_info); | |
132 | ||
133 | /* | |
134 | * Routine: ppc_init | |
135 | * Function: | |
136 | */ | |
137 | void | |
138 | ppc_init( | |
139 | boot_args *args) | |
1c79356b | 140 | { |
91447636 A |
141 | unsigned int maxmem; |
142 | uint64_t xmaxmem; | |
143 | uint64_t newhid; | |
144 | unsigned int cputrace; | |
145 | unsigned int novmx; | |
146 | unsigned int mcksoft; | |
147 | thread_t thread; | |
148 | mapping_t *mp; | |
149 | uint64_t scdata; | |
150 | ||
a3d08fcd A |
151 | |
152 | ||
1c79356b A |
153 | /* |
154 | * Setup per_proc info for first cpu. | |
155 | */ | |
156 | ||
91447636 A |
157 | BootProcInfo.cpu_number = 0; |
158 | BootProcInfo.cpu_flags = 0; | |
3a60a9f5 | 159 | BootProcInfo.istackptr = 0; /* we're on the interrupt stack */ |
91447636 A |
160 | BootProcInfo.intstack_top_ss = (vm_offset_t)&intstack + INTSTACK_SIZE - FM_SIZE; |
161 | BootProcInfo.debstack_top_ss = (vm_offset_t)&debstack + KERNEL_STACK_SIZE - FM_SIZE; | |
162 | BootProcInfo.debstackptr = BootProcInfo.debstack_top_ss; | |
163 | BootProcInfo.interrupts_enabled = 0; | |
164 | BootProcInfo.pending_ast = AST_NONE; | |
165 | BootProcInfo.FPU_owner = 0; | |
166 | BootProcInfo.VMX_owner = 0; | |
167 | BootProcInfo.pp_cbfr = console_per_proc_alloc(TRUE); | |
3a60a9f5 A |
168 | BootProcInfo.rtcPop = EndOfAllTime; |
169 | BootProcInfo.pp2ndPage = (addr64_t)&BootProcInfo; /* Initial physical address of the second page */ | |
170 | ||
171 | BootProcInfo.pms.pmsStamp = 0; /* Dummy transition time */ | |
172 | BootProcInfo.pms.pmsPop = EndOfAllTime; /* Set the pop way into the future */ | |
173 | ||
174 | BootProcInfo.pms.pmsState = pmsParked; /* Park the power stepper */ | |
175 | BootProcInfo.pms.pmsCSetCmd = pmsCInit; /* Set dummy initial hardware state */ | |
176 | ||
91447636 A |
177 | mp = (mapping_t *)BootProcInfo.ppUMWmp; |
178 | mp->mpFlags = 0x01000000 | mpLinkage | mpPerm | 1; | |
55e303ae | 179 | mp->mpSpace = invalSpace; |
1c79356b | 180 | |
3a60a9f5 A |
181 | pmsInit(); /* Initialize the stepper */ |
182 | ||
55e303ae A |
183 | thread_bootstrap(); |
184 | ||
91447636 A |
185 | thread = current_thread(); |
186 | thread->machine.curctx = &thread->machine.facctx; | |
187 | thread->machine.facctx.facAct = thread; | |
3a60a9f5 | 188 | thread->machine.umwSpace = invalSpace; /* Initialize user memory window space to invalid */ |
91447636 | 189 | thread->machine.preemption_count = 1; |
55e303ae | 190 | |
91447636 | 191 | cpu_bootstrap(); |
1c79356b A |
192 | cpu_init(); |
193 | ||
1c79356b | 194 | master_cpu = 0; |
91447636 A |
195 | processor_bootstrap(); |
196 | ||
197 | timer_switch((uint32_t)mach_absolute_time(), &thread->system_timer); | |
1c79356b | 198 | |
91447636 | 199 | static_memory_end = round_page(args->topOfKernelData);; |
55e303ae | 200 | |
3a60a9f5 | 201 | PE_init_platform(FALSE, args); /* Get platform expert set up */ |
de355530 | 202 | |
55e303ae | 203 | if (!PE_parse_boot_arg("novmx", &novmx)) novmx=0; /* Special run without VMX? */ |
3a60a9f5 A |
204 | if(novmx) { /* Yeah, turn it off */ |
205 | BootProcInfo.pf.Available &= ~pfAltivec; /* Turn off Altivec available */ | |
91447636 | 206 | __asm__ volatile("mtsprg 2,%0" : : "r" (BootProcInfo.pf.Available)); /* Set live value */ |
55e303ae | 207 | } |
de355530 | 208 | |
55e303ae A |
209 | if (!PE_parse_boot_arg("fn", &forcenap)) forcenap = 0; /* If force nap not set, make 0 */ |
210 | else { | |
3a60a9f5 A |
211 | if(forcenap < 2) forcenap = forcenap + 1; /* Else set 1 for off, 2 for on */ |
212 | else forcenap = 0; /* Clear for error case */ | |
1c79356b A |
213 | } |
214 | ||
3a60a9f5 A |
215 | if (!PE_parse_boot_arg("pmsx", &pmsExperimental)) pmsExperimental = 0; /* Check if we should start in experimental power management stepper mode */ |
216 | if (!PE_parse_boot_arg("lcks", &LcksOpts)) LcksOpts = 0; /* Set lcks options */ | |
217 | if (!PE_parse_boot_arg("diag", &dgWork.dgFlags)) dgWork.dgFlags = 0; /* Set diagnostic flags */ | |
1c79356b A |
218 | if(dgWork.dgFlags & enaExpTrace) trcWork.traceMask = 0xFFFFFFFF; /* If tracing requested, enable it */ |
219 | ||
3a60a9f5 | 220 | if(PE_parse_boot_arg("ctrc", &cputrace)) { /* See if tracing is limited to a specific cpu */ |
9bccf70c A |
221 | trcWork.traceMask = (trcWork.traceMask & 0xFFFFFFF0) | (cputrace & 0xF); /* Limit to 4 */ |
222 | } | |
223 | ||
55e303ae | 224 | if(!PE_parse_boot_arg("tb", &trcWork.traceSize)) { /* See if non-default trace buffer size */ |
de355530 | 225 | #if DEBUG |
3a60a9f5 | 226 | trcWork.traceSize = 32; /* Default 32 page trace table for DEBUG */ |
55e303ae | 227 | #else |
3a60a9f5 | 228 | trcWork.traceSize = 8; /* Default 8 page trace table for RELEASE */ |
55e303ae | 229 | #endif |
de355530 | 230 | } |
de355530 | 231 | |
55e303ae A |
232 | if(trcWork.traceSize < 1) trcWork.traceSize = 1; /* Minimum size of 1 page */ |
233 | if(trcWork.traceSize > 256) trcWork.traceSize = 256; /* Maximum size of 256 pages */ | |
e5568f75 | 234 | trcWork.traceSize = trcWork.traceSize * 4096; /* Change page count to size */ |
55e303ae | 235 | |
1c79356b | 236 | if (!PE_parse_boot_arg("maxmem", &maxmem)) |
55e303ae | 237 | xmaxmem=0; |
1c79356b | 238 | else |
55e303ae | 239 | xmaxmem = (uint64_t)maxmem * (1024 * 1024); |
1c79356b | 240 | |
91447636 A |
241 | if (!PE_parse_boot_arg("wcte", &wcte)) wcte = 0; /* If write combine timer enable not supplied, make 1 */ |
242 | else wcte = (wcte != 0); /* Force to 0 or 1 */ | |
243 | ||
244 | if (!PE_parse_boot_arg("mcklog", &mckFlags)) mckFlags = 0; /* If machine check flags not specified, clear */ | |
3a60a9f5 | 245 | else if(mckFlags > 1) mckFlags = 0; /* If bogus, clear */ |
91447636 A |
246 | |
247 | if (!PE_parse_boot_arg("ht_shift", &hash_table_shift)) /* should we use a non-default hash table size? */ | |
248 | hash_table_shift = 0; /* no, use default size */ | |
249 | ||
250 | /* | |
251 | * VM initialization, after this we're using page tables... | |
252 | */ | |
1c79356b | 253 | |
55e303ae A |
254 | ppc_vm_init(xmaxmem, args); |
255 | ||
91447636 A |
256 | if(BootProcInfo.pf.Available & pf64Bit) { /* Are we on a 64-bit machine */ |
257 | ||
258 | if(!wcte) { | |
259 | (void)ml_scom_read(GUSModeReg << 8, &scdata); /* Get GUS mode register */ | |
260 | scdata = scdata | GUSMstgttoff; /* Disable the NCU store gather timer */ | |
261 | (void)ml_scom_write(GUSModeReg << 8, scdata); /* Get GUS mode register */ | |
262 | } | |
263 | ||
264 | if(PE_parse_boot_arg("mcksoft", &mcksoft)) { /* Have they supplied "machine check software recovery? */ | |
265 | newhid = BootProcInfo.pf.pfHID5; /* Get the old HID5 */ | |
266 | if(mcksoft < 2) { | |
e5568f75 | 267 | newhid &= 0xFFFFFFFFFFFFDFFFULL; /* Clear the old one */ |
91447636 A |
268 | newhid |= (mcksoft & 1) << 13; /* Set new value to enable machine check recovery */ |
269 | BootProcInfo.pf.pfHID5 = newhid; /* Set the new one */ | |
e5568f75 A |
270 | hid5set64(newhid); /* Set the hid for this processir */ |
271 | } | |
272 | } | |
273 | } | |
3a60a9f5 | 274 | |
1c79356b A |
275 | machine_startup(args); |
276 | } | |
277 | ||
91447636 A |
278 | /* |
279 | * Routine: ppc_init_cpu | |
280 | * Function: | |
281 | */ | |
282 | void | |
1c79356b | 283 | ppc_init_cpu( |
91447636 | 284 | struct per_proc_info *proc_info) |
1c79356b | 285 | { |
91447636 | 286 | uint64_t scdata; |
1c79356b | 287 | |
55e303ae A |
288 | proc_info->cpu_flags &= ~SleepState; |
289 | ||
91447636 A |
290 | if((BootProcInfo.pf.Available & pf64Bit) && !wcte) { /* Should we disable the store gather timer? */ |
291 | (void)ml_scom_read(GUSModeReg << 8, &scdata); /* Get GUS mode register */ | |
292 | scdata = scdata | GUSMstgttoff; /* Disable the NCU store gather timer */ | |
293 | (void)ml_scom_write(GUSModeReg << 8, scdata); /* Get GUS mode register */ | |
294 | } | |
295 | ||
1c79356b | 296 | cpu_init(); |
55e303ae | 297 | |
1c79356b A |
298 | slave_main(); |
299 | } |