[apple/xnu.git] / osfmk / i386 / mp.h

/*
 * Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_LICENSE_HEADER_START@
 * 
 * The contents of this file constitute Original Code as defined in and
 * are subject to the Apple Public Source License Version 1.1 (the
 * "License").  You may not use this file except in compliance with the
 * License.  Please obtain a copy of the License at
 * http://www.apple.com/publicsource and read it before using this file.
 * 
 * This Original Code and all software distributed under the License are
 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
 * License for the specific language governing rights and limitations
 * under the License.
 * 
 * @APPLE_LICENSE_HEADER_END@
 */
/*
 * @OSF_COPYRIGHT@
 */
/* 
 * Mach Operating System
 * Copyright (c) 1991,1990 Carnegie Mellon University
 * All Rights Reserved.
 * 
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 * 
 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 * 
 * Carnegie Mellon requests users of this software to return to
 * 
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 * 
 * any improvements or extensions that they make and grant Carnegie Mellon
 * the rights to redistribute these changes.
 */

/*
 */
#ifdef	KERNEL_PRIVATE

#ifndef _I386AT_MP_H_
#define _I386AT_MP_H_

#ifndef	DEBUG
#include <debug.h>
#endif
//#define	MP_DEBUG 1

#include <i386/apic.h>
#include <i386/mp_events.h>

#define LAPIC_ID_MAX	(LAPIC_ID_MASK)

#define MAX_CPUS	(LAPIC_ID_MAX + 1)

#ifndef	ASSEMBLER
#include <sys/cdefs.h>
#include <mach/boolean.h>
#include <mach/kern_return.h>
#include <mach/i386/thread_status.h>

__BEGIN_DECLS

extern kern_return_t intel_startCPU(int slot_num);
extern void i386_init_slave(void);
extern void smp_init(void);

extern void cpu_interrupt(int cpu);

extern void lapic_init(void);
extern void lapic_shutdown(void);
extern void lapic_smm_restore(void);
extern boolean_t lapic_probe(void);
extern void lapic_dump(void);
extern int  lapic_interrupt(int interrupt, x86_saved_state_t *state);
extern void lapic_end_of_interrupt(void);
extern int  lapic_to_cpu[];
extern int  cpu_to_lapic[];
extern int  lapic_interrupt_base;
extern void lapic_cpu_map(int lapic, int cpu_num);
extern uint32_t ml_get_apicid(uint32_t cpu);

extern void lapic_set_timer(
		boolean_t		interrupt,
		lapic_timer_mode_t	mode,
		lapic_timer_divide_t 	divisor,
		lapic_timer_count_t	initial_count);

extern void lapic_get_timer(
		lapic_timer_mode_t	*mode,
		lapic_timer_divide_t	*divisor,
		lapic_timer_count_t	*initial_count,
		lapic_timer_count_t	*current_count);

typedef	void (*i386_intr_func_t)(void *);
extern void lapic_set_timer_func(i386_intr_func_t func);
extern void lapic_set_pmi_func(i386_intr_func_t func);
extern void lapic_set_thermal_func(i386_intr_func_t func);

__END_DECLS

/*
 * By default, use high vectors to leave vector space for systems
 * with multiple I/O APIC's. However some systems that boot with
 * local APIC disabled will hang in SMM when vectors greater than
 * 0x5F are used. Those systems are not expected to have I/O APIC
 * so 16 (0x50 - 0x40) vectors for legacy PIC support is perfect.
 */
#define LAPIC_DEFAULT_INTERRUPT_BASE	0xD0
#define LAPIC_REDUCED_INTERRUPT_BASE	0x50
/*
 * Specific lapic interrupts are relative to this base
 * in priority order from high to low:
 */

#define LAPIC_PERFCNT_INTERRUPT		0xF
#define LAPIC_TIMER_INTERRUPT		0xE
#define LAPIC_INTERPROCESSOR_INTERRUPT	0xD
#define LAPIC_THERMAL_INTERRUPT		0xC
#define LAPIC_ERROR_INTERRUPT		0xB
#define LAPIC_SPURIOUS_INTERRUPT	0xA
/* The vector field is ignored for NMI interrupts via the LAPIC
 * or otherwise, so this is not an offset from the interrupt
 * base.
 */
#define LAPIC_NMI_INTERRUPT		0x2

#define LAPIC_REG(reg) \
	(*((volatile uint32_t *)(lapic_start + LAPIC_##reg)))
#define LAPIC_REG_OFFSET(reg,off) \
	(*((volatile uint32_t *)(lapic_start + LAPIC_##reg + (off))))

#define LAPIC_VECTOR(src) \
	(lapic_interrupt_base + LAPIC_##src##_INTERRUPT)

#define LAPIC_ISR_IS_SET(base,src) \
	(LAPIC_REG_OFFSET(ISR_BASE,((base+LAPIC_##src##_INTERRUPT)/32)*0x10) & \
		(1 <<((base + LAPIC_##src##_INTERRUPT)%32)))

extern vm_offset_t	lapic_start;

#endif	/* ASSEMBLER */

#define CPU_NUMBER(r)				\
	movl	%gs:CPU_NUMBER_GS,r

#define CPU_NUMBER_FROM_LAPIC(r)		\
    	movl	EXT(lapic_id),r;		\
    	movl	0(r),r;				\
    	shrl	$(LAPIC_ID_SHIFT),r;		\
    	andl	$(LAPIC_ID_MASK),r;		\
	movl	EXT(lapic_to_cpu)(,r,4),r


/* word describing the reason for the interrupt, one per cpu */

#ifndef	ASSEMBLER
#include <kern/lock.h>

extern	unsigned int	real_ncpus;		/* real number of cpus */
extern	unsigned int	max_ncpus;		/* max number of cpus */
decl_simple_lock_data(extern,kdb_lock)	/* kdb lock		*/

__BEGIN_DECLS

extern  void	console_init(void);
extern	void	*console_cpu_alloc(boolean_t boot_cpu);
extern	void	console_cpu_free(void *console_buf);

extern	int	kdb_cpu;		/* current cpu running kdb	*/
extern	int	kdb_debug;
extern	int	kdb_active[];

extern	volatile boolean_t mp_kdp_trap;
extern	void	mp_kdp_enter(void);
extern	void	mp_kdp_exit(void);

#if MACH_KDB
extern void mp_kdb_exit(void);
#endif

/*
 * All cpu rendezvous:
 */
extern void mp_rendezvous(
		void (*setup_func)(void *),
		void (*action_func)(void *),
		void (*teardown_func)(void *),
		void *arg);
extern void mp_rendezvous_no_intrs(
		void (*action_func)(void *),
		void *arg);
extern void mp_rendezvous_break_lock(void);

__END_DECLS

#if MP_DEBUG
typedef struct {
	uint64_t	time;
	int		cpu;
	mp_event_t	event;
} cpu_signal_event_t;

#define	LOG_NENTRIES	100
typedef struct {
	uint64_t		count[MP_LAST];
	int			next_entry;
	cpu_signal_event_t	entry[LOG_NENTRIES];
} cpu_signal_event_log_t;

extern cpu_signal_event_log_t	*cpu_signal[];
extern cpu_signal_event_log_t	*cpu_handle[];

#define DBGLOG(log,_cpu,_event) {					\
	boolean_t		spl = ml_set_interrupts_enabled(FALSE);	\
	cpu_signal_event_log_t	*logp = log[cpu_number()];		\
	int			next = logp->next_entry;		\
	cpu_signal_event_t	*eventp = &logp->entry[next];		\
									\
	logp->count[_event]++;						\
									\
	eventp->time = rdtsc64();					\
	eventp->cpu = _cpu;						\
	eventp->event = _event;						\
	if (next == (LOG_NENTRIES - 1))					\
		logp->next_entry = 0;					\
	else								\
		logp->next_entry++;					\
									\
	(void) ml_set_interrupts_enabled(spl);				\
}

#define DBGLOG_CPU_INIT(cpu)	{					\
	cpu_signal_event_log_t	**sig_logpp = &cpu_signal[cpu];		\
	cpu_signal_event_log_t	**hdl_logpp = &cpu_handle[cpu];		\
									\
	if (*sig_logpp == NULL &&					\
		kmem_alloc(kernel_map,					\
			(vm_offset_t *) sig_logpp,			\
			sizeof(cpu_signal_event_log_t)) != KERN_SUCCESS)\
		panic("DBGLOG_CPU_INIT cpu_signal allocation failed\n");\
	bzero(*sig_logpp, sizeof(cpu_signal_event_log_t));		\
	if (*hdl_logpp == NULL &&					\
		kmem_alloc(kernel_map,					\
			(vm_offset_t *) hdl_logpp,			\
			sizeof(cpu_signal_event_log_t)) != KERN_SUCCESS)\
		panic("DBGLOG_CPU_INIT cpu_handle allocation failed\n");\
	bzero(*sig_logpp, sizeof(cpu_signal_event_log_t));		\
}
#else	/* MP_DEBUG */
#define DBGLOG(log,_cpu,_event)
#define DBGLOG_CPU_INIT(cpu)
#endif	/* MP_DEBUG */

#endif	/* ASSEMBLER */

#define i_bit(bit, word)	((long)(*(word)) & ((long)1 << (bit)))


/* 
 *	Device driver synchronization. 
 *
 *	at386_io_lock(op) and at386_io_unlock() are called
 *	by device drivers when accessing H/W. The underlying 
 *	Processing is machine dependant. But the op argument
 *	to the at386_io_lock is generic
 */

#define MP_DEV_OP_MAX	  4
#define MP_DEV_WAIT	  MP_DEV_OP_MAX	/* Wait for the lock */

/*
 * If the caller specifies an op value different than MP_DEV_WAIT, the
 * at386_io_lock function must return true if lock was successful else
 * false
 */

#define MP_DEV_OP_START 0	/* If lock busy, register a pending start op */
#define MP_DEV_OP_INTR	1	/* If lock busy, register a pending intr */
#define MP_DEV_OP_TIMEO	2	/* If lock busy, register a pending timeout */
#define MP_DEV_OP_CALLB	3	/* If lock busy, register a pending callback */

#if	MACH_RT
#define _DISABLE_PREEMPTION 					\
	incl	%gs:CPU_PREEMPTION_LEVEL

#define _ENABLE_PREEMPTION 					\
	decl	%gs:CPU_PREEMPTION_LEVEL		;	\
	jne	9f					;	\
	pushl	%eax					;	\
	pushl	%ecx					;	\
	pushl	%edx					;	\
	call	EXT(kernel_preempt_check)		;	\
	popl	%edx					;	\
	popl	%ecx					;	\
	popl	%eax					;	\
9:	

#define _ENABLE_PREEMPTION_NO_CHECK				\
	decl	%gs:CPU_PREEMPTION_LEVEL

#if	MACH_ASSERT
#define DISABLE_PREEMPTION					\
	pushl	%eax;						\
	pushl	%ecx;						\
	pushl	%edx;						\
	call	EXT(_disable_preemption);			\
	popl	%edx;						\
	popl	%ecx;						\
	popl	%eax
#define ENABLE_PREEMPTION					\
	pushl	%eax;						\
	pushl	%ecx;						\
	pushl	%edx;						\
	call	EXT(_enable_preemption);			\
	popl	%edx;						\
	popl	%ecx;						\
	popl	%eax
#define ENABLE_PREEMPTION_NO_CHECK				\
	pushl	%eax;						\
	pushl	%ecx;						\
	pushl	%edx;						\
	call	EXT(_enable_preemption_no_check);		\
	popl	%edx;						\
	popl	%ecx;						\
	popl	%eax
#define MP_DISABLE_PREEMPTION					\
	pushl	%eax;						\
	pushl	%ecx;						\
	pushl	%edx;						\
	call	EXT(_mp_disable_preemption);			\
	popl	%edx;						\
	popl	%ecx;						\
	popl	%eax
#define MP_ENABLE_PREEMPTION					\
	pushl	%eax;						\
	pushl	%ecx;						\
	pushl	%edx;						\
	call	EXT(_mp_enable_preemption);			\
	popl	%edx;						\
	popl	%ecx;						\
	popl	%eax
#define MP_ENABLE_PREEMPTION_NO_CHECK				\
	pushl	%eax;						\
	pushl	%ecx;						\
	pushl	%edx;						\
	call	EXT(_mp_enable_preemption_no_check);		\
	popl	%edx;						\
	popl	%ecx;						\
	popl	%eax
#else	/* MACH_ASSERT */
#define DISABLE_PREEMPTION		_DISABLE_PREEMPTION
#define ENABLE_PREEMPTION		_ENABLE_PREEMPTION
#define ENABLE_PREEMPTION_NO_CHECK	_ENABLE_PREEMPTION_NO_CHECK
#define MP_DISABLE_PREEMPTION		_DISABLE_PREEMPTION
#define MP_ENABLE_PREEMPTION		_ENABLE_PREEMPTION
#define MP_ENABLE_PREEMPTION_NO_CHECK 	_ENABLE_PREEMPTION_NO_CHECK
#endif	/* MACH_ASSERT */

#else	/* MACH_RT */
#define DISABLE_PREEMPTION
#define ENABLE_PREEMPTION
#define ENABLE_PREEMPTION_NO_CHECK
#define MP_DISABLE_PREEMPTION
#define MP_ENABLE_PREEMPTION
#define MP_ENABLE_PREEMPTION_NO_CHECK
#endif	/* MACH_RT */

#endif /* _I386AT_MP_H_ */

#endif /* KERNEL_PRIVATE */
Commit	Line	Data
1c79356b	1	/*
91447636	2	* Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved.
1c79356b	3	*
6601e61a	4	* @APPLE_LICENSE_HEADER_START@
1c79356b	5	*
6601e61a A	6	* The contents of this file constitute Original Code as defined in and
	7	* are subject to the Apple Public Source License Version 1.1 (the
	8	* "License"). You may not use this file except in compliance with the
	9	* License. Please obtain a copy of the License at
	10	* http://www.apple.com/publicsource and read it before using this file.
8f6c56a5	11	*
6601e61a A	12	* This Original Code and all software distributed under the License are
6601e61a A	13	* distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5 A	14	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
8f6c56a5 A	15	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
6601e61a A	16	* FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
	17	* License for the specific language governing rights and limitations
	18	* under the License.
8f6c56a5	19	*
6601e61a	20	* @APPLE_LICENSE_HEADER_END@
1c79356b A	21	*/
	22	/*
	23	* @OSF_COPYRIGHT@
	24	*/
	25	/*
	26	* Mach Operating System
	27	* Copyright (c) 1991,1990 Carnegie Mellon University
	28	* All Rights Reserved.
	29	*
	30	* Permission to use, copy, modify and distribute this software and its
	31	* documentation is hereby granted, provided that both the copyright
	32	* notice and this permission notice appear in all copies of the
	33	* software, derivative works or modified versions, and any portions
	34	* thereof, and that both notices appear in supporting documentation.
	35	*
	36	* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
	37	* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
	38	* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
	39	*
	40	* Carnegie Mellon requests users of this software to return to
	41	*
	42	* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
	43	* School of Computer Science
	44	* Carnegie Mellon University
	45	* Pittsburgh PA 15213-3890
	46	*
	47	* any improvements or extensions that they make and grant Carnegie Mellon
	48	* the rights to redistribute these changes.
	49	*/
	50
	51	/*
	52	*/
91447636	53	#ifdef KERNEL_PRIVATE
1c79356b A	54
	55	#ifndef _I386AT_MP_H_
	56	#define _I386AT_MP_H_
	57
55e303ae A	58	#ifndef DEBUG
	59	#include <debug.h>
	60	#endif
91447636	61	//#define MP_DEBUG 1
55e303ae	62
1c79356b	63	#include <i386/apic.h>
55e303ae A	64	#include <i386/mp_events.h>
55e303ae A	65
91447636	66	#define LAPIC_ID_MAX (LAPIC_ID_MASK)
55e303ae	67
91447636	68	#define MAX_CPUS (LAPIC_ID_MAX + 1)
55e303ae A	69
55e303ae A	70	#ifndef ASSEMBLER
91447636 A	71	#include <sys/cdefs.h>
	72	#include <mach/boolean.h>
	73	#include <mach/kern_return.h>
0c530ab8	74	#include <mach/i386/thread_status.h>
91447636 A	75
	76	__BEGIN_DECLS
	77
	78	extern kern_return_t intel_startCPU(int slot_num);
	79	extern void i386_init_slave(void);
	80	extern void smp_init(void);
	81
	82	extern void cpu_interrupt(int cpu);
	83
	84	extern void lapic_init(void);
	85	extern void lapic_shutdown(void);
	86	extern void lapic_smm_restore(void);
	87	extern boolean_t lapic_probe(void);
55e303ae	88	extern void lapic_dump(void);
0c530ab8	89	extern int lapic_interrupt(int interrupt, x86_saved_state_t *state);
91447636	90	extern void lapic_end_of_interrupt(void);
55e303ae A	91	extern int lapic_to_cpu[];
55e303ae A	92	extern int cpu_to_lapic[];
91447636	93	extern int lapic_interrupt_base;
55e303ae	94	extern void lapic_cpu_map(int lapic, int cpu_num);
0c530ab8	95	extern uint32_t ml_get_apicid(uint32_t cpu);
91447636 A	96
	97	extern void lapic_set_timer(
	98	boolean_t interrupt,
	99	lapic_timer_mode_t mode,
	100	lapic_timer_divide_t divisor,
	101	lapic_timer_count_t initial_count);
	102
	103	extern void lapic_get_timer(
	104	lapic_timer_mode_t *mode,
	105	lapic_timer_divide_t *divisor,
	106	lapic_timer_count_t *initial_count,
	107	lapic_timer_count_t *current_count);
	108
	109	typedef void (i386_intr_func_t)(void );
	110	extern void lapic_set_timer_func(i386_intr_func_t func);
	111	extern void lapic_set_pmi_func(i386_intr_func_t func);
0c530ab8	112	extern void lapic_set_thermal_func(i386_intr_func_t func);
91447636 A	113
	114	__END_DECLS
	115
0c530ab8 A	116	/*
	117	* By default, use high vectors to leave vector space for systems
	118	* with multiple I/O APIC's. However some systems that boot with
	119	* local APIC disabled will hang in SMM when vectors greater than
	120	* 0x5F are used. Those systems are not expected to have I/O APIC
	121	* so 16 (0x50 - 0x40) vectors for legacy PIC support is perfect.
	122	*/
	123	#define LAPIC_DEFAULT_INTERRUPT_BASE 0xD0
	124	#define LAPIC_REDUCED_INTERRUPT_BASE 0x50
	125	/*
	126	* Specific lapic interrupts are relative to this base
	127	* in priority order from high to low:
	128	*/
	129
	130	#define LAPIC_PERFCNT_INTERRUPT 0xF
	131	#define LAPIC_TIMER_INTERRUPT 0xE
	132	#define LAPIC_INTERPROCESSOR_INTERRUPT 0xD
	133	#define LAPIC_THERMAL_INTERRUPT 0xC
	134	#define LAPIC_ERROR_INTERRUPT 0xB
	135	#define LAPIC_SPURIOUS_INTERRUPT 0xA
	136	/* The vector field is ignored for NMI interrupts via the LAPIC
	137	* or otherwise, so this is not an offset from the interrupt
	138	* base.
	139	*/
	140	#define LAPIC_NMI_INTERRUPT 0x2
	141
	142	#define LAPIC_REG(reg) \
	143	(((volatile uint32_t )(lapic_start + LAPIC_##reg)))
	144	#define LAPIC_REG_OFFSET(reg,off) \
	145	(((volatile uint32_t )(lapic_start + LAPIC_##reg + (off))))
	146
	147	#define LAPIC_VECTOR(src) \
	148	(lapic_interrupt_base + LAPIC_##src##_INTERRUPT)
	149
	150	#define LAPIC_ISR_IS_SET(base,src) \
	151	(LAPIC_REG_OFFSET(ISR_BASE,((base+LAPIC_##src##_INTERRUPT)/32)*0x10) & \
	152	(1 <<((base + LAPIC_##src##_INTERRUPT)%32)))
	153
	154	extern vm_offset_t lapic_start;
	155
55e303ae	156	#endif /* ASSEMBLER */
1c79356b	157
55e303ae	158	#define CPU_NUMBER(r) \
91447636 A	159	movl %gs:CPU_NUMBER_GS,r
	160
	161	#define CPU_NUMBER_FROM_LAPIC(r) \
55e303ae A	162	movl EXT(lapic_id),r; \
	163	movl 0(r),r; \
	164	shrl $(LAPIC_ID_SHIFT),r; \
	165	andl $(LAPIC_ID_MASK),r; \
	166	movl EXT(lapic_to_cpu)(,r,4),r
1c79356b A	167
1c79356b A	168
1c79356b A	169	/* word describing the reason for the interrupt, one per cpu */
	170
	171	#ifndef ASSEMBLER
	172	#include <kern/lock.h>
91447636 A	173
	174	extern unsigned int real_ncpus; /* real number of cpus */
	175	extern unsigned int max_ncpus; /* max number of cpus */
1c79356b	176	decl_simple_lock_data(extern,kdb_lock) /* kdb lock */
91447636 A	177
	178	__BEGIN_DECLS
	179
	180	extern void console_init(void);
	181	extern void *console_cpu_alloc(boolean_t boot_cpu);
	182	extern void console_cpu_free(void *console_buf);
1c79356b A	183
	184	extern int kdb_cpu; /* current cpu running kdb */
	185	extern int kdb_debug;
1c79356b	186	extern int kdb_active[];
55e303ae A	187
55e303ae A	188	extern volatile boolean_t mp_kdp_trap;
91447636 A	189	extern void mp_kdp_enter(void);
91447636 A	190	extern void mp_kdp_exit(void);
55e303ae	191
0c530ab8 A	192	#if MACH_KDB
	193	extern void mp_kdb_exit(void);
	194	#endif
	195
55e303ae A	196	/*
	197	* All cpu rendezvous:
	198	*/
0c530ab8 A	199	extern void mp_rendezvous(
	200	void (setup_func)(void ),
	201	void (action_func)(void ),
	202	void (teardown_func)(void ),
	203	void *arg);
	204	extern void mp_rendezvous_no_intrs(
	205	void (action_func)(void ),
	206	void *arg);
	207	extern void mp_rendezvous_break_lock(void);
55e303ae	208
91447636 A	209	__END_DECLS
91447636 A	210
55e303ae A	211	#if MP_DEBUG
	212	typedef struct {
	213	uint64_t time;
	214	int cpu;
	215	mp_event_t event;
	216	} cpu_signal_event_t;
	217
	218	#define LOG_NENTRIES 100
	219	typedef struct {
	220	uint64_t count[MP_LAST];
	221	int next_entry;
	222	cpu_signal_event_t entry[LOG_NENTRIES];
	223	} cpu_signal_event_log_t;
	224
91447636 A	225	extern cpu_signal_event_log_t *cpu_signal[];
91447636 A	226	extern cpu_signal_event_log_t *cpu_handle[];
55e303ae A	227
55e303ae A	228	#define DBGLOG(log,_cpu,_event) { \
91447636 A	229	boolean_t spl = ml_set_interrupts_enabled(FALSE); \
91447636 A	230	cpu_signal_event_log_t *logp = log[cpu_number()]; \
55e303ae A	231	int next = logp->next_entry; \
55e303ae A	232	cpu_signal_event_t *eventp = &logp->entry[next]; \
55e303ae A	233	\
	234	logp->count[_event]++; \
	235	\
	236	eventp->time = rdtsc64(); \
	237	eventp->cpu = _cpu; \
	238	eventp->event = _event; \
	239	if (next == (LOG_NENTRIES - 1)) \
	240	logp->next_entry = 0; \
	241	else \
	242	logp->next_entry++; \
	243	\
	244	(void) ml_set_interrupts_enabled(spl); \
	245	}
91447636 A	246
	247	#define DBGLOG_CPU_INIT(cpu) { \
	248	cpu_signal_event_log_t **sig_logpp = &cpu_signal[cpu]; \
	249	cpu_signal_event_log_t **hdl_logpp = &cpu_handle[cpu]; \
	250	\
	251	if (*sig_logpp == NULL && \
	252	kmem_alloc(kernel_map, \
	253	(vm_offset_t *) sig_logpp, \
	254	sizeof(cpu_signal_event_log_t)) != KERN_SUCCESS)\
	255	panic("DBGLOG_CPU_INIT cpu_signal allocation failed\n");\
	256	bzero(*sig_logpp, sizeof(cpu_signal_event_log_t)); \
	257	if (*hdl_logpp == NULL && \
	258	kmem_alloc(kernel_map, \
	259	(vm_offset_t *) hdl_logpp, \
	260	sizeof(cpu_signal_event_log_t)) != KERN_SUCCESS)\
	261	panic("DBGLOG_CPU_INIT cpu_handle allocation failed\n");\
	262	bzero(*sig_logpp, sizeof(cpu_signal_event_log_t)); \
	263	}
55e303ae A	264	#else /* MP_DEBUG */
55e303ae A	265	#define DBGLOG(log,_cpu,_event)
91447636	266	#define DBGLOG_CPU_INIT(cpu)
55e303ae A	267	#endif /* MP_DEBUG */
55e303ae A	268
1c79356b A	269	#endif /* ASSEMBLER */
	270
	271	#define i_bit(bit, word) ((long)(*(word)) & ((long)1 << (bit)))
	272
	273
	274	/*
	275	* Device driver synchronization.
	276	*
	277	* at386_io_lock(op) and at386_io_unlock() are called
	278	* by device drivers when accessing H/W. The underlying
	279	* Processing is machine dependant. But the op argument
	280	* to the at386_io_lock is generic
	281	*/
	282
	283	#define MP_DEV_OP_MAX 4
	284	#define MP_DEV_WAIT MP_DEV_OP_MAX /* Wait for the lock */
	285
	286	/*
	287	* If the caller specifies an op value different than MP_DEV_WAIT, the
	288	* at386_io_lock function must return true if lock was successful else
	289	* false
	290	*/
	291
	292	#define MP_DEV_OP_START 0 /* If lock busy, register a pending start op */
	293	#define MP_DEV_OP_INTR 1 /* If lock busy, register a pending intr */
	294	#define MP_DEV_OP_TIMEO 2 /* If lock busy, register a pending timeout */
	295	#define MP_DEV_OP_CALLB 3 /* If lock busy, register a pending callback */
	296
1c79356b	297	#if MACH_RT
91447636 A	298	#define _DISABLE_PREEMPTION \
91447636 A	299	incl %gs:CPU_PREEMPTION_LEVEL
1c79356b	300
91447636 A	301	#define _ENABLE_PREEMPTION \
91447636 A	302	decl %gs:CPU_PREEMPTION_LEVEL ; \
1c79356b A	303	jne 9f ; \
	304	pushl %eax ; \
	305	pushl %ecx ; \
	306	pushl %edx ; \
	307	call EXT(kernel_preempt_check) ; \
	308	popl %edx ; \
	309	popl %ecx ; \
	310	popl %eax ; \
	311	9:
	312
91447636 A	313	#define _ENABLE_PREEMPTION_NO_CHECK \
91447636 A	314	decl %gs:CPU_PREEMPTION_LEVEL
1c79356b A	315
1c79356b A	316	#if MACH_ASSERT
91447636	317	#define DISABLE_PREEMPTION \
1c79356b A	318	pushl %eax; \
	319	pushl %ecx; \
	320	pushl %edx; \
	321	call EXT(_disable_preemption); \
	322	popl %edx; \
	323	popl %ecx; \
	324	popl %eax
91447636	325	#define ENABLE_PREEMPTION \
1c79356b A	326	pushl %eax; \
	327	pushl %ecx; \
	328	pushl %edx; \
	329	call EXT(_enable_preemption); \
	330	popl %edx; \
	331	popl %ecx; \
	332	popl %eax
91447636	333	#define ENABLE_PREEMPTION_NO_CHECK \
1c79356b A	334	pushl %eax; \
	335	pushl %ecx; \
	336	pushl %edx; \
	337	call EXT(_enable_preemption_no_check); \
	338	popl %edx; \
	339	popl %ecx; \
	340	popl %eax
91447636	341	#define MP_DISABLE_PREEMPTION \
1c79356b A	342	pushl %eax; \
	343	pushl %ecx; \
	344	pushl %edx; \
	345	call EXT(_mp_disable_preemption); \
	346	popl %edx; \
	347	popl %ecx; \
	348	popl %eax
91447636	349	#define MP_ENABLE_PREEMPTION \
1c79356b A	350	pushl %eax; \
	351	pushl %ecx; \
	352	pushl %edx; \
	353	call EXT(_mp_enable_preemption); \
	354	popl %edx; \
	355	popl %ecx; \
	356	popl %eax
91447636	357	#define MP_ENABLE_PREEMPTION_NO_CHECK \
1c79356b A	358	pushl %eax; \
	359	pushl %ecx; \
	360	pushl %edx; \
	361	call EXT(_mp_enable_preemption_no_check); \
	362	popl %edx; \
	363	popl %ecx; \
	364	popl %eax
1c79356b	365	#else /* MACH_ASSERT */
91447636 A	366	#define DISABLE_PREEMPTION _DISABLE_PREEMPTION
	367	#define ENABLE_PREEMPTION _ENABLE_PREEMPTION
	368	#define ENABLE_PREEMPTION_NO_CHECK _ENABLE_PREEMPTION_NO_CHECK
	369	#define MP_DISABLE_PREEMPTION _DISABLE_PREEMPTION
	370	#define MP_ENABLE_PREEMPTION _ENABLE_PREEMPTION
	371	#define MP_ENABLE_PREEMPTION_NO_CHECK _ENABLE_PREEMPTION_NO_CHECK
1c79356b A	372	#endif /* MACH_ASSERT */
	373
	374	#else /* MACH_RT */
91447636 A	375	#define DISABLE_PREEMPTION
	376	#define ENABLE_PREEMPTION
	377	#define ENABLE_PREEMPTION_NO_CHECK
	378	#define MP_DISABLE_PREEMPTION
	379	#define MP_ENABLE_PREEMPTION
	380	#define MP_ENABLE_PREEMPTION_NO_CHECK
1c79356b A	381	#endif /* MACH_RT */
	382
	383	#endif /* _I386AT_MP_H_ */
91447636 A	384
91447636 A	385	#endif /* KERNEL_PRIVATE */