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1c79356b 1/*
91447636 2 * Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved.
1c79356b 3 *
6601e61a 4 * @APPLE_LICENSE_HEADER_START@
1c79356b 5 *
6601e61a
A
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
8f6c56a5 11 *
6601e61a
A
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5
A
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
6601e61a
A
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
8f6c56a5 19 *
6601e61a 20 * @APPLE_LICENSE_HEADER_END@
1c79356b
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21 */
22/*
23 * @OSF_COPYRIGHT@
24 */
25/*
26 * Mach Operating System
27 * Copyright (c) 1991,1990 Carnegie Mellon University
28 * All Rights Reserved.
29 *
30 * Permission to use, copy, modify and distribute this software and its
31 * documentation is hereby granted, provided that both the copyright
32 * notice and this permission notice appear in all copies of the
33 * software, derivative works or modified versions, and any portions
34 * thereof, and that both notices appear in supporting documentation.
35 *
36 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
37 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
38 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
39 *
40 * Carnegie Mellon requests users of this software to return to
41 *
42 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
43 * School of Computer Science
44 * Carnegie Mellon University
45 * Pittsburgh PA 15213-3890
46 *
47 * any improvements or extensions that they make and grant Carnegie Mellon
48 * the rights to redistribute these changes.
49 */
50
51/*
52 */
91447636 53#ifdef KERNEL_PRIVATE
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54
55#ifndef _I386AT_MP_H_
56#define _I386AT_MP_H_
57
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58#ifndef DEBUG
59#include <debug.h>
60#endif
91447636 61//#define MP_DEBUG 1
55e303ae 62
1c79356b 63#include <i386/apic.h>
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64#include <i386/mp_events.h>
65
91447636 66#define LAPIC_ID_MAX (LAPIC_ID_MASK)
55e303ae 67
91447636 68#define MAX_CPUS (LAPIC_ID_MAX + 1)
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69
70#ifndef ASSEMBLER
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71#include <sys/cdefs.h>
72#include <mach/boolean.h>
73#include <mach/kern_return.h>
74
75__BEGIN_DECLS
76
77extern kern_return_t intel_startCPU(int slot_num);
78extern void i386_init_slave(void);
79extern void smp_init(void);
80
81extern void cpu_interrupt(int cpu);
82
83extern void lapic_init(void);
84extern void lapic_shutdown(void);
85extern void lapic_smm_restore(void);
86extern boolean_t lapic_probe(void);
55e303ae 87extern void lapic_dump(void);
6601e61a 88extern int lapic_interrupt(int interrupt, void *state);
91447636 89extern void lapic_end_of_interrupt(void);
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90extern int lapic_to_cpu[];
91extern int cpu_to_lapic[];
91447636 92extern int lapic_interrupt_base;
55e303ae 93extern void lapic_cpu_map(int lapic, int cpu_num);
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94
95extern void lapic_set_timer(
96 boolean_t interrupt,
97 lapic_timer_mode_t mode,
98 lapic_timer_divide_t divisor,
99 lapic_timer_count_t initial_count);
100
101extern void lapic_get_timer(
102 lapic_timer_mode_t *mode,
103 lapic_timer_divide_t *divisor,
104 lapic_timer_count_t *initial_count,
105 lapic_timer_count_t *current_count);
106
107typedef void (*i386_intr_func_t)(void *);
108extern void lapic_set_timer_func(i386_intr_func_t func);
109extern void lapic_set_pmi_func(i386_intr_func_t func);
110
111__END_DECLS
112
55e303ae 113#endif /* ASSEMBLER */
1c79356b 114
55e303ae 115#define CPU_NUMBER(r) \
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116 movl %gs:CPU_NUMBER_GS,r
117
118#define CPU_NUMBER_FROM_LAPIC(r) \
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119 movl EXT(lapic_id),r; \
120 movl 0(r),r; \
121 shrl $(LAPIC_ID_SHIFT),r; \
122 andl $(LAPIC_ID_MASK),r; \
123 movl EXT(lapic_to_cpu)(,r,4),r
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124
125
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126/* word describing the reason for the interrupt, one per cpu */
127
128#ifndef ASSEMBLER
129#include <kern/lock.h>
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130
131extern unsigned int real_ncpus; /* real number of cpus */
132extern unsigned int max_ncpus; /* max number of cpus */
1c79356b 133decl_simple_lock_data(extern,kdb_lock) /* kdb lock */
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134
135__BEGIN_DECLS
136
137extern void console_init(void);
138extern void *console_cpu_alloc(boolean_t boot_cpu);
139extern void console_cpu_free(void *console_buf);
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140
141extern int kdb_cpu; /* current cpu running kdb */
142extern int kdb_debug;
6601e61a 143extern int kdb_is_slave[];
1c79356b 144extern int kdb_active[];
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145
146extern volatile boolean_t mp_kdp_trap;
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147extern void mp_kdp_enter(void);
148extern void mp_kdp_exit(void);
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149
150/*
151 * All cpu rendezvous:
152 */
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153extern void mp_rendezvous(void (*setup_func)(void *),
154 void (*action_func)(void *),
155 void (*teardown_func)(void *),
156 void *arg);
55e303ae 157
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158__END_DECLS
159
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160#if MP_DEBUG
161typedef struct {
162 uint64_t time;
163 int cpu;
164 mp_event_t event;
165} cpu_signal_event_t;
166
167#define LOG_NENTRIES 100
168typedef struct {
169 uint64_t count[MP_LAST];
170 int next_entry;
171 cpu_signal_event_t entry[LOG_NENTRIES];
172} cpu_signal_event_log_t;
173
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174extern cpu_signal_event_log_t *cpu_signal[];
175extern cpu_signal_event_log_t *cpu_handle[];
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176
177#define DBGLOG(log,_cpu,_event) { \
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178 boolean_t spl = ml_set_interrupts_enabled(FALSE); \
179 cpu_signal_event_log_t *logp = log[cpu_number()]; \
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180 int next = logp->next_entry; \
181 cpu_signal_event_t *eventp = &logp->entry[next]; \
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182 \
183 logp->count[_event]++; \
184 \
185 eventp->time = rdtsc64(); \
186 eventp->cpu = _cpu; \
187 eventp->event = _event; \
188 if (next == (LOG_NENTRIES - 1)) \
189 logp->next_entry = 0; \
190 else \
191 logp->next_entry++; \
192 \
193 (void) ml_set_interrupts_enabled(spl); \
194}
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195
196#define DBGLOG_CPU_INIT(cpu) { \
197 cpu_signal_event_log_t **sig_logpp = &cpu_signal[cpu]; \
198 cpu_signal_event_log_t **hdl_logpp = &cpu_handle[cpu]; \
199 \
200 if (*sig_logpp == NULL && \
201 kmem_alloc(kernel_map, \
202 (vm_offset_t *) sig_logpp, \
203 sizeof(cpu_signal_event_log_t)) != KERN_SUCCESS)\
204 panic("DBGLOG_CPU_INIT cpu_signal allocation failed\n");\
205 bzero(*sig_logpp, sizeof(cpu_signal_event_log_t)); \
206 if (*hdl_logpp == NULL && \
207 kmem_alloc(kernel_map, \
208 (vm_offset_t *) hdl_logpp, \
209 sizeof(cpu_signal_event_log_t)) != KERN_SUCCESS)\
210 panic("DBGLOG_CPU_INIT cpu_handle allocation failed\n");\
211 bzero(*sig_logpp, sizeof(cpu_signal_event_log_t)); \
212}
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213#else /* MP_DEBUG */
214#define DBGLOG(log,_cpu,_event)
91447636 215#define DBGLOG_CPU_INIT(cpu)
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216#endif /* MP_DEBUG */
217
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218#endif /* ASSEMBLER */
219
220#define i_bit(bit, word) ((long)(*(word)) & ((long)1 << (bit)))
221
222
223/*
224 * Device driver synchronization.
225 *
226 * at386_io_lock(op) and at386_io_unlock() are called
227 * by device drivers when accessing H/W. The underlying
228 * Processing is machine dependant. But the op argument
229 * to the at386_io_lock is generic
230 */
231
232#define MP_DEV_OP_MAX 4
233#define MP_DEV_WAIT MP_DEV_OP_MAX /* Wait for the lock */
234
235/*
236 * If the caller specifies an op value different than MP_DEV_WAIT, the
237 * at386_io_lock function must return true if lock was successful else
238 * false
239 */
240
241#define MP_DEV_OP_START 0 /* If lock busy, register a pending start op */
242#define MP_DEV_OP_INTR 1 /* If lock busy, register a pending intr */
243#define MP_DEV_OP_TIMEO 2 /* If lock busy, register a pending timeout */
244#define MP_DEV_OP_CALLB 3 /* If lock busy, register a pending callback */
245
1c79356b 246#if MACH_RT
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247#define _DISABLE_PREEMPTION \
248 incl %gs:CPU_PREEMPTION_LEVEL
1c79356b 249
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250#define _ENABLE_PREEMPTION \
251 decl %gs:CPU_PREEMPTION_LEVEL ; \
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252 jne 9f ; \
253 pushl %eax ; \
254 pushl %ecx ; \
255 pushl %edx ; \
256 call EXT(kernel_preempt_check) ; \
257 popl %edx ; \
258 popl %ecx ; \
259 popl %eax ; \
2609:
261
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262#define _ENABLE_PREEMPTION_NO_CHECK \
263 decl %gs:CPU_PREEMPTION_LEVEL
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264
265#if MACH_ASSERT
91447636 266#define DISABLE_PREEMPTION \
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267 pushl %eax; \
268 pushl %ecx; \
269 pushl %edx; \
270 call EXT(_disable_preemption); \
271 popl %edx; \
272 popl %ecx; \
273 popl %eax
91447636 274#define ENABLE_PREEMPTION \
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275 pushl %eax; \
276 pushl %ecx; \
277 pushl %edx; \
278 call EXT(_enable_preemption); \
279 popl %edx; \
280 popl %ecx; \
281 popl %eax
91447636 282#define ENABLE_PREEMPTION_NO_CHECK \
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283 pushl %eax; \
284 pushl %ecx; \
285 pushl %edx; \
286 call EXT(_enable_preemption_no_check); \
287 popl %edx; \
288 popl %ecx; \
289 popl %eax
91447636 290#define MP_DISABLE_PREEMPTION \
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291 pushl %eax; \
292 pushl %ecx; \
293 pushl %edx; \
294 call EXT(_mp_disable_preemption); \
295 popl %edx; \
296 popl %ecx; \
297 popl %eax
91447636 298#define MP_ENABLE_PREEMPTION \
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299 pushl %eax; \
300 pushl %ecx; \
301 pushl %edx; \
302 call EXT(_mp_enable_preemption); \
303 popl %edx; \
304 popl %ecx; \
305 popl %eax
91447636 306#define MP_ENABLE_PREEMPTION_NO_CHECK \
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307 pushl %eax; \
308 pushl %ecx; \
309 pushl %edx; \
310 call EXT(_mp_enable_preemption_no_check); \
311 popl %edx; \
312 popl %ecx; \
313 popl %eax
1c79356b 314#else /* MACH_ASSERT */
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315#define DISABLE_PREEMPTION _DISABLE_PREEMPTION
316#define ENABLE_PREEMPTION _ENABLE_PREEMPTION
317#define ENABLE_PREEMPTION_NO_CHECK _ENABLE_PREEMPTION_NO_CHECK
318#define MP_DISABLE_PREEMPTION _DISABLE_PREEMPTION
319#define MP_ENABLE_PREEMPTION _ENABLE_PREEMPTION
320#define MP_ENABLE_PREEMPTION_NO_CHECK _ENABLE_PREEMPTION_NO_CHECK
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321#endif /* MACH_ASSERT */
322
323#else /* MACH_RT */
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324#define DISABLE_PREEMPTION
325#define ENABLE_PREEMPTION
326#define ENABLE_PREEMPTION_NO_CHECK
327#define MP_DISABLE_PREEMPTION
328#define MP_ENABLE_PREEMPTION
329#define MP_ENABLE_PREEMPTION_NO_CHECK
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330#endif /* MACH_RT */
331
332#endif /* _I386AT_MP_H_ */
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333
334#endif /* KERNEL_PRIVATE */