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1 /*
2 * @APPLE_LICENSE_HEADER_START@
3 *
4 * Copyright (c) 2018 Apple Inc. All Rights Reserved.
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. Please obtain a copy of the License at
10 * http://www.opensource.apple.com/apsl/ and read it before using this
11 * file.
12 *
13 * The Original Code and all software distributed under the License are
14 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
15 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
16 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
18 * Please see the License for the specific language governing rights and
19 * limitations under the License.
20 *
21 * @APPLE_LICENSE_HEADER_END@
22 */
23 /********************************************************************
24 *
25 * arm64-asm.h - asm tools for arm64/arm64_32 and ROP/JOP
26 *
27 ********************************************************************/
28
29 #if __arm64__
30
31 #if __LP64__
32 // true arm64
33
34 #define SUPPORT_TAGGED_POINTERS 1
35 #define PTR .quad
36 #define PTRSIZE 8
37 #define PTRSHIFT 3 // 1<<PTRSHIFT == PTRSIZE
38 // "p" registers are pointer-sized
39 #define UXTP UXTX
40 #define p0 x0
41 #define p1 x1
42 #define p2 x2
43 #define p3 x3
44 #define p4 x4
45 #define p5 x5
46 #define p6 x6
47 #define p7 x7
48 #define p8 x8
49 #define p9 x9
50 #define p10 x10
51 #define p11 x11
52 #define p12 x12
53 #define p13 x13
54 #define p14 x14
55 #define p15 x15
56 #define p16 x16
57 #define p17 x17
58
59 // true arm64
60 #else
61 // arm64_32
62
63 #define SUPPORT_TAGGED_POINTERS 0
64 #define PTR .long
65 #define PTRSIZE 4
66 #define PTRSHIFT 2 // 1<<PTRSHIFT == PTRSIZE
67 // "p" registers are pointer-sized
68 #define UXTP UXTW
69 #define p0 w0
70 #define p1 w1
71 #define p2 w2
72 #define p3 w3
73 #define p4 w4
74 #define p5 w5
75 #define p6 w6
76 #define p7 w7
77 #define p8 w8
78 #define p9 w9
79 #define p10 w10
80 #define p11 w11
81 #define p12 w12
82 #define p13 w13
83 #define p14 w14
84 #define p15 w15
85 #define p16 w16
86 #define p17 w17
87
88 // arm64_32
89 #endif
90
91
92 #if __has_feature(ptrauth_returns)
93 // ROP
94 # define SignLR pacibsp
95 # define AuthenticateLR autibsp
96 #else
97 // not ROP
98 # define SignLR
99 # define AuthenticateLR
100 #endif
101
102 #if __has_feature(ptrauth_calls)
103 // JOP
104
105 .macro TailCallFunctionPointer
106 // $0 = function pointer value
107 braaz $0
108 .endmacro
109
110 .macro TailCallCachedImp
111 // $0 = cached imp, $1 = address of cached imp
112 brab $0, $1
113 .endmacro
114
115 .macro TailCallMethodListImp
116 // $0 = method list imp, $1 = address of method list imp
117 braa $0, $1
118 .endmacro
119
120 .macro TailCallBlockInvoke
121 // $0 = invoke function, $1 = address of invoke function
122 braa $0, $1
123 .endmacro
124
125 .macro AuthAndResignAsIMP
126 // $0 = cached imp, $1 = address of cached imp
127 autib $0, $1 // authenticate cached imp
128 paciza $0 // resign cached imp as IMP
129 .endmacro
130
131 // JOP
132 #else
133 // not JOP
134
135 .macro TailCallFunctionPointer
136 // $0 = function pointer value
137 br $0
138 .endmacro
139
140 .macro TailCallCachedImp
141 // $0 = cached imp, $1 = address of cached imp
142 br $0
143 .endmacro
144
145 .macro TailCallMethodListImp
146 // $0 = method list imp, $1 = address of method list imp
147 br $0
148 .endmacro
149
150 .macro TailCallBlockInvoke
151 // $0 = invoke function, $1 = address of invoke function
152 br $0
153 .endmacro
154
155 .macro AuthAndResignAsIMP
156 // empty
157 .endmacro
158
159 // not JOP
160 #endif
161
162 #define TailCallBlockInvoke TailCallMethodListImp
163
164
165 // __arm64__
166 #endif