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1 /*
2 * @APPLE_LICENSE_HEADER_START@
3 *
4 * Copyright (c) 2018 Apple Inc. All Rights Reserved.
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. Please obtain a copy of the License at
10 * http://www.opensource.apple.com/apsl/ and read it before using this
11 * file.
12 *
13 * The Original Code and all software distributed under the License are
14 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
15 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
16 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
18 * Please see the License for the specific language governing rights and
19 * limitations under the License.
20 *
21 * @APPLE_LICENSE_HEADER_END@
22 */
23 /********************************************************************
24 *
25 * isa.h - Definitions of isa fields for C and assembly code.
26 *
27 ********************************************************************/
28
29 #ifndef _OBJC_ISA_H_
30 #define _OBJC_ISA_H_
31
32 #include "objc-config.h"
33
34
35 #if (!SUPPORT_NONPOINTER_ISA && !SUPPORT_PACKED_ISA && !SUPPORT_INDEXED_ISA) ||\
36 ( SUPPORT_NONPOINTER_ISA && SUPPORT_PACKED_ISA && !SUPPORT_INDEXED_ISA) ||\
37 ( SUPPORT_NONPOINTER_ISA && !SUPPORT_PACKED_ISA && SUPPORT_INDEXED_ISA)
38 // good config
39 #else
40 # error bad config
41 #endif
42
43
44 #if SUPPORT_PACKED_ISA
45
46 // extra_rc must be the MSB-most field (so it matches carry/overflow flags)
47 // nonpointer must be the LSB (fixme or get rid of it)
48 // shiftcls must occupy the same bits that a real class pointer would
49 // bits + RC_ONE is equivalent to extra_rc + 1
50 // RC_HALF is the high bit of extra_rc (i.e. half of its range)
51
52 // future expansion:
53 // uintptr_t fast_rr : 1; // no r/r overrides
54 // uintptr_t lock : 2; // lock for atomic property, @synch
55 // uintptr_t extraBytes : 1; // allocated with extra bytes
56
57 # if __arm64__
58 // ARM64 simulators have a larger address space, so use the ARM64e
59 // scheme even when simulators build for ARM64-not-e.
60 # if __has_feature(ptrauth_calls) || TARGET_OS_SIMULATOR
61 # define ISA_MASK 0x007ffffffffffff8ULL
62 # define ISA_MAGIC_MASK 0x0000000000000001ULL
63 # define ISA_MAGIC_VALUE 0x0000000000000001ULL
64 # define ISA_HAS_CXX_DTOR_BIT 0
65 # define ISA_BITFIELD \
66 uintptr_t nonpointer : 1; \
67 uintptr_t has_assoc : 1; \
68 uintptr_t weakly_referenced : 1; \
69 uintptr_t shiftcls_and_sig : 52; \
70 uintptr_t has_sidetable_rc : 1; \
71 uintptr_t extra_rc : 8
72 # define RC_ONE (1ULL<<56)
73 # define RC_HALF (1ULL<<7)
74 # else
75 # define ISA_MASK 0x0000000ffffffff8ULL
76 # define ISA_MAGIC_MASK 0x000003f000000001ULL
77 # define ISA_MAGIC_VALUE 0x000001a000000001ULL
78 # define ISA_HAS_CXX_DTOR_BIT 1
79 # define ISA_BITFIELD \
80 uintptr_t nonpointer : 1; \
81 uintptr_t has_assoc : 1; \
82 uintptr_t has_cxx_dtor : 1; \
83 uintptr_t shiftcls : 33; /*MACH_VM_MAX_ADDRESS 0x1000000000*/ \
84 uintptr_t magic : 6; \
85 uintptr_t weakly_referenced : 1; \
86 uintptr_t unused : 1; \
87 uintptr_t has_sidetable_rc : 1; \
88 uintptr_t extra_rc : 19
89 # define RC_ONE (1ULL<<45)
90 # define RC_HALF (1ULL<<18)
91 # endif
92
93 # elif __x86_64__
94 # define ISA_MASK 0x00007ffffffffff8ULL
95 # define ISA_MAGIC_MASK 0x001f800000000001ULL
96 # define ISA_MAGIC_VALUE 0x001d800000000001ULL
97 # define ISA_HAS_CXX_DTOR_BIT 1
98 # define ISA_BITFIELD \
99 uintptr_t nonpointer : 1; \
100 uintptr_t has_assoc : 1; \
101 uintptr_t has_cxx_dtor : 1; \
102 uintptr_t shiftcls : 44; /*MACH_VM_MAX_ADDRESS 0x7fffffe00000*/ \
103 uintptr_t magic : 6; \
104 uintptr_t weakly_referenced : 1; \
105 uintptr_t unused : 1; \
106 uintptr_t has_sidetable_rc : 1; \
107 uintptr_t extra_rc : 8
108 # define RC_ONE (1ULL<<56)
109 # define RC_HALF (1ULL<<7)
110
111 # else
112 # error unknown architecture for packed isa
113 # endif
114
115 // SUPPORT_PACKED_ISA
116 #endif
117
118
119 #if SUPPORT_INDEXED_ISA
120
121 # if __ARM_ARCH_7K__ >= 2 || (__arm64__ && !__LP64__)
122 // armv7k or arm64_32
123
124 # define ISA_INDEX_IS_NPI_BIT 0
125 # define ISA_INDEX_IS_NPI_MASK 0x00000001
126 # define ISA_INDEX_MASK 0x0001FFFC
127 # define ISA_INDEX_SHIFT 2
128 # define ISA_INDEX_BITS 15
129 # define ISA_INDEX_COUNT (1 << ISA_INDEX_BITS)
130 # define ISA_INDEX_MAGIC_MASK 0x001E0001
131 # define ISA_INDEX_MAGIC_VALUE 0x001C0001
132 # define ISA_HAS_CXX_DTOR_BIT 1
133 # define ISA_BITFIELD \
134 uintptr_t nonpointer : 1; \
135 uintptr_t has_assoc : 1; \
136 uintptr_t indexcls : 15; \
137 uintptr_t magic : 4; \
138 uintptr_t has_cxx_dtor : 1; \
139 uintptr_t weakly_referenced : 1; \
140 uintptr_t unused : 1; \
141 uintptr_t has_sidetable_rc : 1; \
142 uintptr_t extra_rc : 7
143 # define RC_ONE (1ULL<<25)
144 # define RC_HALF (1ULL<<6)
145
146 # else
147 # error unknown architecture for indexed isa
148 # endif
149
150 // SUPPORT_INDEXED_ISA
151 #endif
152
153
154 // _OBJC_ISA_H_
155 #endif