runtime/arm64-asm.h

   1 /*
   2  * @APPLE_LICENSE_HEADER_START@
   3  *
   4  * Copyright (c) 2018 Apple Inc.  All Rights Reserved.
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. Please obtain a copy of the License at
  10  * http://www.opensource.apple.com/apsl/ and read it before using this
  11  * file.
  12  *
  13  * The Original Code and all software distributed under the License are
  14  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  15  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
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  18  * Please see the License for the specific language governing rights and
  19  * limitations under the License.
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  21  * @APPLE_LICENSE_HEADER_END@
  22  */
  23 /********************************************************************
  24  *
  25  *  arm64-asm.h - asm tools for arm64/arm64_32 and ROP/JOP
  26  *
  27  ********************************************************************/
  28
  29 #if __arm64__
  30
  31 #include "objc-config.h"
  32
  33 #if __LP64__
  34 // true arm64
  35
  36 #define SUPPORT_TAGGED_POINTERS 1
  37 #define PTR .quad
  38 #define PTRSIZE 8
  39 #define PTRSHIFT 3  // 1<<PTRSHIFT == PTRSIZE
  40 // "p" registers are pointer-sized
  41 #define UXTP UXTX
  42 #define p0  x0
  43 #define p1  x1
  44 #define p2  x2
  45 #define p3  x3
  46 #define p4  x4
  47 #define p5  x5
  48 #define p6  x6
  49 #define p7  x7
  50 #define p8  x8
  51 #define p9  x9
  52 #define p10 x10
  53 #define p11 x11
  54 #define p12 x12
  55 #define p13 x13
  56 #define p14 x14
  57 #define p15 x15
  58 #define p16 x16
  59 #define p17 x17
  60
  61 // true arm64
  62 #else
  63 // arm64_32
  64
  65 #define SUPPORT_TAGGED_POINTERS 0
  66 #define PTR .long
  67 #define PTRSIZE 4
  68 #define PTRSHIFT 2  // 1<<PTRSHIFT == PTRSIZE
  69 // "p" registers are pointer-sized
  70 #define UXTP UXTW
  71 #define p0  w0
  72 #define p1  w1
  73 #define p2  w2
  74 #define p3  w3
  75 #define p4  w4
  76 #define p5  w5
  77 #define p6  w6
  78 #define p7  w7
  79 #define p8  w8
  80 #define p9  w9
  81 #define p10 w10
  82 #define p11 w11
  83 #define p12 w12
  84 #define p13 w13
  85 #define p14 w14
  86 #define p15 w15
  87 #define p16 w16
  88 #define p17 w17
  89
  90 // arm64_32
  91 #endif
  92
  93
  94 #if __has_feature(ptrauth_returns)
  95 // ROP
  96 #   define SignLR pacibsp
  97 #   define AuthenticateLR autibsp
  98 #else
  99 // not ROP
 100 #   define SignLR
 101 #   define AuthenticateLR
 102 #endif
 103
 104 #if __has_feature(ptrauth_calls)
 105 // JOP
 106
 107 .macro TailCallFunctionPointer
 108         // $0 = function pointer value
 109         braaz   $0
 110 .endmacro
 111
 112 .macro TailCallCachedImp
 113         // $0 = cached imp, $1 = address of cached imp, $2 = SEL, $3 = isa
 114         eor     $1, $1, $2      // mix SEL into ptrauth modifier
 115         eor     $1, $1, $3  // mix isa into ptrauth modifier
 116         brab    $0, $1
 117 .endmacro
 118
 119 .macro TailCallMethodListImp
 120         // $0 = method list imp, $1 = address of method list imp
 121         braa    $0, $1
 122 .endmacro
 123
 124 .macro TailCallBlockInvoke
 125         // $0 = invoke function, $1 = address of invoke function
 126         braa    $0, $1
 127 .endmacro
 128
 129 .macro AuthAndResignAsIMP
 130         // $0 = cached imp, $1 = address of cached imp, $2 = SEL, $3 = isa
 131         // note: assumes the imp is not nil
 132         eor     $1, $1, $2      // mix SEL into ptrauth modifier
 133         eor     $1, $1, $3  // mix isa into ptrauth modifier
 134         autib   $0, $1  // authenticate cached imp
 135         ldr     xzr, [$0]       // crash if authentication failed
 136         paciza  $0              // resign cached imp as IMP
 137 .endmacro
 138
 139 .macro ExtractISA
 140         and     $0, $1, #ISA_MASK
 141 #if ISA_SIGNING_AUTH_MODE == ISA_SIGNING_STRIP
 142         xpacd   $0
 143 #elif ISA_SIGNING_AUTH_MODE == ISA_SIGNING_AUTH
 144         mov     x10, $2
 145         movk    x10, #ISA_SIGNING_DISCRIMINATOR, LSL #48
 146         autda   $0, x10
 147 #endif
 148 .endmacro
 149
 150 .macro AuthISASuper dst, addr_mutable, discriminator
 151 #if ISA_SIGNING_AUTH_MODE == ISA_SIGNING_AUTH
 152         movk    \addr_mutable, #\discriminator, LSL #48
 153         autda   \dst, \addr_mutable
 154 #elif ISA_SIGNING_AUTH_MODE == ISA_SIGNING_STRIP
 155         xpacd   \dst
 156 #endif
 157 .endmacro
 158
 159 .macro SignAsImp
 160         paciza  $0
 161 .endmacro
 162
 163 // JOP
 164 #else
 165 // not JOP
 166
 167 .macro TailCallFunctionPointer
 168         // $0 = function pointer value
 169         br      $0
 170 .endmacro
 171
 172 .macro TailCallCachedImp
 173         // $0 = cached imp, $1 = address of cached imp, $2 = SEL, $3 = isa
 174         eor     $0, $0, $3
 175         br      $0
 176 .endmacro
 177
 178 .macro TailCallMethodListImp
 179         // $0 = method list imp, $1 = address of method list imp
 180         br      $0
 181 .endmacro
 182
 183 .macro TailCallBlockInvoke
 184         // $0 = invoke function, $1 = address of invoke function
 185         br      $0
 186 .endmacro
 187
 188 .macro AuthAndResignAsIMP
 189         // $0 = cached imp, $1 = address of cached imp, $2 = SEL
 190         eor     $0, $0, $3
 191 .endmacro
 192
 193 .macro SignAsImp
 194 .endmacro
 195
 196 .macro ExtractISA
 197         and    $0, $1, #ISA_MASK
 198 .endmacro
 199
 200 // not JOP
 201 #endif
 202
 203 #define TailCallBlockInvoke TailCallMethodListImp
 204
 205
 206 // __arm64__
 207 #endif