src/hw_shims.h

   1 /*
   2  * Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_APACHE_LICENSE_HEADER_START@
   5  *
   6  * Licensed under the Apache License, Version 2.0 (the "License");
   7  * you may not use this file except in compliance with the License.
   8  * You may obtain a copy of the License at
   9  *
  10  *     http://www.apache.org/licenses/LICENSE-2.0
  11  *
  12  * Unless required by applicable law or agreed to in writing, software
  13  * distributed under the License is distributed on an "AS IS" BASIS,
  14  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  15  * See the License for the specific language governing permissions and
  16  * limitations under the License.
  17  *
  18  * @APPLE_APACHE_LICENSE_HEADER_END@
  19  */
  20
  21 /*
  22  * IMPORTANT: This header file describes INTERNAL interfaces to libdispatch
  23  * which are subject to change in future releases of Mac OS X. Any applications
  24  * relying on these interfaces WILL break.
  25  */
  26
  27 #ifndef __DISPATCH_HW_SHIMS__
  28 #define __DISPATCH_HW_SHIMS__
  29
  30 /* x86 has a 64 byte cacheline */
  31 #define DISPATCH_CACHELINE_SIZE 64
  32 #define ROUND_UP_TO_CACHELINE_SIZE(x)   (((x) + (DISPATCH_CACHELINE_SIZE - 1)) & ~(DISPATCH_CACHELINE_SIZE - 1))
  33 #define ROUND_UP_TO_VECTOR_SIZE(x)      (((x) + 15) & ~15)
  34
  35 #if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 2)
  36 // GCC generates suboptimal register pressure
  37 // LLVM does better, but doesn't support tail calls
  38 // 6248590 __sync_*() intrinsics force a gratuitous "lea" instruction, with resulting register pressure
  39 #if 0 && defined(__i386__) || defined(__x86_64__)
  40 #define dispatch_atomic_xchg(p, n)      ({ typeof(*(p)) _r; asm("xchg %0, %1" : "=r" (_r) : "m" (*(p)), "0" (n)); _r; })
  41 #else
  42 #define dispatch_atomic_xchg(p, n)      __sync_lock_test_and_set((p), (n))
  43 #endif
  44 #define dispatch_atomic_cmpxchg(p, o, n)        __sync_bool_compare_and_swap((p), (o), (n))
  45 #define dispatch_atomic_inc(p)  __sync_add_and_fetch((p), 1)
  46 #define dispatch_atomic_dec(p)  __sync_sub_and_fetch((p), 1)
  47 #define dispatch_atomic_add(p, v)       __sync_add_and_fetch((p), (v))
  48 #define dispatch_atomic_sub(p, v)       __sync_sub_and_fetch((p), (v))
  49 #define dispatch_atomic_or(p, v)        __sync_fetch_and_or((p), (v))
  50 #define dispatch_atomic_and(p, v)       __sync_fetch_and_and((p), (v))
  51 #if defined(__i386__) || defined(__x86_64__)
  52 /* GCC emits nothing for __sync_synchronize() on i386/x86_64. */
  53 #define dispatch_atomic_barrier()       __asm__ __volatile__("mfence")
  54 #else
  55 #define dispatch_atomic_barrier()       __sync_synchronize()
  56 #endif
  57 #else
  58 #error "Please upgrade to GCC 4.2 or newer."
  59 #endif
  60
  61 #if defined(__i386__) || defined(__x86_64__)
  62 #define _dispatch_hardware_pause() asm("pause")
  63 #define _dispatch_debugger() asm("int3")
  64 #else
  65 #define _dispatch_hardware_pause() asm("")
  66 #define _dispatch_debugger() asm("trap")
  67 #endif
  68 // really just a low level abort()
  69 #define _dispatch_hardware_crash() __builtin_trap()
  70
  71
  72 #endif