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1 /*
2 * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. Please obtain a copy of the License at
10 * http://www.opensource.apple.com/apsl/ and read it before using this
11 * file.
12 *
13 * The Original Code and all software distributed under the License are
14 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
15 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
16 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
18 * Please see the License for the specific language governing rights and
19 * limitations under the License.
20 *
21 * @APPLE_LICENSE_HEADER_END@
22 */
23
24 /* void _longjmp(jmp_buf env, int val); */
25
26 /* int _longjmp(jmp_buf env); */
27 /*
28 * Copyright (c) 1998 Apple Computer, Inc. All rights reserved.
29 *
30 * File: sys/ppc/_longjmp.s
31 *
32 * Implements _longjmp()
33 *
34 * History:
35 * 8 September 1998 Matt Watson (mwatson@apple.com)
36 * Created. Derived from longjmp.s
37 */
38
39 #include <architecture/ppc/asm_help.h>
40 #include "_setjmp.h"
41
42 #define VRSave 256
43
44 /* special flag bit definitions copied from /osfmk/ppc/thread_act.h */
45
46 #define floatUsedbit 1
47 #define vectorUsedbit 2
48
49
50 #if defined(__DYNAMIC__)
51 .data
52 .non_lazy_symbol_pointer
53 .align 2
54 L_memmove$non_lazy_ptr:
55 .indirect_symbol _memmove
56 .long 0
57 .non_lazy_symbol_pointer
58 .align 2
59 L__cpu_has_altivec$non_lazy_ptr:
60 .indirect_symbol __cpu_has_altivec
61 .long 0
62 .text
63 #endif
64
65 LEAF(__longjmp)
66
67 ; need to restore FPRs or VRs?
68
69 lwz r5,JMP_flags(r3)
70 lwz r6,JMP_addr_at_setjmp(r3)
71 rlwinm r7,r5,0,vectorUsedbit,vectorUsedbit
72 rlwinm r8,r5,0,floatUsedbit,floatUsedbit
73 cmpw cr1,r3,r6 ; jmp_buf still at same address?
74 cmpwi cr3,r7,0 ; set cr3 iff VRs in use (non-volatile CR)
75 cmpwi cr4,r8,0 ; set cr4 iff FPRs in use (non-volatile CR)
76 beq+ cr1,LRestoreVRs
77
78 ; jmp_buf was moved since setjmp (or is uninitialized.)
79 ; We must move VRs and FPRs to be quadword aligned at present address.
80
81 stw r3,JMP_addr_at_setjmp(r3) ; update, in case we longjmp to this again
82 mr r31,r4 ; save "val" arg across memmove
83 mr r30,r3 ; and jmp_buf ptr
84 addi r3,r3,JMP_vr_base_addr
85 addi r4,r6,JMP_vr_base_addr
86 rlwinm r3,r3,0,0,27 ; r3 <- QW aligned addr where they should be
87 rlwinm r4,r4,0,0,27 ; r4 <- QW aligned addr where they originally were
88 sub r7,r4,r6 ; r7 <- offset of VRs/FPRs within jmp_buf
89 add r4,r30,r7 ; r4 <- where they are now
90 li r5,(JMP_buf_end - JMP_vr_base_addr)
91 #if defined(__DYNAMIC__)
92 bcl 20,31,1f ; Get pic-base
93 1: mflr r12
94 addis r12, r12, ha16(L_memmove$non_lazy_ptr - 1b)
95 lwz r12, lo16(L_memmove$non_lazy_ptr - 1b)(r12)
96 mtctr r12 ; Get address left by dyld
97 bctrl
98 #else
99 bl _memmove
100 #endif
101 mr r3,r30
102 mr r4,r31
103
104 ; Restore VRs iff any
105 ; cr3 - bne if VRs
106 ; cr4 - bne if FPRs
107
108 LRestoreVRs:
109 beq+ cr3,LZeroVRSave ; no VRs
110 lwz r0,JMP_vrsave(r3)
111 addi r6,r3,JMP_vr_base_addr
112 cmpwi r0,0 ; any live VRs?
113 mtspr VRSave,r0
114 beq+ LRestoreFPRs
115 lvx v20,0,r6
116 li r7,16*1
117 lvx v21,r7,r6
118 li r7,16*2
119 lvx v22,r7,r6
120 li r7,16*3
121 lvx v23,r7,r6
122 li r7,16*4
123 lvx v24,r7,r6
124 li r7,16*5
125 lvx v25,r7,r6
126 li r7,16*6
127 lvx v26,r7,r6
128 li r7,16*7
129 lvx v27,r7,r6
130 li r7,16*8
131 lvx v28,r7,r6
132 li r7,16*9
133 lvx v29,r7,r6
134 li r7,16*10
135 lvx v30,r7,r6
136 li r7,16*11
137 lvx v31,r7,r6
138 b LRestoreFPRs ; skip zeroing VRSave
139
140 ; Zero VRSave iff Altivec is supported, but VRs were not in use
141 ; at setjmp time. This covers the case where VRs are first used after
142 ; the setjmp but before the longjmp, and where VRSave is nonzero at
143 ; the longjmp. We need to zero it now, or it will always remain
144 ; nonzero since they are sticky bits.
145
146 LZeroVRSave:
147 #if defined(__DYNAMIC__)
148 bcl 20,31,1f
149 1: mflr r9 ; get our address
150 addis r6,r9,ha16(L__cpu_has_altivec$non_lazy_ptr - 1b)
151 lwz r7,lo16(L__cpu_has_altivec$non_lazy_ptr - 1b)(r6)
152 lwz r7,0(r7) ; load the flag
153 #else
154 lis r7, ha16(__cpu_has_altivec)
155 lwz r7, lo16(__cpu_has_altivec)(r7)
156 #endif
157 cmpwi r7,0
158 li r8,0
159 beq LRestoreFPRs ; no Altivec, so skip
160 mtspr VRSave,r8
161
162 ; Restore FPRs if any
163 ; cr4 - bne iff FPRs
164
165 LRestoreFPRs:
166 beq cr4,LRestoreGPRs ; FPRs not in use at setjmp
167 addi r6,r3,JMP_fp_base_addr
168 rlwinm r6,r6,0,0,27 ; mask off low 4 bits to qw align
169 lfd f14,0*8(r6)
170 lfd f15,1*8(r6)
171 lfd f16,2*8(r6)
172 lfd f17,3*8(r6)
173 lfd f18,4*8(r6)
174 lfd f19,5*8(r6)
175 lfd f20,6*8(r6)
176 lfd f21,7*8(r6)
177 lfd f22,8*8(r6)
178 lfd f23,9*8(r6)
179 lfd f24,10*8(r6)
180 lfd f25,11*8(r6)
181 lfd f26,12*8(r6)
182 lfd f27,13*8(r6)
183 lfd f28,14*8(r6)
184 lfd f29,15*8(r6)
185 lfd f30,16*8(r6)
186 lfd f31,17*8(r6)
187
188 ; Restore GPRs
189
190 LRestoreGPRs:
191 lwz r31, JMP_r31(r3)
192 /* r1, r14-r30 */
193 lwz r1, JMP_r1 (r3)
194 lwz r2, JMP_r2 (r3)
195 lwz r13, JMP_r13(r3)
196 lwz r14, JMP_r14(r3)
197 lwz r15, JMP_r15(r3)
198 lwz r16, JMP_r16(r3)
199 lwz r17, JMP_r17(r3)
200 lwz r18, JMP_r18(r3)
201 lwz r19, JMP_r19(r3)
202 lwz r20, JMP_r20(r3)
203 lwz r21, JMP_r21(r3)
204 lwz r22, JMP_r22(r3)
205 lwz r23, JMP_r23(r3)
206 lwz r24, JMP_r24(r3)
207 lwz r25, JMP_r25(r3)
208 lwz r26, JMP_r26(r3)
209 lwz r27, JMP_r27(r3)
210 lwz r28, JMP_r28(r3)
211 lwz r29, JMP_r29(r3)
212 lwz r30, JMP_r30(r3)
213 lwz r0, JMP_cr(r3)
214 mtcrf 0xff,r0
215 lwz r0, JMP_lr(r3)
216 mtlr r0
217 lwz r0, JMP_ctr(r3) ; XXX ctr is volatile
218 mtctr r0
219 lwz r0, JMP_xer(r3) ; XXX xer is volatile
220 mtxer r0
221 mr. r3, r4
222 bnelr
223 li r3, 1
224 blr
225